JPS62177047U - - Google Patents
Info
- Publication number
- JPS62177047U JPS62177047U JP1986064833U JP6483386U JPS62177047U JP S62177047 U JPS62177047 U JP S62177047U JP 1986064833 U JP1986064833 U JP 1986064833U JP 6483386 U JP6483386 U JP 6483386U JP S62177047 U JPS62177047 U JP S62177047U
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- package
- semiconductor element
- metal
- insulating container
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000005219 brazing Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986064833U JPS62177047U (no) | 1986-04-29 | 1986-04-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986064833U JPS62177047U (no) | 1986-04-29 | 1986-04-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62177047U true JPS62177047U (no) | 1987-11-10 |
Family
ID=30901354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986064833U Pending JPS62177047U (no) | 1986-04-29 | 1986-04-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62177047U (no) |
-
1986
- 1986-04-29 JP JP1986064833U patent/JPS62177047U/ja active Pending