JPS62174349U - - Google Patents
Info
- Publication number
- JPS62174349U JPS62174349U JP6255686U JP6255686U JPS62174349U JP S62174349 U JPS62174349 U JP S62174349U JP 6255686 U JP6255686 U JP 6255686U JP 6255686 U JP6255686 U JP 6255686U JP S62174349 U JPS62174349 U JP S62174349U
- Authority
- JP
- Japan
- Prior art keywords
- pins
- grid array
- pin grid
- double
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6255686U JPS62174349U (pt) | 1986-04-26 | 1986-04-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6255686U JPS62174349U (pt) | 1986-04-26 | 1986-04-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62174349U true JPS62174349U (pt) | 1987-11-05 |
Family
ID=30896940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6255686U Pending JPS62174349U (pt) | 1986-04-26 | 1986-04-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62174349U (pt) |
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1986
- 1986-04-26 JP JP6255686U patent/JPS62174349U/ja active Pending