JPS62172570A - Signal processor for disk memory - Google Patents

Abstract

PURPOSE:To attain the large capacity storage and random access by extracting the storage of constant interval and number of revolution constant system contactlessly and applying filtering processing in response to the position of a pickup. CONSTITUTION:The constant interval storage is attained by the signal light velocity processed by prescribed modulation at a signal source 30 controlled by a recording command signal in the timing in response to the pickup position from a line velocity detection section 70 to a constant revolution disk memory section 50. The storage is read optically contactlessly and a reproducing signal in response to the reflected luminous flux is processed by a filter of a signal reproducing section 80 decided in response to a reproducing command signal from the detection section 70 and noise or the like is eliminated excellently from the recording of the different line velocity and the result is reproduced. A large capacity data is stored by the constant interval recording and the data is subject to random access by the constant revolution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to optical or magnetic recording and reproduction of signals in a disk memory, and is particularly directed to a signal processing device that is effective in a system in which a disk is rotated at a constant rotation speed. Regarding.

[Conventional technology]

Since disk-shaped memories such as optical disks, magnetic disks, and magneto-optical disks have a large storage capacity, they can be widely used as external memory for computers, etc., in addition to conventional consumer uses such as storing audio and video signals.

There are two drive systems for this disk memory: one that keeps the rotation speed constant like that of a record, and one that changes the rotation speed depending on the position of the pickup like the optical disk file memory device described in the March 26, 1984 issue of the magazine Nikkei Electronics J. There is one that makes the rotation speed variable and keeps the circumferential speed constant.

[Problem that the invention seeks to solve]

'Comparing these two methods, the constant circumferential speed method can store information at fixed intervals determined by the resolution, so it can store larger amounts of information than the constant rotation speed method. By the way, this is not so much of a problem when the pickup moves continuously from the outside to the contents, such as on a record, but when using it as an external memory for a computer, random access is essential, so it is necessary to move the pickup position discontinuously. The 6-rotation speed variable force formula, which requires changes, is unsuitable for such applications, and high-speed rotation speed changes are not possible.

In view of the above, it is an object of the present invention to provide a signal processing method for a disk memory that can simultaneously achieve mass storage and random access.

[Means for solving problems]

In the present invention, a constant interval storage and constant rotation speed method is used, and the filtering process of the extracted signal is controlled according to the pickup position.

[Function] By storing data at regular intervals, a large capacity can be stored. By keeping the rotation speed constant, random access will not be affected by mechanical inertia. On the other hand, if the intervals of the extracted signals are uneven, Therefore, filtering signal processing is performed according to the pickup position.

〔Example〕

FIG. 1 is an overall explanatory diagram of an embodiment of the present invention.

The symbols and operations shown in FIG. 1 will be described below.

10 is an original signal group. The original signal group 10 includes audio, video, or analog quantities such as voltage, current, and temperature to be recorded.
Alternatively, 30 is a signal source, which may be a digital quantity.

The signal source 30 is a signal source for recording on the optical disk memory, and is configured to conveniently record the original signal.
Coded Modulation (PCM) or Frequency Modulation (FM)
, pulse width modulation, amplitude modulation, etc., as appropriate. In some cases, code errors may also be detected,
In some cases, code processing has been performed to perform corrections and the like.

This signal source 30 corresponds to the pickup position and controls the original signal acquisition conditions, modulation, and output timing according to, for example, the linear velocity accompanying the rotation of the disk.

50 is an optical disk memory section. The details of the operation will be described later with reference to FIG. 2, and only the outline will be described below. The optical disk memory section 50 rotates a disk having a recording medium at a constant rotation speed and optically records the output signal from the signal source 30. Also.

Optical detection is also performed when reproducing recorded signals, and the optical system is equipped with autofocus and tracking functions so that signals can be recorded and reproduced at predetermined positions on the recording medium.

Reference numeral 70 denotes a linear velocity detection unit included in the optical disc memory unit 50 for detecting the linear velocity of the disc when the disc is driven. Based on the value detected by the linear velocity detection section 70,
The timing of recording signals on the optical disc is controlled so that the signals are arranged at equal intervals on the circumference of the disc.

81 and 90 are the outputs of the linear velocity detection section, 81 is a recording command signal, and 90 is a reproduction command signal.

301 modulated the output of the signal source 30 into a luminous flux.

This is the light beam irradiated onto the optical disk memory unit 50.

361 is a reflected light flux from the optical disk memory unit 50. 80 is a signal reproducing section, and the optical disk memory section 50
This is the part that receives the reflected light beam 61 from and returns it to an electrical signal.

FIG. 2 is an explanatory diagram of the operation contents mainly of the optical disk memory section 50 of FIG. 1. Hereinafter, symbols that are the same each time indicate the equivalent. The signal source 30 generates a luminous flux 301 necessary for recording, signal reproduction, erasing, etc., respectively. As the light source for the luminous flux, for example, one that converts an electric signal into a luminous flux using a semiconductor laser can be used. A lens 31 transforms the light beam 301 into a parallel light beam 32. Reference numeral 33 denotes a beam splitter, which allows the parallel light beam 301, which is the incident light from the lens 31, to pass straight through, and conversely, the light coming from the 1/4λ plate 34 side is refracted and sent to the mirror 43 side.

The 1/4λ plate 34 changes the phase of the light beam passing through it.
It is for the purpose of Reference numeral 35 denotes an objective lens, which adjusts the incident parallel light beam so that it is focused on the recording medium 39. Therefore, the objective lens 35 has an additional function of following a guide track on the recording medium and focusing so that the focal point from the lens matches the irradiation point of the recording medium 39 on which the light beam is irradiated. 37 is a lens holder that can perform tracking and focus control.

36 is a condensed light beam focused by the objective lens 35. 38 is a light beam irradiation point. 42 is a track groove;
39 was equipped with a recording medium. Disk, 40 is rotating table,
41 is a motor. The disk 39 is placed on a rotary table 42 and can be rotated by pulsating a motor 41. The disk 39 records a signal at a predetermined position,
Play.

Alternatively, it has a track groove 42 for performing tracking for one positioning in order to perform erasing or the like.

61 indicates the center of rotation of the disk 39.

When a signal is recorded on the disk 39 and when it is erased, the reflectance when irradiated with the condensed light beam 36 is different, and the reflected light beam 361 is used for signal decoding, that is, reproduction, tracking, and focusing. Used for control.

A reflected light beam 361 is obtained after passing through the objective lens 35, the λ/4 plate 34, and the beam splitter 33. 43 is a half mirror that passes a part of the incident light beam 361 and refracts a part of it.

44 is a two-split optical sensor, and 45 is a comparator, which are used to perform tracking control. The light beam obtained by partially refracting the reflected light beam 361 by the half mirror 43 is
31. The luminous flux 431 is.

When a predetermined track is irradiated with the condensed light beam 36, the two-split optical sensor 44 is uniformly irradiated, the output voltages 441 and 442 of the two-split optical sensor become equal, and the output of the comparator 45 becomes zero. , the tracking control is stopped at the same position. If the condensed light beam 36 is irradiated with a deviation to the left or right, the two-split optical sensor 4
A difference occurs between the output voltages 441 and 442 of 4, and the output voltage 44
The lens holder 37 is controlled so that the difference between 1 and 442 becomes zero. , 451 are tracking control signals for this purpose.

Next, focus control will be explained. Reflected luminous flux 36
Let 432 be the luminous flux in which a part of the light beam 1 passes through the half mirror 43 and is output. 46 is a cylindrical lens that deforms the light beam 432. The output luminous flux is assumed to be 461. Reference numeral 47 denotes a four-division optical sensor, and numerals 51 and 52 denote an adder, which inputs and adds values obtained by converting light into electric quantities by the four-division optical sensor 47.

A comparator 54 compares the outputs of the adders 51 and 52 and provides a signal 541 to control the lens holder 37 based on the same concept as tracking. In focus control, when the focused light beam 36 is focused and irradiated on the target light beam irradiation point 38, a light beam 461 based on the reflected light beam 361 is uniformly irradiated onto the 4-split optical sensor 47, and the 4-split optical sensor 47 is uniformly illuminated. Each output voltage 471, 472, 473. and 4
74 are the same, the output of the comparator 54 is zero, the focus control signal 541 is also zero, and the focus control function of the lens holder 37 is set such that the focusing of the objective lens 35 is maintained as it is. remains working. If the focus is not good, a difference will occur between the outputs of the adder 52 and the adder 51 depending on the distance of the focus position.
For example, when the focus position is too close, the output 476 of the adder 51 becomes larger than the output 475 of the adder 52,
Conversely, when the distance is far, output 475 is assumed to be larger than output 466, and therefore output 475 and output 47
focus control signal 5 of comparator 54 until 6 are equal.
41 performs focus control.

Next, an outline of the signal reproducing function, which is the main part of the present invention, will be explained. First, output voltages 471, 473, 472, and 474 detected by a 4-split optical sensor based on the luminous flux 461
Addition outputs 475 and 476 are added by an adder 53. The output of the adder 53 is assumed to be 531. Output 531 contains the recorded signal and its timing signal. A filter 55 made of, for example, a switched capacitor that passes signals in a band including the timing signal is provided, and a timing signal detection section 56 detects the timing signal from the output signal of the switched capacitor filter. This timing signal is recorded on the disk 39, and its frequency changes corresponding to the number of rotations of the disk 39.

Therefore, detection of the timing signal corresponds to the function of the disk linear velocity detection section 70. The detected timing signal 561 is a recording command signal 81 . and is used as a reproduction command signal 90. The configuration and operation of this part will be detailed later.

FIG. 3 is a conceptual diagram of the structure of the disk 39. In the figure, 11 is a pit in which a signal is recorded. The pits 11 are arranged on the circumference at equal intervals of Ω. The pit 11 is arranged above the track line 12. Digital signals "1" and '0' are recorded in the pit 11.The signal "1" has a difference such that the reflected luminous flux 361 when the light condenser 36 is irradiated onto the disk 39 is larger than that of the signal taO. Any material may be used as long as it has a color tone change, and for example, an optical recording crystal and an alloy that utilizes phase change between crystals can be used. 61 is the center of rotation of the disk, and the disk 39 is rotated at a constant speed.

FIG. 4 shows the input signal 531 and output signal 551 of the switched capacitor filter 55 when recorded as shown in FIG.
shows. 561 shows an example of the output signal waveform of the timing detection section, where the number of rotations of the disk 39 is constant N rotations per second, the radius to the pit is r (m), and the pit interval is Ω (m ).
Then, the travel time of the irradiation point of the condensed light beam 36 between the pits is □2πrN (seconds). This time becomes the period of the timing signal, and depends on the rotation speed N of the disk 39, the radius r, and the pit interval Ω. You can see that it changes. Now, in the present invention, since the pit interval Ω and the rotation speed N are constant, the travel time between the pits differs depending on the radius r of the disk, that is, whether the recording and playback position is on the outer circumference side or the inner circumference side of the disk 39. The frequency of the timing signal will change. Here, in order to simplify the configuration of the disk 39 and the entire signal processing device, and to improve the signal-to-noise ratio (S/N ratio), it is necessary to keep the rotation speed N constant and the pit interval constant. 39 should record as many sample values of the signal as possible.

FIG. 5 shows a timing signal 5 accompanying the rotation of the disk 39.
5(a) shows an example of a configuration for detecting the signal 61 (recording command signal 81), sampling the signal, and recording the signal. FIG. 5(a) shows the signal source 30 in FIG. 1. FIG. 5(b) is an explanatory diagram showing the contents of the signals related to FIG. 5(a). The operation shown in FIG. 4(a) will be explained below. 10 is the original signal.

311 is a switched capacitor filter, which is a band-limiting filter when sampling and recording the original signal 1o. 312 is an analog-to-digital converter (A/D
), which converts the analog signal into, for example, a binary code. What determines the characteristics of the switched capacitor filter 311 is a timing signal indicated by a recording command signal 81, and based on this, an appropriate lock is generated. 82 is a clock generation circuit. The clock for the switched capacitor filter of the clock generation circuit is indicated by 801, A/
The D conversion clock is also indicated by 802.

The code modulation unit 313 is used for error checking of the digitized code and for incorporating a synchronization signal and the like. This code modulation section 313 also uses the clock 803. clock 80
3 is generated based on the recording designation signal 81,
As already shown in FIG. 4, this is related to the moving speed of the pit interval of the disk 39.

Reference numeral 314 denotes a laser driving section, which digitally adjusts the intensity of the laser light emission according to the code of the code modulation section 313. The analog signal in FIG. 5(b) is an example of the original signal group 10. The original signal group 10 is A/D converted by a clock 802 for sampling timing.

FIG. 6 is an embodiment showing the operation contents of the signal reproducing circuit unit 80. Reference numeral 90 denotes a reproduction command signal, which is obtained based on the moving speed of the pit irradiation position as explained in FIG. 53
Reference numeral 1 denotes an optical/electrical conversion output signal derived using the 4-split optical sensor shown in FIG. 881 is a code demodulation unit, which includes a synchronization signal, code error detection, code error correction functions, etc. for extracting signal components. 882 is a D/A converter that converts a digital signal into an analog signal. 883 is a switched capacitor filter, D
/A is a filter for suppressing harmonic components of the output signal. 901, 902, and 903 are clocks, respectively, which are generated based on the reproduction command signal 90.

Clock 901 is used to generate the functions of the code demodulator. A clock 902 determines the D/A conversion timing.

Clock 903 is for setting the characteristics of the switched capacitor filter.

FIG. 7 shows an example in which the characteristics of the switched capacitor filter 55 when detecting a timing signal are controlled by the output of the timing detection section 56.

Clock 563 given by 562 to the switched capacitor
This is a phase memory circuit that generates . The clock 563 is
The output of the timing detector 56 is temporarily stored, and the switched capacitor filter always outputs the output of the timing detector 56.
This control is performed so that the band can be passed to the maximum value of the frequency component of the input signal 551 of No. 6. Therefore, the memory time of the one-phase memory circuit 562 is sufficient as long as it is enough to stabilize the transient response of the switched capacitor filter 55. In the above invention, the recording and reproduction of signals using the code modulation method has been described, but single frequency modulation, pulse width modulation, or amplitude modulation may also be used. In addition, switched capacitor filters require impedance matching with the connected circuit when inputting or outputting signals, and operational amplifiers are often used for buffering in the input stage or output stage. Figure 17 shows an example in which a switched capacitor filter and an operational amplifier are combined.
In the figure, 325 is a switched capacitor, 326
is a buffer amplifier of the signal input circuit, and 327 is a buffer amplifier on the signal output side.

320 is an analog signal processing circuit. By making the entire analog signal processing circuit of 320 into a highly integrated circuit, so-called LSI, the effect of miniaturization is increased. Furthermore, since they are used under the same environment, they have the effect of making it easier to stabilize the characteristics.

Next, a specific method of driving a switched capacitor filter will be explained based on the drawings.

8. As shown in FIG. 8, the switched capacitor equivalent resistance SCI is composed of switches SWI to SWI5WIs and a capacitor Cr1. The same applies to the other switched capacitor equivalent resistances SCz, SCs, and SC4. C1e Cz is an integrating capacitor 100 and 200 are operational amplifiers. A switched capacitor filter is equivalent to an active filter in which the resistance element is replaced with a switched capacitor equivalent resistance.

The switches SWs and SWz have clock input terminals φ
When 1 is “1”, ONt, switches SWt and SW
4 is turned on when the clock input terminal φ1 is 1''. Switches SWs and SW7 are turned on when the clock input terminal φ2 is 1'.
1", the switches SWs and SWs are turned ON when the clock input terminal (z is "1"). Furthermore, the switches SW11, tSW, Z, 5W1B and
W te is O when the clock input terminal φS is 1".
N and switch SWtδ.

SWt number, 5W17, and SW ta are turned ON when the clock input terminal φ3 is "1". That is, the switched capacitor equivalent resistances SCt and SCz output independent clocks to the clock input terminals φ1 and C1 and C2 and C2.
SCa and SC4 operate by applying the same clock to clock input terminals φ3 and C3.

In the circuit shown in FIG. 8, the output of the operational amplifier 100 becomes the output of the second-order bandpass filter, and the output of the operational amplifier 200 becomes the output of the second-order low-pass filter.

First, the bandpass filter will be explained.

The following equation shows the transfer function of the bandpass filter.

However, C0: Angular frequency Q: Selectivity H: Gain coefficient In the circuit shown in Fig. 8, the clock to be applied to realize the switched capacitor equivalent resistance shown in SCz to SC4 is connected to the clock input terminals φ1, φ1, φ2 and (z and φ8
and 78 groups. Than this,
The characteristic constant of the bandpass filter can be expressed by the following equation.

Here, in the circuit of FIG. 8, fax is the clock frequency applied to the clock input terminals φ1 and 71, fsz is the clock frequency applied to the clock input terminals φ2 and φ2,
Jss is a clock frequency applied to clock input terminals φ8 and ds. Furthermore, the clock input terminal Tl is φl
On the other hand, <61 indicates that an inverted clock is given to φ2, and T8 is given to φ♂.

First, the case of changing the center frequency io will be explained. Focusing on the above equation (6), the center frequency fo is a function of the capacitors Cr a g Cr4 t C1 and C2, and is also expressed as a function of the clock frequency fss. That is, in order to arbitrarily change the center frequency fo, the capacitor (:, ,
It can be understood that it can be changed by arbitrarily changing the clock frequency fss in addition to changing the values of B, C a , CI, and Cx.

The clock frequency fss mentioned above is determined by the selectivity Q from equation (7).
Since it is also a parameter of , the selectivity Q is also changed at the same time. Therefore, in order to change only the center frequency fo without changing the 1 selectivity Q, it is necessary to change it in accordance with fst and +fsa.

Furthermore, if fsx is changed, the gain coefficient H
913i! will also be changed, so fsx must also be changed to match fss. Considering one or more things, the 913i! I (a) shows a clock wiring diagram for changing only the center frequency fo.

In FIG. 9(a), the clock input terminal φ! .

The basic clock frequency shown in FIG. 10 is applied to φ2 and φ8!
, the clock CKa of φ1. A clock CKa obtained by inverting the clock CKa is applied to φ2 and T8.

The frequency-gain characteristic at this time is vl in Fig. 11(a).
Shown below. In vl of FIG. 11(a), an example in which the center frequency fo is 100 Hz is shown. On the other hand, if the frequency is −
The clock pulses CKa and CKδ of f, are respectively φl, φ2 .
φ8 and φl, φ2. When given to φ8, as shown in v2 in FIG. 11(a), only the center frequency fo becomes
) is 50Hz, which is one times the Vz.

Since the clock frequency fss is one time the basic clock frequency, substituting it into equation (6) gives f.

It is easy to understand that the value increases by - times. moreover.

Clock CKz with a frequency of 2fs, CKx is φ.

φ2. φ, and T'ILe'I's, the center frequency f is given as v8 in Fig. 11(a).
.

is 200 Hz, which is twice vl in FIG. 11(a). Also, by substituting the clock frequencies of φ8 and φ8 into equation (6), it is clear that jo is doubled, which is greater than 0. Give each a clock with the same period. It will be understood that by varying the frequency of this clock, only the center frequency io can be varied arbitrarily.

Table 1 shows the relationship between the clock input terminals explained above, the clock, and the correspondence of their effects.

Table 1 Next, an example of changing only the selectivity Q will be explained.

Focusing on the above equation (7), the selectivity Q can be expressed as a function of the clock frequencies fsz and fs8. In other words, in order to arbitrarily change the selectivity Q.

This can be achieved by arbitrarily changing fsz and fss. However, if fsa is changed, the center frequency fo will also be changed.

In order to change only the selectivity Q, it is preferable to change fsx. However, as described above, fsz is also related to gain coefficient H, so fsl must also be changed in accordance with fsz. FIG. 9(b) shows a clock wiring diagram for changing only Q. The frequency-gain characteristics when the clock CKa is applied to the clock input terminals φ1, φ2 and φS in FIG. 9(b) and the clock number GK is applied to extφ2 and φδ are shown in vl in FIG. 11(b). , which is exactly the same as vl in FIG. 11(a). On the other hand, clock input terminals φ1 and φ2
clock CK6. Clock CKs is given to T and Tz, and clock CKx is given to φδ, and clock CK is given to $a.
When z is given, only the selectivity Q can be doubled as shown by v2' in FIG. 11(b). Furthermore, if φ3 and p8 are left as they are and clock CKI is applied to φ1 and φ2, and clock CK z is applied to Tt and φ2, only the selectivity Q has a characteristic that is - times as large as Va' in FIG. 11(b). From the 0 or more that can be obtained, the selectivity Q can be increased by pairing the terminals φ and φ2 and 161 and 72 and varying the clock arbitrarily.
Table 2 shows the relationship between each of the clock input terminals described above and the clock, and the correspondence of their effects.

Table 2 Next, an example in which only the gain coefficient H is changed will be explained. Focusing on the above equation (8), the gain coefficient H is a function of the clock frequencies fs1 and fsz.

That is, in order to arbitrarily change the gain coefficient H, ls
This can be achieved by arbitrarily changing z and fsx. Furthermore, by arbitrarily changing only fsx from equation (8), the gain coefficient H can be changed independently. A wiring diagram of the clock at this time is shown in FIG. 9(a).

Since the clock frequency fsx relates only to the gain coefficient H in the characteristic equation of the bandpass filter, the gain coefficient H can be arbitrarily and independently varied by arbitrarily varying fs>. 8th
Clock input terminal φtt$z+ φ3 and $ of the circuit shown in the figure
Vr in FIG. 11(c) shows the frequency-gain characteristics when the clocks CKa and CK4 are applied to it da + da, respectively.

This is exactly the same as vl in FIG. 11(a).

On the other hand, clock input terminal φ2. φ♂ and Tz.

CK of frequency fs which is the basic clock at φ8
11 (c
), the gain coefficient H increases by one time. Furthermore, when clocks CKI and CKz of frequency 2fs are applied to φl and 71, the gain coefficient H is doubled as shown by Va' in FIG. 11(c). From the above, it can be understood that by arbitrarily varying φl and T1 clock frequency, only the gain coefficient H can be arbitrarily varied. Table 3 shows the relationship between each clock input terminal and the clock described above and the correspondence of their effects.

Table 3 Although the bandpass filter in the circuit of FIG. 8 has been described above, the following lowpass filter will be described. The transfer function of the low-pass filter is expressed by the following formula: %: ： The breaking wave number, which is the characteristic constant of the low-pass filter! , is expressed in exactly the same way as Equation (6) for a bandpass filter, so Equation (6) is used by replacing fo *fs. Furthermore, the 1 selectivity Q is exactly the same as equation (7). However, in the case of a low-pass filter, the gain coefficient H can be expressed by the following equation.

axCrt H= ・・・・・・(
1o) JsaCr number First, an example in which only the cutoff layer wave number f is changed will be described.

Focusing on equation (6), the cutoff layer wave number f can be arbitrarily changed by arbitrarily changing the clock frequency ft, s, just like a bandpass filter.

In Fig. 12(a), the shear fault wave number! In other words, in the circuit of FIG. 8, the clock CKa is applied to the clock input terminals φ1, φ2 and φ♂, and the clock CK is applied to Tls $z and φB.
For the characteristic Va when a is given, φ! , φ2 and φ8
Clock CKδ, 71°72 and 7♂ clock CK
The characteristic v6 is given by a, and the cut-off layer wave number f is doubled. Furthermore, a clock CK s with a frequency of 2 fs is applied to φl, φ2, and φ8, and 71. The characteristics of $2 and 78 given the clock CK x, which is an inversion of the clock C1, are v6, and Table 4 summarizes the relationships of 0 or more showing that the cutoff layer wave number f is doubled. .

Table 4 Next, an example in which only the selectivity Q is changed will be described. Focusing on equation (7), just like the bandpass filter, by pairing the clock input terminals φl and φ2 and Tt and 72 of the circuit in FIG. 8 and arbitrarily varying the clock, only the selectivity Q can be changed arbitrarily. It can be changed to Figure 12 (
b) shows the frequency-gain characteristics when the 1 selectivity Q is arbitrarily changed.

That is, for the characteristic shown in v4 of FIG. 12(b),
Clock input terminal φ2 and clock input terminal CKg, φ1
The characteristic obtained by applying the clock CKe to φ2 is Va', and the selectivity Q is doubled.

Furthermore, φ1 and φ2 have clocks CKs, φx and φ2
The characteristic of giving clock CK 2 to , respectively, is Ve'
Tona JJ, it can be seen that the selectivity Q in this case is - times that of V4. The above relationships are summarized in Table 5.

Table 5 Next, an example in which only the gain coefficient H is changed will be explained.

Focusing on equation (10), the gain coefficient H is a function of the clock frequencies fsx and fs4. In order to arbitrarily change the gain coefficient H, fsl and fs4 may be changed arbitrarily. Furthermore, when only the gain coefficient H is changed independently,
From equations (6), (7) and (10), clock frequency f
It goes without saying that this is possible by changing only ax. FIG. 12(c) shows an example in which only the gain coefficient H is changed, that is.

In contrast to the characteristic shown by V4 in FIG. 12(c), the characteristic when clock CKs is applied to the clock input terminal φl and clock CK6 is applied to $t becomes Vg' in FIG. 12(a), and the gain coefficient H is 1 times become.

Furthermore, the clock CKI and φ1 are connected to the clock input terminal φ.
The characteristic when a clock CK z is given to is v6',
The gain factor H is doubled. The above relationships are shown in Table 6.

Table 6 Note 1: Not only the piquat type filter which is an embodiment of the present invention, but also the leave-frog type filter can be controlled in the same manner by controlling the clock frequency other than H (H
l) any filter characteristic can be obtained.

Furthermore, arbitrary filter characteristics can be obtained not only for low-pass filters and band-pass filters but also for bypass filters by controlling the clock frequency.

Thus, according to this embodiment, the characteristic constants of the filter, such as the center frequency, cutoff frequency fa, selectivity Q, and gain coefficient H, can be arbitrarily varied using an external clock. In contrast to the characteristics of the built-in filter, where only the center frequency could be varied, the characteristic constants can be changed arbitrarily, making it possible to fully respond to changes in characteristics.Furthermore, since the capacitance value of the capacitor, which is one circuit constant, does not change, , there is no need to add a capacitor to change the characteristic constants.Therefore, the chip area is small.

It can be highly integrated, and since a control terminal for switching capacitors is not required, the number of unnecessary pins can be reduced.

1. Second Embodiment - A second embodiment of the present invention is shown in FIGS. 13 to 16. In this second embodiment, the same or overlapping parts as shown in FIGS. 8 to 12 are given the same reference numerals and will be explained below.

This second embodiment uses a group of switches so that the characteristic constants of the switched capacitor filter, such as the center frequency foe selectivity Q and the gain coefficient H, can be arbitrarily and independently changed at one location using only the clock frequency. It is divided roughly into three parts, and changes in clock frequency are controlled with priority, and the switched capacitor filling itself is the same as in the first embodiment, so a description thereof will be omitted.

In FIG. 13, numeral 300 indicates a clock signal generation circuit, which generates the basic tarok frequency fs. This basic clock signal is transmitted to the continuously connected first counter 401.
The frequency is sequentially divided by the second counter 402 and the third counter 403, and each manual changeover selection switch St, S2. Each switched capacitor equivalent resistance circuit S C1 * S Cz + S Cs via Sa and the inverter 500
#S C4 clock input terminals φ, φl, φ2. φ
2. φ6. φ8 is made.

First, the case of changing the center frequency jo will be explained. Focusing on the above equation (6), the center frequency fo is a function of the capacitors C a g C a y Ci and C2, and is also expressed as a function of the clock frequency fss. That is, in order to arbitrarily change the center frequency fo, it is necessary to change the capacitor Cr5v, which is a parameter of equation (6).
In addition to changing the values of Cra, Cs and C2, the clock frequency! , δ can be changed arbitrarily.

The clock frequency fss mentioned above is determined by the selectivity Q from equation (7).
Since it is also a parameter of , the selectivity Q is also changed at the same time. Therefore, in order to change only the center frequency io without changing the selectivity Q, fsz must also be changed in accordance with fss.

Furthermore, when fsz is changed, the gain coefficient H
Since the FSA will also be changed, the fax must also be changed to match the FSA.

Therefore, a counter 401゜40 that divides the clock signal is used.
2.403 are connected in cascade, and the output of the first counter 401 is applied to the clock input terminals φ8 and 73. That is, when the frequencies of the clock input terminals φ8 and φ8 are changed, the counters 402 and 403 in the next stage and subsequent stages follow the above change, so their output frequencies are automatically changed. Therefore, only the center frequency fo can be changed independently at one location. This will be explained in detail below using the clock waveform shown in FIG.

In the circuit of FIG. 13, the selection switch SL.

By selecting B, B' and B' of the outputs of counters 401, 402 and 403 at St and Sa, clock input terminals φ1. The clocks CKtts CKtz and GK1g shown in FIG. 14(a) are applied to φ2 and φ8, and the clock CKz is applied to St, *z and 76.
Assume that x, CKzz, and CK t a are inverted and provided by the inverter 500.

Here, the frequency of the clock CK11 is assumed to be fs.

The frequency-gain characteristic at this time is Vl in Fig. 15(a).
Shown below. 1 in FIG. 15(a) shows an example in which the center frequency io is lOOHz. On the other hand, when C is selected from the output of the first stage by the selection switch Ss, the clocks CKII', CKlz' and CKza' shown in FIG. 7(b) are provided.

The frequency of clock cxiz' and CKza' is CKss
', each will be multiplied by 1. At this time, the frequency-gain characteristic is as shown in v2 in Fig. 15(a), where only the center frequency io is -50 times vl in Fig. 15(a).
It is clear that the frequency is Hz.

This can be easily understood by substituting into equation (6) since the clock frequency fss is one times the basic clock frequency f.

Next, an example of changing only the selectivity Q will be described. Focusing on the above equation (7), the selectivity Q can be expressed as a function of the clock frequencies fsz and fsa. That is, in order to arbitrarily change the selectivity Q, fsz and f
This can be achieved by arbitrarily changing ss. However, when changing fss, the center frequency fo
In order to change only the selectivity Q,

It is better to change fsz. However, as mentioned above, fsz is also related to the gain coefficient H, so fsx is also related to f
It must be changed according to sz.

Therefore, in the circuit of FIG. 13, the second counter 402
The outputs of the clock input terminals φ2 and φ2 are supplied to the clock input terminals φ2 and φ2. That is, when the frequencies applied to the clock input terminals φ2 and 72 are changed, the frequency of the third counter 403 is automatically changed to follow the change, and only the selectivity Q can be changed independently at one place. This will be explained in detail below using the clock waveform shown in FIG.

In the circuit of FIG. 8, the selection switches Sz, St and S8 select from the outputs of the counters 401, 402 and 403.
By selecting clock input terminals φ1.B, B' and B'. Clocks CKzz, CKzz and CKza shown in FIG. 14(c) are applied to φ2 and φ8. Here, the frequency of the clock CKzz is assumed to be fs. The frequency-gain characteristic at this time is shown in vl in FIG. 15(b). On the other hand, the selection switch S2 selects the second counter 4.
When C' is selected from the output of 02, clocks CKzz, CKzz' and CKza' shown in FIG. 14(d) are applied to φl, φ2 and φ8. As a result, Fig. 15(b)
As shown in Vz', only the selectivity Q can be doubled.

This can be easily understood by substituting it into equation (7) since the clock frequency fss is one times the basic clock frequency fs.

Next, an example in which only the gain coefficient H is changed will be described. Focusing on the above equation (8), the gain coefficient H can be independently changed at one location by arbitrarily changing only the clock frequency fs1.

Therefore, in the circuit of FIG. 13, the third counter 403
The output of is given to the clock input terminal φ1 and =/=1. That is, since the output of the third counter 403 is only given to the clock input terminals φ1 and =fix,
This shows that only the frequencies applied to the clock input terminals φ1 and (5) can be changed independently. Therefore, by equation (8), only the gain coefficient H can be changed independently.
This will be explained in detail using the clock waveform shown in FIG.

In the circuit of FIG. 13, the selection switch 81.

By selecting B, B' and B' from S2 and S3, the clock input terminals φ1. Figure 14 (
Clock CK811 CKaz and CKaa shown in e)
is given. Here, the frequency of clock CKaa is f,
shall be. The frequency-gain characteristics at this time are shown in Figure 15 (Q
) is shown in vl. On the other hand, when C' is selected from the output of the third counter 403 by the selection switch S8, the clocks CKat, CKaz and CKaa shown in FIG. 14(f) are applied to the clock input terminals φ1, φ2 and φδ. As a result, it is possible to obtain a characteristic in which only the gain coefficient H is doubled, as shown by Vz in FIG. 15(Q).

This can be understood by substituting it into equation (8) since the clock frequency fss is one times the basic clock frequency fs.

As described above, by giving priority to changing the clock frequency, the characteristic constant of the filter can be changed independently at one location. That is, to summarize, when the clock frequency for changing io is changed, the clock frequency for changing Q and H is also changed. Also, when the clock frequency for changing Q is changed, the clock frequency for changing H is changed in the same way, but the clock frequency for changing io is not changed.Even if the clock frequency for changing H is changed, f.

And the clock frequency for Q change is not changed.

-+1 The present invention can be sufficiently applied to low-pass filters, bypass filters, etc. other than the band-pass filters described in the embodiments of the present invention.

Furthermore, not only piquat type filters.

Of course, the same applies to leapflock filters as well.

As described above, according to the present invention, by changing only the clock frequency, 1. Since each characteristic constant of the switched capacitor filter can be changed independently, the device configuration can be simplified.

FIG. 18 shows an embodiment in which an active filter consisting of a resistor, a capacitor, and an operational amplifier is used instead of the switched capacitor filter described above. In the figure, 561 is the timing for detecting the linear velocity of the optical disk memory. P81 is a controller, which is used to control a switch that varies the resistance value of the active filter depending on the frequency of the signal at timing 561. The output signal of the controller pat is
It is 8. The output signal PC8 is the switch Sll.

Used to close one of S 1st, S ta, and S tn. Which one should be closed is determined in advance by the value of timing 561, and is stored in the controller Paz in advance. For example, a microcomputer may be used as the controller P81. Ri
t, Rze Rta, Rtn are resistances.

Aal is an operational amplifier. Cat is a capacitor. The active filter shown here is an example of a first-order low-pass filter. Gain characteristics are Vout(S)
L □Knee□ ・・・・・・(11) VI II
It is represented by (S) R1s ・Ca I S. However, this is an example in which the ideal characteristic of the operational amplifier is 1, and the resistance is selected as Rat. therefore.

The gain of the filter can be changed by varying the resistors R11 to R1° depending on the contents of the timing 561. In the figure, only the resistance was varied, but by similarly varying the resistance of the capacitor Cl1l,
Furthermore, the characteristics of the filter can be varied. Further, in FIG. 18, the values of components may be changed depending on the contents of the timing 561 in the combination of active filters, etc. Also, the filter and sampling frequency are
The desired effect can be obtained even if the linear velocity of the optical disk memory is divided into two or three stages, such as outer, intermediate, and inner, and varied according to these divisions.

Furthermore, in addition to varying the value of the resistor or capacitor in FIG. 18, the current flowing through the capacitor may also be controlled. FIG. 20 is an example of this. In FIG. 20, the same symbols as in FIG. 18 are equivalent; *Rat is a resistor, and CC is a current controller flowing through a capacitor Can. The current controller may be a limiter that prevents the current from flowing beyond a certain level. 561 is a signal that detects the linear velocity of the optical disk memory, and is the timing. At timing 561, the current flowing through the capacitor Cl1l is controlled. When the current flowing through the capacitor is Ice, the output voltage of the filter is as follows.The characteristics of the integral filter can be changed by controlling the current Ice. Further, the filters shown in FIGS. 18 and 20 are just examples, and these configurations may be configured in series or in combination with parallel circuits.

Of course, filters with various characteristics can be provided.

FIG. 19 is an example in which a digital filter is added as a filter. In the figure, 3110F is a digital filter. 311 may be the previously mentioned switched capacitor filter, and 312 is an A/D converter.

The input signal is sampled at regular intervals using a switched capacitor filter 311 with fixed clock characteristics and a clock with a frequency sufficiently higher than the sampling timing 802, and an A/D converter 312, and its digital output is obtained. Let the signal be ADO. Digital output signal AD
A digital filter 311DF is used to record O on an optical disk memory and limit the band to the one necessary for reproduction. G30
Reference numeral 2 denotes a gate, which outputs a signal for recording according to the sampling timing 802 determined by the linear velocity of the optical disk memory.

Since the clock of the A/D converter can be kept constant, the circuit can be simplified, and signals can be recorded according to the linear velocity of the optical disc.

〔Effect of the invention〕

According to the present invention, even if the rotation speed of the optical disk memory is kept constant, signals can be efficiently recorded, thereby improving the signal-to-noise ratio during signal reproduction, simplifying the device configuration, and improving economic efficiency.
This is effective in terms of reliability, etc.

[Brief explanation of drawings]

FIG. 1 is an overall explanatory diagram of the present invention, FIG. 2 is an explanation of the optical disk memory section, FIG. 3 is an explanation of an example of the configuration of an optical disk, FIG. 4 is an explanation of timing signal detection, and FIG. 5 is an explanation of recording signal modulation. Explanation of an example, Fig. 6 is an explanation of signal regeneration operation, Fig. 7 is an explanation of timing signal detection using phase memory, and Fig. 8 is an explanation of timing signal detection using a phase memory.
The figure shows an example of a circuit of a switched capacitor filter, Fig. 9 is an explanatory diagram of characteristics of the filter, Fig. 10 is a time chart of the filter, and Fig. 11 shows a switched capacitor filter.
12 is an explanation of the characteristics of the switched capacitor low-pass filter. FIG. 13 is an example of the embodiment shown in FIG. 12. FIG. 14 is an explanation of the clock signal and time chart. Fig. 16 is an explanatory diagram showing priorities, Fig. 17 is a conceptual diagram of a filter configuration, Fig. 18 is an example of an analog filter, Fig. 19 is a digital filter combination configuration diagram, and Fig. 20 is a modified configuration example of an analog filter. are shown respectively. DESCRIPTION OF SYMBOLS 10... Original signal group, 30... Signal source, 50... Optical disk memory section, 70... Linear velocity detection section, 80...
- Signal regeneration section, 55...Switched capacitor filter, SCI, SCz, SCa, SC4-switched capacitor equivalent resistance, SWI~5Wxo...Analog switch, CI, Cx...Capacitor, φ1. $
1... Clock, Aal... Operational amplifier, 561.
... Taimin Yu 5 figure (α) mark (b, 1 躬6 figure tank'1 figure 563 't. Suri 8 figure (BPF) 9 figure (α) (b) (C) Otsu υU FM%ueTLCy
Fyeq, 4enc zo -mo 13 fig.

Claims (1)

[Claims] 1. A disk memory in which data is stored at regular intervals in a disk-shaped memory, the disk is driven at a constant rotation, and data is extracted through a filter from a signal regarding the data extracted without contact with the disk. Signal processing device. 2. Data is stored in a disk-shaped memory at regular intervals, the disk is driven at a constant rotation, and the data is extracted from the signal of the data extracted without contact with the disk via a filter, and the data is extracted according to the signal extraction position of the disk. A disk memory signal processing device that allows variable filter characteristics. 3. A signal processing device for a disk memory according to item 2, characterized in that a timing signal of a signal detected as corresponding to a signal extraction position on the disk is used.