JPS6217253U - - Google Patents
Info
- Publication number
- JPS6217253U JPS6217253U JP10729285U JP10729285U JPS6217253U JP S6217253 U JPS6217253 U JP S6217253U JP 10729285 U JP10729285 U JP 10729285U JP 10729285 U JP10729285 U JP 10729285U JP S6217253 U JPS6217253 U JP S6217253U
- Authority
- JP
- Japan
- Prior art keywords
- tuner circuit
- circuit
- adjusted
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Noise Elimination (AREA)
Description
第１図は本考案に係わるチユーナ回路の構成を
示すブロツク図、第２図は実施例を示す回路図で
ある。 ３…切換スイツチ、９…妨害除去回路、９ａ…
複同調回路。
示すブロツク図、第２図は実施例を示す回路図で
ある。 ３…切換スイツチ、９…妨害除去回路、９ａ…
複同調回路。
Claims (1)
- チユーナ回路の入力段に帯域特性の調整可能な
複同調回路が切換スイツチによつて接続可能とな
されたことを特徴とするチユーナ回路。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10729285U JPS6217253U (ja) | 1985-07-12 | 1985-07-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10729285U JPS6217253U (ja) | 1985-07-12 | 1985-07-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6217253U true JPS6217253U (ja) | 1987-02-02 |
Family
ID=30983439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10729285U Pending JPS6217253U (ja) | 1985-07-12 | 1985-07-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6217253U (ja) |
-
1985
- 1985-07-12 JP JP10729285U patent/JPS6217253U/ja active Pending
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