JPS62169523U - - Google Patents

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Publication number
JPS62169523U
JPS62169523U JP5736886U JP5736886U JPS62169523U JP S62169523 U JPS62169523 U JP S62169523U JP 5736886 U JP5736886 U JP 5736886U JP 5736886 U JP5736886 U JP 5736886U JP S62169523 U JPS62169523 U JP S62169523U
Authority
JP
Japan
Prior art keywords
volumes
sliding
terminal
amplifier
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5736886U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5736886U priority Critical patent/JPS62169523U/ja
Publication of JPS62169523U publication Critical patent/JPS62169523U/ja
Pending legal-status Critical Current

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Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案のレベル調整回路の一実施例
図、第2図は従来のレベル調整回路図である。 SW,SW,SW……スイツチ、RV
,RV……ボリユーム、Q……FET。
FIG. 1 is a diagram of an embodiment of the level adjustment circuit of this invention, and FIG. 2 is a diagram of a conventional level adjustment circuit. SW 1 , SW 2 , SW 3 ... switch, RV 1
, RV 2 ...Volume, Q...FET.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] n個の複数の入力信号を選択するスイツチと、
前記スイツチで選択された入力信号を増幅する増
幅器と、前記増幅器の出力に並列接続されたn個
のボリユームと、前記n個のボリユームのうち任
意の1つのボリユームの摺動端子と他各ボリユー
ムの摺動端子間に直列接続された(n−1)個の
FETと、前記(n−1)個のFETの導通を制
御する制御手段とから成り、前記任意の1つのボ
リユームの摺動端子を出力端としたことを特徴と
するレベル調整回路。
a switch for selecting n plural input signals;
an amplifier that amplifies the input signal selected by the switch, n volumes connected in parallel to the output of the amplifier, a sliding terminal of any one volume among the n volumes, and a sliding terminal of each of the other volumes. It consists of (n-1) FETs connected in series between sliding terminals, and a control means for controlling conduction of the (n-1) FETs, and the sliding terminal of any one volume A level adjustment circuit characterized by having an output terminal.
JP5736886U 1986-04-16 1986-04-16 Pending JPS62169523U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5736886U JPS62169523U (en) 1986-04-16 1986-04-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5736886U JPS62169523U (en) 1986-04-16 1986-04-16

Publications (1)

Publication Number Publication Date
JPS62169523U true JPS62169523U (en) 1987-10-27

Family

ID=30887005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5736886U Pending JPS62169523U (en) 1986-04-16 1986-04-16

Country Status (1)

Country Link
JP (1) JPS62169523U (en)

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