JPS6216708Y2 - - Google Patents
Info
- Publication number
- JPS6216708Y2 JPS6216708Y2 JP10088584U JP10088584U JPS6216708Y2 JP S6216708 Y2 JPS6216708 Y2 JP S6216708Y2 JP 10088584 U JP10088584 U JP 10088584U JP 10088584 U JP10088584 U JP 10088584U JP S6216708 Y2 JPS6216708 Y2 JP S6216708Y2
- Authority
- JP
- Japan
- Prior art keywords
- buzzer
- volume
- volume control
- noise level
- measuring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Electromechanical Clocks (AREA)
- Electric Clocks (AREA)
Description
【考案の詳細な説明】
本考案はアラーム時計等ブザーを有するブザー
付き時計に関する。[Detailed Description of the Invention] The present invention relates to a watch with a buzzer, such as an alarm watch.
セツトした時刻がやつてくれば報時音によつて
それを知らせるアラーム時計やタイマー付き時計
は非常に便利な機能である。 An alarm clock or a clock with a timer that notifies you when the set time has arrived is a very convenient feature.
しかし従来こうした音響発生源であるブザーの
音量のレベルは固定であり、雑踏の中では音量が
不足したり、静かな会議中などでは音が大き過ぎ
たり不都合な点が多かつた。 However, in the past, the volume level of the buzzer, which is the source of sound, was fixed, and there were many inconveniences such as the volume being insufficient in a crowded environment or being too loud during a quiet meeting.
本考案は上記の点を改善するもので周囲の環境
の騒音レベルに応じて自動的にブザーへの音量を
制御し、確実で他人に迷惑をかけないブザー付き
時計を構成するのを目的とする。 The purpose of this invention is to improve the above points, and to construct a watch with a buzzer that automatically controls the volume of the buzzer according to the noise level of the surrounding environment, and that is reliable and does not disturb others. .
以下図面により本考案の詳細な説明を行なう。 The present invention will be explained in detail below with reference to the drawings.
第1図はブザーのオートレベル設定をするため
の本考案の実施例のブロツク図である。 FIG. 1 is a block diagram of an embodiment of the present invention for automatic level setting of a buzzer.
1は騒音レベルの検出手段、2は1の出力のア
ナログ処理手段、3はA/D変換手段、4はデジ
タル処理手段、5は音量制御手段、6はブザーで
ある。このブロツク図で構成された機能が動作す
るのは時計部よりアラーム時刻到来出力等があつ
た場合に限られ通常はパワーを消費しない。 1 is a noise level detection means, 2 is an analog processing means for the output of 1, 3 is an A/D conversion means, 4 is a digital processing means, 5 is a volume control means, and 6 is a buzzer. The functions configured in this block diagram operate only when the clock section outputs an alarm time arrival output, and normally does not consume power.
1の騒音レベル検出手段はマイクロホンを用い
れば良いが簡易化のため、電気−機械変換器であ
るブザーを逆に用いて電気出力を得ても良い。こ
の場合ブザーを鳴らす前にブザーによつて騒音レ
ベルを測定するのであるから時間的には先となる
騒音レベルの測定と記憶をした上で4〜6のブザ
ー駆動手段及びブザーによつて音が発生する。 A microphone may be used as the noise level detection means 1, but for simplicity, a buzzer, which is an electro-mechanical converter, may be used to obtain an electrical output. In this case, the noise level is measured by the buzzer before sounding the buzzer, so in terms of time, the noise level is measured and memorized first, and then the buzzer driving means 4 to 6 and the buzzer are used to measure the noise level. Occur.
2のアナログ処理手段は1よりの出力の増巾回
路及び一定時間での平均を取るための積分回路を
含む。4のデジタル処理手段は測定した騒音レベ
ルのデジタル出力のメモリー及び該出力に対しプ
ラス何ホン程度大きな音量でブザーを鳴らすのか
を演算する回路である。実際には回路素子数低下
のためブザーの駆動レベルを何種類か作つておき
騒音レベルに対しどの駆動レベルを選択するか決
定する。 The analog processing means No. 2 includes an amplifying circuit for the output from No. 1 and an integrating circuit for taking an average over a certain period of time. The digital processing means 4 is a circuit that stores a digital output of the measured noise level and calculates the output plus how many louder volumes the buzzer should sound. In practice, to reduce the number of circuit elements, several types of buzzer drive levels are created and it is determined which drive level to select based on the noise level.
第2図は本考案の実施例の表示パネルの表示を
示したもので騒音量を56ホンと表示している例で
あり、このような構成とすることにより騒音計と
しても利用できるものである。数字56が現われる
場所は時刻の秒や日といつた桁と兼用し、騒音計
として動作させるためのデマンドスイツチを外部
に設ける。第3図は第1図のブロツク5の音量制
御手段の回路である。原理としては、第4図のよ
うに周波数特性を有し駆動する周波数によつて予
め音量の差が出るブザーを用い、第3図の回路に
より駆動周波数を制御する事により音量を変え
る。この回路の長所は比較的大きな電流を流した
り、LSI上に作り込みのむずかしい音量制御用の
抵抗を排することができることである。又、音量
制御用抵抗を用いる場合には切換えスイツチもブ
ザーを駆動するための比較的電流容量の大きなス
イツチとなるためLSI上に形成するには面積で大
きく取り好ましくない。 Figure 2 shows the display panel display of the embodiment of the present invention, and is an example in which the amount of noise is displayed as 56 phons, and with this configuration, it can also be used as a sound level meter. . The place where the number 56 appears also serves as the second and day digits of the time, and a demand switch is installed externally to operate it as a sound level meter. FIG. 3 shows a circuit of the volume control means of block 5 in FIG. The principle is to use a buzzer that has frequency characteristics as shown in FIG. 4 and whose volume varies depending on the driving frequency, and to change the volume by controlling the driving frequency using the circuit shown in FIG. The advantage of this circuit is that it allows a relatively large current to flow and eliminates the need for a volume control resistor, which is difficult to build on an LSI. Furthermore, when a volume control resistor is used, the changeover switch also becomes a switch with a relatively large current capacity for driving the buzzer, so it is not preferable to form it on an LSI because it requires a large area.
第3図の回路ではブザーコイル7の駆動回路8
を有するのでf1〜f6をスイツチS6〜S11で切り換え
る部分は電力を扱かわずLSI上でも小さく形成で
きる。駆動回路8の直接ブザーをドライブするト
ランジスタは1個であるのでLSI上に形成する事
もできるし、デイスクリートに外付けしても良
い。周波数f1〜f6は第4図の周波数特性で見られ
る如くf1を選択した時音量最大、f2→f3→f4→f5→
f6とステツプ的に音量が小さくなり、この場合6
値の選択となる。 In the circuit shown in FIG. 3, the drive circuit 8 for the buzzer coil 7
Therefore, the portion for switching f 1 to f 6 using switches S 6 to S 11 can be formed small on an LSI without dealing with electric power. Since there is only one transistor that directly drives the buzzer in the drive circuit 8, it can be formed on an LSI, or it can be externally connected to a discrete device. For frequencies f 1 to f 6 , as shown in the frequency characteristics in Figure 4, when f 1 is selected, the volume is maximum, f 2 → f 3 → f 4 → f 5 →
f 6 and the volume decreases in steps, in this case 6
It becomes a value selection.
以上のように本考案によれば、外部騒音に応じ
た音量でブザーを駆動することができ、又ブザー
の音量制御回路はブザーの周波数特性を利用する
ことによつて極めて簡単な回路で構成することが
できる。 As described above, according to the present invention, the buzzer can be driven at a volume that corresponds to external noise, and the buzzer volume control circuit can be configured with an extremely simple circuit by utilizing the frequency characteristics of the buzzer. be able to.
第1図は本考案のブロツク図。第2図は本考案
の表示部の一例を示す図。第3図は音量制御回
路、第4図はブザーの周波数特性を示す図。
1………騒音レベル検出手段、2……アナログ
処理手段、3……A/D変換手段、4……デジタ
ル処理手段、6……ブザー、7……ブザーコイ
ル、8……ブザー駆動回路。
Fig. 1 is a block diagram of the present invention. Fig. 2 is a diagram showing an example of the display unit of the present invention. Fig. 3 is a volume control circuit, and Fig. 4 is a diagram showing the frequency characteristics of a buzzer. 1... noise level detection means, 2... analog processing means, 3... A/D conversion means, 4... digital processing means, 6... buzzer, 7... buzzer coil, 8... buzzer drive circuit.
Claims (1)
駆動周波数によつて音量が変化するブザー、周囲
の騒音レベルを測定する測定手段、前記測定手段
による測定結果をデジタル信号に変換するA/D
変換手段及び前記A/D変換手段の値に従つて前
記ブザーの発する前記警報音の音量を制御する音
量制御手段を有し、前記音量制御手段は複数の周
波数の異なる信号を切換える切換えスイツチとブ
ザー駆動回路よりなることを特徴とする電子時
計。 In an electronic clock that emits an alarm at a predetermined time,
A buzzer whose volume changes depending on the driving frequency, a measuring means for measuring the ambient noise level, and an A/D that converts the measurement results of the measuring means into a digital signal.
It has a volume control means for controlling the volume of the alarm sound emitted by the buzzer according to the values of the conversion means and the A/D conversion means, and the volume control means includes a changeover switch for switching signals of a plurality of different frequencies, and a buzzer. An electronic timepiece characterized by comprising a drive circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10088584U JPS6033682U (en) | 1984-07-04 | 1984-07-04 | electronic clock |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10088584U JPS6033682U (en) | 1984-07-04 | 1984-07-04 | electronic clock |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6033682U JPS6033682U (en) | 1985-03-07 |
JPS6216708Y2 true JPS6216708Y2 (en) | 1987-04-27 |
Family
ID=30238469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10088584U Granted JPS6033682U (en) | 1984-07-04 | 1984-07-04 | electronic clock |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6033682U (en) |
-
1984
- 1984-07-04 JP JP10088584U patent/JPS6033682U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6033682U (en) | 1985-03-07 |
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