JPS62166782A - Multioutput, multivoltage rectifying circuit - Google Patents

Abstract

PURPOSE:To be able to take a desired voltage without recourse to the gradually increasing number of stages by providing a plurality of output ends by altering connection of a Cockcroft-Walton type voltage multiplying rectifying circuit. CONSTITUTION:A Cockcroft-Walton type voltage multiplying rectifying circuit having the gradually increasing number of 5 stages is altered and the third capacitor C3 viewed from the input end (a) side out of capacitors C1-C5 on the side to be connected to loads R1, R2 through diodes D1-D10 is separated from a node (g) near its input end (a) and connected to the input end (c) to which electric potential higher than that at the input end (a) is supplied. At the same time, the cathode node (h) of the diode D4 connected to said node (g) is connected to the second output end P2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multi-output multi-voltage rectifier circuit which is an improved Kotscroft-Walton type voltage doubler rectifier circuit and is capable of taking out a plurality of different voltages.

[Technical Background of the Invention and its Problems] Conventionally, as a means for obtaining high DC voltage, a Cock-Clock-Walton type voltage doubler rectifier circuit, which has a simple circuit configuration, has been often used. This circuit has 95
A predetermined double voltage of the input voltage is obtained by combining several diodes and capacitors and sequentially switching the charging and discharging paths of each capacitor using the diodes in accordance with the polarity reversal of the alternating current voltage. By the way, in the rectifying circuit described above, by providing an output terminal at an arbitrary output terminal of each capacitor, different voltages can be obtained from the output terminals. However, in this rectifier circuit, the voltage fluctuation due to the load current is excessive, and the mutual influence of the voltage fluctuation due to each output current is large, so it is impossible to effectively output multiple outputs, and in reality, it is impossible to output multiple outputs. Unable to obtain multiplied voltage.

Furthermore, it is impossible to extract the desired voltage.

[Object of the Invention] This invention was made to improve the above-mentioned problems, and it is possible to provide a plurality of output terminals and adjust the voltage taken out from the output terminals to a desired voltage without depending on the number of multiplication stages. The object of the present invention is to provide a multi-output multiplier rectifier circuit that can be set.

[Summary of the Invention] That is, the multi-output multivoltage rectifier circuit according to the present invention includes a first input terminal to which a first AC voltage is applied, a second input terminal connected to a reference potential point, and the first input terminal connected to a reference potential point. a third input terminal to which a second AC voltage having a larger amplitude than the first AC voltage is applied; a plurality of diodes; a capacitor of the same number as the diodes; and a plurality of output terminals; diodes with the same rectification direction are connected in series, one end of which is connected to the second input terminal, and an even number of diodes adjacent to the connection point including one end and the other end of each of the series-connected diodes is connected in series. Half of the capacitors among the plurality of capacitors are connected in parallel between all the connection points of the second connection point, and arbitrary connection points among the even number connection points are respectively connected to the plurality of output terminals. The other end of the diode connected to the input end of the diode is connected to the first input end through one of the remaining half capacitors, and the even-numbered diode connection is connected to the output end. Each of the odd-numbered diode connection points next to the point is connected to the third input terminal through one of the remaining capacitors, and the remaining capacitors are connected between all other adjacent odd-numbered connection points. It is characterized by being connected.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 shows its configuration, and T in the figure is a transformer. An AC power supply A is connected to both ends of the first-order wire w1 of the transformer T, and the first to third terminals a of the secondary winding w2,
A multi-output multiplier rectifier circuit based on the present invention is connected to b and c. That is, the second terminal of the secondary winding W2 is a reference potential point connected to the ground point G, and the first terminal a is an intermediate terminal and is lower than the AC voltage generated at the third terminal C. An alternating current voltage with an amplitude level is generated. The anode of a diode D1 of a diode series circuit in which ten diodes D1 to DIO are connected in series is connected to this terminal. Here, if the connection points between the diodes of this diode series circuit are respectively 0 to m, and the cathode of the diode DIO is the output terminal n, then between a and e, between e and g, and between c
- between i, between i-, between k and m, between b and f, between f and h, h
Capacitors Cl and Cl0 of the same capacity are connected between -j, j-1, and NO-n, respectively. The connection points n and h are connected to the first and second output terminals P1 and P2, respectively, a load resistance R1 is connected between P1 and 22, and a load resistance is connected between P2 and the ground point 0. R2 is connected.

That is, this circuit is an improved Cottcroft-Walton type voltage doubler rectifier circuit having five multiplication stages. Among the capacitors C1 to C5 connected to the loads R1 and R2 via the diodes D1 to DIO, Connect the third capacitor C3 from the input terminal a side to the connection point g near the input terminal a.
and connect it to input terminal C, which is supplied with a higher voltage than input terminal a, and at the same time connect the cathode connection point of diode D4 connected to this connection point g to the second output terminal P.
2, and other than the above, it is a completely normal Kotscroft-Walton type voltage doubler rectifier circuit.

The operation of the above configuration will be explained below.

First, when there is no load, that is, when the load resistances R1 and R2 are both infinite, an alternating voltage with a voltage amplitude of EO1 [V] is generated between a and b of the secondary winding iW2 of the transformer T, and between c and b. Assume that an alternating voltage with a voltage amplitude EO2 [V] is generated. Now, considering the point in time when the potential of the terminal a of the secondary winding w2 of the transformer T becomes -EO1 [V] with respect to the ground potential, in this case the diode Di turns on, so b→D1→
The current flows in the order of e -C1-*a. Therefore, the capacitor C1 is charged to EOl[V] in a direction such that the point e is on the positive side. Then, point a becomes EOl[V
] In this case, since the diode D2 is turned on, a current flows in the order of a-Cl→e→D2→f-CB-b. Therefore, the capacitor C6 is connected to the voltage EO1 [V] occurring between a and b of the secondary winding W: and the charging voltage EOL [V] of the capacitor C1 in the direction where point i is on the positive side.
It is charged to 2EO1[V] which is the sum of . Here again a
When the point becomes -EO1 [V], diode D3 turns on, so b-CG Mf-'D3 →g-+C2→C1→
Current flows in the order of a. Therefore capacitor C2 is 2
In the direction where the point is on the positive side, the voltage EO1 [V] occurring between a and the secondary winding w2, and the charging voltage 2 of the capacitor CG.
EO1 [V] and charging voltage of capacitor CI - EOl [
2EO1 [V is charged by adding V. moreover,
When point a reaches EOl[V], diode D4 turns on, so a-I-C1→C2-g→D4-h-C7-CO
→ Current flows in the order of b. Therefore, the capacitor C7 has a b-a voltage EO1 [V], so that the h point is on the positive side.
Charging voltage of capacitor C1 01E [V], charging voltage of C2 2EO1 [V] and charging voltage of CG -2EO1[
V] is added to 2EO1[V]. Then,
When the 0 point becomes -EO2 [V], the diode D5 turns on, so current flows in the order of b-C6 → C7 → h-D5 → i → C3-"c. Therefore, the i point of capacitor C3 is on the positive side. In the direction of
It is charged to 02+ 4 E 01 [V]. Next, 0
When the point reaches EO2 [V], diode D6 turns on, so c →C3M i −”DO→j→C3-C7→C
Current flows in the order of 6→b. Therefore capacitor C8
is the mold pressure between c and b EO2 [V] in the direction where the three points are on the positive side,
Charging voltage of capacitor C3 E 02+ 4 E O[[
V] and capacitor CG.

2EO2 which is the sum of each charging voltage of C7 -2EO1 [V]
Charged to [V]. Below, in the same way, capacitor C5
, C9 and C10 are charged to 2EO2 [V] in the direction of the positive side of the m point, 1 point and n point, respectively.

That is, the output voltage between the first and second output terminals P1゜22 is defined by the series circuit of capacitors C8 to CIO, and the output voltage between the second output terminal P2 and ground point G is defined by the capacitors CB and C7. Specified in series circuit. Therefore P
The no-load output voltage between L-22 is 6EO2 [V], and the no-load output voltage between R2-0 is 4EOL [V].

Here, it is assumed that no load is left between PI-22 and a predetermined load is connected between R2-0. In other words, it is assumed that the load resistance R1 has an infinite resistance value q, and the load resistance R2 has a resistance value R[Ω].

Then, the current flowing through R2 is I2 [A], R2-
If the voltage between 0 and 0 is E2 [V], the capacitance of the capacitors C1, C2, CB, and C7 interposed between these is C[F], and the number of multiplication stages in this section is I2, then the Kotscroft-Walton By applying the formula for a type voltage doubler rectifier circuit, the following equation can be obtained.

However, f is the operating frequency of the input power source A, and I2 is n2-2 in this embodiment. When examining the voltage between Pi and 22 at this time, the 0 point is the ground voltage - EO2
In the state of [V], the capacitor C3 becomes b-+ as mentioned above.
CG -C7-oh-R5-1-1-1-C3-h c
The charging voltage is c-
The sum of the type pressure between B EO2 [V] and each charging voltage of capacitors CG and C7, that is, the type pressure between R2 and G E2 [V]
The sum is EO2+E2 [V]. then 0
If the point becomes +EO2[Vl, capacitor C8
As mentioned above, (-4C3-* i -* p
Q −e j →C8−+ C7−h C6−+ l
), the charging voltage is the voltage between c and b EO2 [VI, the charging voltage of capacitor C3 EO2 + E2 [the voltage between VI and P2-0 - R
2 is added to 2EO2[VI. Note that the charging of capacitors C4, C5, C9, and CIO is performed by sequentially transferring the charging voltage of capacitor C8 as described above, so that the charging voltage of each capacitor C4°C5, C9, and CIO is all 2EO2. [Becomes VI. Therefore PI-2
It can be seen that the no-load voltage is output between 2.

Next, it is assumed that a predetermined load is connected between PL-22 and no load is left between P2 and 0. In other words, the load resistance R2 has an infinite resistance value, and the load resistance R1 has a resistance value of R-[Ω].

Then, the current flowing through R1 is Il [A], PI
-22 capacitors C4, C5, C8°C
9. Let each capacitance of CIO be C[F], the input conditions be the same as in the case described above, and the description will be made according to an operation analysis of a Kotscroft-Walton type voltage doubler rectifier circuit in a general literature. First, the voltage drop e[VI caused by the current 1 supplied from the capacitor C10 to the load resistor R1 during one cycle of the input AC voltage is expressed as shown in the following equation. In addition, q
is the amount of charge to supply current ■1 during one period,
T is its period (-1/f).

This charge reduction generated in capacitor CIO is replenished by capacitor C5 every cycle. Therefore, the voltage drop occurring during one period of the capacitor C5 is also e[VI. Next, since the capacitor C9 supplies charge to the capacitor C5 and current to the load R1 every cycle, the voltage drop across the capacitor C9 becomes 2e[VI. Capacitor C4 supplies charge to capacitor C9, so capacitor C
The voltage drop during one cycle of 4 is 2e[VI. Similarly, since capacitor C8 supplies charge to C4 and current to load R1, a voltage drop of 3e[VI occurs. This capacitor C8 is replenished with charge from the capacitor C3. The operation up to this point is exactly the same as that of a normal Kotscroft-Walton type voltage doubler rectifier circuit having three multiplier stages.

However, when considering the operation when charge is supplied from capacitor C3 to 08, capacitor C is added to the current path.
Since B and C7 are present, the charge is also supplied to C6 and C7. Therefore, if a charge corresponding to a voltage change of 3e is supplied from 03 to 08, the voltage change occurring between bj will be 9e. Conversely, unless a voltage drop of 9e occurs between b and j, the capacitor C8 will not be able to supply the required amount of charge. However, since capacitors C6 and C7 are unloaded, no voltage drop can occur here. Therefore, all of this 9e voltage drop must occur across capacitor C8. Therefore, the capacitor C8 has a voltage drop of 9e when the charge supply to the load R1 and the capacitor C4 is completed, and a voltage drop of 6e when the charge supply from the capacitor C3 is completed. That is, the capacitor C8 causes an additional voltage drop of 6e compared to the case of a normal Kotscroft-Walton type rectifier circuit.

Further, since the charges to capacitors C4, C5, C9, and CIO are transferred from capacitor C8, the voltage drop in all of them increases by 6e. Therefore, the voltage drop in the output voltage to the load R1 has increased by 18e.

This voltage drop of 18e is determined by the number of multiplication stages related to load R2 and R
It is the value obtained by multiplying the product of the square of the number of multiplication stages related to 1 by e. Therefore, the output voltage El between Pi and 22 can be expressed as in the following equation. However, if the number of multiplication steps in this section is 01
Indicated by In this example, n1=3.

Cr (3) It has been confirmed through experiments and computer simulations that both equations (1) and (2) can calculate the output almost accurately.

Next, P2- under the conditions of R1-R-[Ω] and R2-oo
Considering the voltage between 0 and 0, when the 0 point becomes +E02, the current flows in the order of C → C3 → i → DB-j → C8-C7-CB → b, so 3e for one capacitor
voltage change occurs.

Therefore, since capacitors C6 and 'C7 are each reversely charged by 3e, the voltage between P2-0 rises by 6e from the no-load voltage. Then, if point a becomes -E, b-
Similarly to the above, a voltage change of 3e occurs for one capacitor in the order of 4CB→C7→h→D5→1-4C3-a. Therefore, all of the capacitors C3, Chi, and C7 return to their no-load voltages. All of these considerations have been confirmed by experiments and computer simulations. From the above, if there is no load between P2 and 0, even if load R1 is connected between Pi and P2, there will be a voltage ripple effect, but the voltage between P2 and G will be maintained at almost the no-load voltage. I know that it will happen.

Furthermore, when comparing equations (1) and (3), it can be seen that the voltage drop due to the load current between PL and P2 is somewhat large, but the input voltage (voltage between c and b) related to this period is set high. By doing so, it is possible to compensate for the voltage drop caused by the load current.

FIG. 2 shows another embodiment. However, in FIG. 2, the same parts as in FIG. 1 are denoted by the same reference numerals, and the explanation thereof will be omitted. In other words, this multi-output multi-voltage rectifier circuit
The capacitor C2 of the circuit shown in the figure is disconnected from the connection point e and connected to the C terminal of the secondary winding W2 of the transformer T, the connection point f is connected to the third output terminal P3, and a load is applied between P2 and 23. A resistor R2 is connected, and a load resistor R3 is connected between P3-0. In this case as well, as in the above embodiment, equations (1) to (3) hold true, and between PL and P2 and between P2 and 23, it is sufficient to replace them with R2-1, and between P2 and 23, and between P
For between 3-0, nl = n2-1 and (
Equations 1) to (3) may be applied.

Therefore, if a multi-output multi-voltage rectifier circuit configured as described above is used, even if multiple output terminals are provided, each output voltage can be independently set to an arbitrary multiplied voltage, and furthermore, even if multiple output terminals are provided, each output voltage can be set to an arbitrary multiplied voltage. between the output terminals (in the embodiment shown in the drawings, P
It is also possible to compensate for the voltage drop caused by the load current (between i and P2 or between P2 and 23) using the input terminal, and since the input voltage can be used multiple times, the output voltage can be set freely beyond the control of the number of multiplication stages. It becomes possible.

[Effects of the Invention] As detailed above, according to the present invention, the voltages taken out from a plurality of output terminals can be adjusted by making a slight change in the configuration of an ordinary Kotscroft-Walton voltage doubler rectifier circuit. It is possible to provide a multi-output multiplier rectifier circuit that can set a desired voltage regardless of the number of multiplication stages.

[Brief explanation of drawings]

FIG. 1 shows a circuit t+'? which shows an embodiment of the multi-output multiplier rectifier circuit according to the present invention. FIG. 2 is a circuit configuration diagram showing another embodiment of the present invention. A...AC power supply, T...transformer, Wl...-secondary winding, W2...secondary winding, D1~DIO...diode, 01~CIO...capacitor, R1-R3・・・
·Load resistance.

Claims (1)

[Claims] A first input terminal to which a first AC voltage is applied, a second input terminal connected to a reference potential point, and a third input terminal to which a second AC voltage having a larger amplitude than the first AC voltage is applied. It has an input terminal, a plurality of diodes, the same number of capacitors as the diodes, and a plurality of output terminals, the plurality of diodes are connected in series with the same rectification direction, and one end is connected to the half of the plurality of capacitors are connected in parallel between all the even-numbered connection points adjacent to the connection points including one end and the other end of each of the series-connected diodes. any of the even-numbered connection points are connected to the plurality of output terminals, and the other end of the diode connected to the second input terminal is connected to one of the remaining half capacitors. 1
of the remaining capacitors, and the odd-numbered diode connection point next to the even-numbered diode connection point connected to the output terminal is connected to the first input terminal through one capacitor of the remaining capacitors. A multi-output multivoltage rectifier circuit, characterized in that the remaining capacitors are connected to the third input terminal via the third input terminal, and the remaining capacitors are connected between all other adjacent odd-numbered connection points.