JPS62166613A - Signal detecting device - Google Patents

Abstract

PURPOSE:To improve the detecting ratio of a signal detecting device, by dividing signals from an alignment mark in connection with time and integrating each division, and then, correcting the integrated values by multiplying the integrated values by changeable fixed values. CONSTITUTION:Peak detection is performed on the output signal Sig of a photoelectric detector which is signals from the alignment mark of a mask 1 by means of a peak value detecting circuit 27. The peak detection is performed synchronously to the count-up of a counter 23 and the peak position and peak value are respectively stored in a memory 24 and RAM in the peak value detecting circuit 27. The gain of an amplifier 31 and threshold voltage of a binary coding circuit 14 are determined by the first laser scan. Namely, an integration circuit 32 integrates the output of the amplifier 31 and further obtains a roughly estimated changing value by multiplying the integrated value by a fixed value, and then, stores the roughly estimated value in its built-in RAM. Simultaneously, the peak value detecting circuit 27 detects the peak value of signals for each period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a signal detection device for detecting pulse signals sent to a pedestal in duplicate, and for example, when printing a mask pattern on a wafer in a semiconductor printing device, etc. The present invention relates to a signal detection device used to detect the position of each mark from an electrical signal obtained by optically scanning both alignment marks in order to efficiently measure the distance between alignment marks that are position identification marks.

[Description of Prior Art] In semiconductor printing equipment, etc., alignment between a mask and a wafer is achieved by, for example, scanning alignment marks for automatic alignment drawn in advance on each of the mask and wafer with a laser beam, and scattering the mark edges. Diffracted light is used for alignment information.

In this case, after the light receiving section optically removes the directly reflected light, the intensity of the scattered diffracted light from the edge of each alignment mark is photoelectrically converted into an electrical pulse, and this pulse position is determined by a clock counter. Generally, the distance between alignment marks, that is, the deviation, is determined by measuring the distance between the alignment marks.

Specifically, an alignment mark M as shown in FIG. 2(a) is used as a mask, as shown in FIG. 2(b).

A mark W is drawn on the wafer, and a laser beam is scanned over the alignment marks M and W on the mask 1 and the wafer 2 as shown in FIG. 2(d) using a device configured as shown in FIG. to find the deviation between each mark, move either the mask 1 or the wafer 2 according to this deviation, and then
The mask 1 and the wafer 2 are aligned relative to each other in the state shown in Figure (C).

FIG. 3 shows an example of an alignment system in a semiconductor printing apparatus. In the figure, 1 is a mask, 2 is a wafer,
3 is a moving stage, 4 is a moving stage that transfers the pattern of mask 1 to wafer 2.
This is a projection lens for transferring onto the image. 7 is a polygon mirror rotated by a motor 6, and the laser light emitted from the laser light source, for example, the tube 5, passes through the polygon mirror 7, mirror 8, beam splitter 11, objective lens 10, and mirror 9 to the mask 1 and the wafer 2. Scan the upper 7 alignment marks M and W. Scattered light from these alignment marks M and W passes through a mirror 9, an objective lens 10, a beam splitter 11, and a photoelectric detector 1.
Enter 2.

The output signal of the photoelectric detector 12 is an analog signal as shown in FIG. 2(e), and m1 in this signal.

m2 is a signal due to scattered light from mark M on mask 1,
W1 to W4 are signals caused by scattered light from marks W on the wafer 2. These signals are binarized by the comparator 14 in the control circuit 13 and become a pulse train as shown in FIG. 2(f). These pulse intervals are measured by a measurement clock oscillator 15 and a pulse interval measurement circuit 16.

Reference numeral 17 denotes a CPU that reads out the value of the measurement circuit 16, calculates the relative displacement between the mask 1 and the wafer 2 from this counted value, and controls the motors 18 and 19 so that the mask and wafer are in the correct positional relationship. Turn to drive the moving stage 3.

However, at this time, the output signal of the photoelectric detector 12 also includes a signal due to scattered light from sources other than the alignment mark (for example, a pattern for an actual device). For example, when the laser beam scans an area other than area a where the alignment mark is formed on the wafer 2 as shown in FIG. Assuming that there is an area b in which alignment marks and the like for the process are formed, the signal from the photoelectric detector will be as shown in FIG. 4 (2). Therefore, if these signals are taken in as they are, it becomes difficult to distinguish which signal is from the alignment mark, making alignment difficult. Therefore, in general, a signal like that shown in FIG. 4 (3) (hereinafter referred to as the 111J signal) synchronized with the start of scanning of the laser beam on the wafer surface is obtained by another photoelectric detector (not shown). Then, a signal (hereinafter referred to as a window signal) as shown in FIG. 4 (4) delayed by a certain period of time TDW from this synchronization signal is created, and the electric signal output from the photoelectric detector 12 is controlled by this window signal. Only signals from area a where alignment marks necessary for positioning are present are gated and extracted.

FIG. 5 shows in more detail the pulse interval measuring circuit 16 for detecting signals from the alignment marks of FIG. In the figure, the counter 20 counts the time Tpw in FIG. 4(4) upon arrival of the synchronization signal 3 ync in FIG. 4(3). Upon completion of this count, the counter 21 then counts the time TW of the window signal and generates a window signal that is at H level during this time TW.

The AND gate 22 has this wind signal @ at one input terminal.
TW is supplied, and a photoelectric detector 12 is connected to the other input terminal.
A mark detection signal obtained by converting the output signal Sig into a binary value by a comparator 14 is supplied. Therefore, this mark detection signal is selected by the gate 22 and supplied to the position measurement counter 25 only during the period Tw when the window signal is at H level.

The counter 23 is supplied with the mark detection signal output from the comparator 14, and updates the address of the memory 24 by incrementing it by 1 each time this signal is output. While the window signal is at the H level, the value of the position measurement counter 25 is written to the updated address of the memory 24 each time the mark detection signal is selected in ANDGOO 1 to 22. After the scanning by the laser beam is completed, the CPU 17 can read out the memory 24 to know the position of the alignment mark.

26 is a slice level (r: A value) setting circuit that determines the threshold voltage of the binarization circuit (comparator) 14, and is composed of a RAM whose address is updated by the output of the counter 23, a D/A converter, etc. There is. The contents of the RAM are set by CPtJ17 before measurement.

The peak value detection circuit 27 includes a peak hold circuit, an A/D
It is composed of a converter, a RAM, etc., and detects the peak of the electric signal Sig every time the electric signal Sig arrives from the photoelectric detector 12, A/D converts the value, and stores it in the RAM.

Next, the pulse interval measurement operation in the conventional alignment system will be explained with reference to FIGS. 3 and 5.

Prior to measurement, the CPU 17 first writes an appropriate threshold voltage into the RAM of the threshold value setting circuit 26. After that, mask 1 and wafer 2 are removed using a laser beam.
When scanning above, the comparator 14 detects the photoelectric detector 1
The signal Sig from 2 is compared with the threshold voltage, and an H level mark detection signal is generated at a portion where the signal Sig exceeds the threshold voltage. The counter 23 updates the address of the RAM of the peak value detection circuit 27 every time this mark detection signal arrives, and the signal level (peak value) from the photoelectric detector 12 is stored as a digital value in each address of the RAM. Next, CPU 17
The contents of this RAM are read out and appropriate threshold voltage values are set in the RAM of the circuit 26 for each signal.

When measurement is performed in this manner, an appropriate binary signal @ (mark detection signal) corresponding to the peak of each signal can be obtained, and measurement accuracy can be improved.

However, the signal from wafer 2 is generally
The part of the G-like mark where there is no signal (baseline)
The G lines are not always uniform; for example, on wafers that have undergone aluminum vapor deposition, the G lines are raised randomly as shown in Figure 6 (1) (this is called a pedestal). ).

This is because diffusely reflected light from the rough surface of aluminum enters the photoelectric detector.

In such a case, it becomes difficult not only to detect the peak of the signal level of the alignment mark on the wafer, but also to detect the alignment mark signal itself. For example, as shown in Figure 6 (1), even if the signal levels of Wl and W3 are low and you want to increase them by increasing the gain of the detection system, if the pedestal voltage level Vpd is high, increasing the gain will cause the detection system to may be saturated first at the pedestal voltage Vpd, and there is a limit to increasing the gain. Therefore, wafers processed in this manner have a problem in that the detection rate of signals from alignment marks is significantly reduced. Also, the 6th
Even in the case of a process where the signal level is extremely low as shown in FIG. 2, there is a problem in that if the gain is increased, the pedestal voltage Vlld is saturated first, making it impossible to detect the mark signal. Furthermore, a method has been considered in which the pedestal is reduced by integrating the signals from such alignment marks to obtain an average value and subtracting the average value. However, even in such a method, the pedestal value to be subtracted is just an average value, and while it is effective if the pedestal is ideal as shown in (1) in Figure 7, it is effective in (2) in Figure 7. With a waveform in which the pedestal is irregular, as in the case of the waveform shown in FIG.

[Object of the Invention] In view of the problems of the prior art described above, an object of the present invention is to provide an alignment mark for a wafer such as a rough aluminum surface where the baseline of the signal fluctuates or a wafer where the level and shape of the pedestal component fluctuates. The object of the present invention is to provide a signal detection device that can detect signals quickly and reliably.

[Explanation of Examples] Hereinafter, the present invention will be explained in detail using the drawings.

Note that parts common or corresponding to those of the conventional example are represented by the same reference numerals.

FIG. 1 shows a pulse interval measuring circuit 1 according to an embodiment of the present invention.
6 shows the block configuration of No. 6. In the figure, reference numeral 20 is a counter for counting the delay time Tpw from the arrival of the synchronizing signal 3 ync coming in from the signal line 5 ync to the generation of the window signal, and this time can be arbitrarily preset by the CPU 17. 21 is a counter for counting the time (Tw) of the window signal, which starts counting at the same time as the counter 20 counts up, and can also be preset by CP tJ 17. 25 is a position measurement counter, which includes the AND gate 22 shown in FIG. Each of these counters counts clock pulses output from the measurement clock oscillator 15 of FIG.

30 is a timing circuit which receives a window signal from the counter 21 and a signal TM from counters 28 and 29, which will be described later.
Based on I and TM2, a signal is generated to determine the operation timing of the threshold value setting circuit 2G, the single value detection circuit 27, the integrating circuit 32, the pedestal level setting circuit 33, etc.

Reference numeral 32 is an integration circuit which performs integration according to the timing signal from the timing circuit 30, and multiplies it by a constant value, which is the approximate change rate described later, to obtain an approximate change value, which is then input to the A/D.
It has a function of converting and storing it in RAM (included in circuit 32). The content of this RAM, that is, the integral value, is determined by the CPU.
It can be read by '17.

The pedestal level setting circuit 33 has a RAM that can be written by the CP tJ 17, and the output of this RAM is converted to/A and supplied to the J and width divider 31.

31 is a variable gain amplifier, the gain of which is CP
It is controlled by U17. Moreover, this amplifier 31
amplifies the difference between the signal @SIQ from the photoelectric detector 12 and the output of the pedestal level setting circuit 33.

A pedestal pattern storage circuit 34 stores a pedestal pattern input from an external console via an interface (encoder, etc.) 35.

Next, a third circuit to which the pulse interval measuring circuit 16 of FIG.
The operation of the alignment system shown in the figure will be explained.

First, CP tJ 17 sets the RAM of the circuit 33 so that the output of the pedestal level setting circuit 33 becomes 0■, sets the amplifier 31 to an appropriate gain, and also sets an appropriate value to the counter 20.21. set.

Further, an appropriate threshold voltage is set in the threshold value setting circuit 26. These levels, gains, count values, threshold values, etc. can be set in advance during system adjustment. In particular, regarding the threshold voltage, since the pedestal shape changes depending on the process, the pattern for each case can be entered from the console so that the appropriate threshold voltage can be set according to the process.

Subsequently, only the signal from the alignment mark of the mask 1 is measured in a state where there is no wafer signal (for example, before the wafer 2 is sent under the projection lens 4 in FIG. 3). That is, in a state where no signal from the wafer 2 enters the photoelectric detector 12, the peak value detection circuit 27 detects the peak of the photoelectric detector output signal Sig, which is a signal from the alignment mark of the mask 1. The peak detection timing at this time is performed in synchronization with the count up of the counter 23, and the peak position is stored in the memory 24 and the peak value is stored in the RAM in the peak value detection circuit 27. In general, signals from a mask have a higher signal level and are more stable than signals from a wafer coated with resist or the like, and in this method, only the mask signal can be detected with sufficient stability.

Next, the value of the slice level setting circuit 26 is appropriately reset based on the detected peak level, and only the signal of the mask alignment mark is measured again. After performing peak detection using this reset slice level,
The CPU 17 reads out the memory 24 and stores the positions of the alignment marks on the mask (TM1 and 7M2 in FIG. 9).
Detect.

Then, two signals m1. from the alignment marks of the mask. The count value of the counter 20 is preset to Tpw and the count value of the counter 21 (direct Tw) is preset so that the second mask signal is distributed equally to the center of the window signal.
and 7M2 are also preset in the counter 28]. The counter 29 counts a certain fixed time (TMD) at the same time as the counter 28 counts up, and this count time (TMD) is also preset by the cpU 17.

Next, the wafer 2 is sent under the projection lens 4 and measured. First, the gain of the amplifier 31 and the threshold voltage of the binarization circuit 14 are determined in the first laser scan.

That is, the integrating circuit 32 converts the output of the amplifier 31 into the output shown in FIG.
Integrate for each period of c-f in 2), roughly multiply the value by a certain value to obtain the aSS change value, and use them as the internal R
Store in AM. At the same time, the peak value detection circuit 27
The peak value of the signal is detected for each period f. After the laser scan is completed, the CPU 17 is connected to the circuit 27.3.
The peak value and approximate change value of 2 are read respectively.

FIG. 7 is a subtraction diagram of the pedestal waveform when the slice level is set using the average value as the pedestal portion. In the figure, ■1 is the signal component voltage, ■2 is the pedestal component voltage, ■3 is the average subtracted voltage derived from the integral value of the signal,
V4 is a correction waveform voltage, and Vs is a residual pedestal component voltage. Vs is the slice level, which is the baseline voltage of the correction voltage.

FIG. 8 is a subtraction diagram of the pedestal waveform after changing the average value based on the pedestal pattern input value and setting the slice level. In the same figure,
V6 is a pedestal pattern input correction subtraction voltage (hereinafter referred to as approximate change value voltage), Rv is an IR calculation change rate, and the approximate change $Rv is a constant value.

The estimated changed output value of the integrating circuit 32 will be explained below with reference to FIGS. 7 and 8.

In FIG. 7, the area inside the diagonal line is the average value, from which the average reduced voltage V3 is determined, and the slide level ys is determined.

First, considering the case (1) in Figure 7 (ideal pedestal waveform), the corrected waveform voltage can be found by simply subtracting the integrated value (average value) of the signal. If the pedestal has a different shape as shown in (2) in the figure, the residual pedestal component voltage v5 remains and it cannot be said that correct correction has been performed unless the pedestal is subtracted accordingly.

Therefore, in the case of FIG. 7(2), it is necessary to correct the signal by subtracting the product multiplied by the ratio (approximate change rate) to the pedestal component (integral value).

Here, the pedestal portion is a pedestal pattern measured using an oscilloscope or the like. In other words, it will reproduce the actual measured pedestal that was originally input from the console.

The reason why this is done is that in conventional steppers, etc., the change rate was set to a fixed value, so the slice level (derived by multiplying the average value by the integrating circuit by the above change rate) is not necessarily true. It did not reproduce the height up to the voltage of the pedestal. Therefore, using one wafer as a sample, the actual measured pedestal is determined using the oscilloscope or the like. Of course, this is
This idea was made because it is known that the pedestal pattern, which may be different depending on each process, remains almost the same in one process.

In particular, until now, the slice level (average value) from the integrating circuit was directly used as the pedestal component. This made it impossible to make changes mid-way as in the present invention. In other words, the key point of the present invention is that the control software of a semiconductor printing apparatus such as a stepper is improved to accommodate this change.

In this example, when exposing multiple wafers in the same process, one of the wafers is used to determine the "approximate change rate", and the other wafers are exposed using this "approximate change rate". The pedestal reduction sieve fraction is calculated. That is, let the measured value of the pedestal pattern be P, and the average value for each wafer be VA+, VA2, -, VAn,
Find the approximate change rate Rv = P/VA 1 and calculate the pedestal subtraction valve Vow for each wafer.

Vg2. ..., Von is the following formula % formula % Figure 8 is a diagram showing the state of this correction. Part) Enter as P from a console or the like and divide by the average value VAI of the sample wafer to find the approximate change rate RV. From now on, this approximate change rate R
Find the approximate change voltage Vam (1≦m≦n) by V,
This is set as slice level Vs (subtraction value of pedestal pattern). Thereby, the pedestal component can be successfully subtracted regardless of whether the signal has an ideal waveform as shown in FIG. 8(1) or not as shown in FIG. 8(2). Therefore, by performing this subtraction value for each interval, as shown in FIG. 9 (1), approximate change value voltages VG1 to VG corresponding to the baseline (pedestal) G of the signal at that time are obtained for each integral interval C to f. Vc, 4 is obtained, and these values are stored in the RAM in the pedestal level setting circuit 33.
is set to Further, the output values of the peak detection circuit 27 include the maximum peaks Vpl to Vp of each of the sections C to f.
4 is obtained. Next, CP u 17 examines these values and sets the gain of amplifier 31 as necessary.

That is, if the difference ρ between the minimum value among the peak values Vp1 to Vp4 and the maximum value among the estimated change value voltages Vcl to Vc4 is less than a certain value (Vk), the gain is increased by A times.

If you do this and perform another laser scan,
As the output of the amplifier 31, as shown in FIG. 9 (3), the value Vc, 1 is subtracted from the electrical signal Sig in the period C, the value Vc2 is subtracted in the period d, and the value Vc is subtracted in the period e.
3 is subtracted, and in period f, the value Vc4 is subtracted, and a signal in which only the signal of the alignment mark is accurately amplified appears.

In this way, the signal from the alignment mark on the wafer can be amplified while eliminating the rise in the baseline (pedestal) caused by the influence of irregular underlying surfaces (such as rough aluminum surfaces). It is possible to greatly amplify only the signal portion of a wafer that has undergone a large process or has a pedestal with an irregular level and shape due to diffused reflection from a rough aluminum surface.

Note that the integral value detection circuit 32 detects the integral value and inputs the in change value voltages Vc1 to VG to the pedestal level setting circuit 33.
By repeating the processing cycle consisting of setting 4 and increasing the gain of the amplifier 31, it is possible to amplify the signal component from the wafer alignment mark to the maximum S/N even for the wafer signal as shown in FIG. 7 (2). becomes.

[Effects of the Invention] As explained above, according to the present invention, the signals from the alignment marks are divided in time and integrated, and the integrated values are corrected by multiplying by a variable constant value, so that the signal can be calculated. Because the method is to know the baseline voltage and then subtract that value to increase the gain, the alignment mark can be adjusted even for wafers with irregular pedestal levels and shapes, or wafers with extremely low signal levels. It has become possible to greatly improve the detection rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pulse interval measuring circuit according to an embodiment of the present invention, FIG. 2 is a diagram illustrating alignment marks on a mask and a wafer, and FIG. 3 is a diagram of an alignment system in a semiconductor printing apparatus. Schematic configuration diagram; Figure 4 is a diagram showing alignment mark signal detection timing; Figure 5 is a more detailed block diagram of the pulse interval measurement circuit in Figure 3; Figure 6 is a signal level from the alignment mark. FIG. 7 is a subtraction diagram of the pedestal waveform based on the average value, FIG. 8 is a subtraction diagram of the pedestal waveform based on the pedestal pattern input value, and FIG. 2 is an operational waveform diagram of the circuit shown in FIG. 1. FIG. 1: Mask, 2: Wafer, 5: Tube, 7: Polygon mirror, 12: Photoelectric detector, 13: Control circuit, 14
: Binarization circuit, 15: Measurement clock oscillator, 16:
C/L/ sta 1ilj all constant circuit, 17
:, CPtJ, 20.21: Wind signal generation counter, 22: AND gate, 26: Threshold value setting circuit, 27:
Peak value detection circuit, 31 variable gain amplifier, 32:
Integration circuit, 33: Pedestal level setting circuit, 34: Pedestal pattern storage circuit, 35: Interface.

Claims (1)

[Claims] 1. A signal detection device for detecting a pulse signal in an electrical signal in which the pulse signal overlaps on a pedestal, comprising an integrating means for detecting the average value of the electrical signal, and a peak of the electrical signal. means for detecting the value; means for calculating and storing an approximate change value by multiplying the average value by a variable approximate change rate; means for subtracting and amplifying the approximate change value from the electrical signal; A signal detection device comprising means for controlling an amplification factor of the amplification means according to a difference between a peak value and a peak value. 2. The signal detection device according to claim 1, wherein the estimated change rate is calculated based on a constant value input from the outside and at least one of the average values. 3. The signal detection device according to claim 1 or 2, wherein the approximate change value and peak value detection means respectively receive the output signal of the amplification means and detect the approximate change value and peak value. 4. A claim in which the electric signal is a photoelectric conversion output of scattered light obtained by optically scanning an object, and the pulse signal is a scattered light detection signal from an alignment mark provided on the object. The signal detection device according to any one of Items 1 to 3. 5. The signal detection device according to claim 4, wherein the integrating means separately integrates the electric signal in each section divided in time according to the arrival timing of the alignment mark detection signal. 6. The electrical signal is a repeating signal with a constant period, and the amplification factor control means is configured such that the difference between the peak value and the estimated changed value is equal to or greater than a predetermined value based on the estimated changed value and peak value detection result in the previous cycle. Any one of claims 1 to 5, in which the process of increasing the amplification factor in stages is repeated until
The signal detection device described in .