JPS6216559B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a resin-sealed semiconductor device in which a semiconductor element including an N-type silicon Hall element is sealed with an insulating resin material. In recent years, with advances in research on semiconductor materials and manufacturing technology, several types of Hall elements have been put into practical use by utilizing the Hall effect known as the magnetosensitive effect. Indium antimony (InSb), gallium arsenide (GaAs), and other materials have better sensitivity to magnetic fields than silicon, but advances in integrated circuit technology using silicon have made it easier to form high-gain amplifier circuits. Thus, a so-called silicon Hall IC, which is an integrated circuit element incorporating a silicon Hall element that can obtain sufficient magnetic field sensitivity by combining the Hall element and an amplifier circuit such as a differential amplifier circuit, has been realized. This silicon Hall IC can contain not only an amplifier circuit but also peripheral circuits. In addition, it has advantages not found in other semiconductor materials, such as the ability to use ordinary silicon IC circuit technology and manufacturing technology as is. Furthermore, as with general semiconductor devices, a resin-sealed envelope made of insulating resin material is used for the purpose of protecting semiconductor elements, preventing deterioration, and maintaining electrical characteristics over a long period of time. Therefore, it has many advantages such as easy manufacture, excellent mass productivity, and low cost. Figures 1A to 1C show an example of a resin-sealed semiconductor magnetic sensing device, and Figure A is a cross-sectional view of the same resin-sealed semiconductor magnetic sensing device, and Figure B is a plan view. Figure 1 and Figure C are enlarged plan views of the main parts. In the figure, reference numeral 1 denotes a semiconductor element, which is placed and fixed on a base 2 made of, for example, a metal material, and is bonded to a metal lead 3 serving as an electrode terminal by a thin metal wire 4. This semiconductor element 1 is sealed with an envelope 5 made of insulating resin to constitute a resin-sealed semiconductor magnetically sensitive device 6 . Semiconductor element 1 has C in the same figure.
As shown in the figure, an epitaxial layer or a diffusion layer,
An N-type silicon Hall element 7 formed of an ion-implanted layer or the like is provided. The N-type silicon Hall element 7 includes current electrodes 8a, 8b and output voltage electrodes 9a, 9b formed perpendicularly to the current direction.
is formed. In the case of such a Hall IC, the semiconductor element 1 includes an N-type silicon Hall element 7.
In addition, transistors constituting a predetermined integrated circuit,
Elements such as diodes and resistors are formed at the same time. The N-type silicon Hall element 7 has inferior sensitivity compared to Hall elements such as indium antimony (InSb), and its Hall output relative to the magnetic field is minute, so it is practically impossible to achieve an amplification factor of at least one order of magnitude. requires an amplifier circuit with Therefore, even if the Hall element has a slight unbalanced output voltage, this equilibrium point will become very large, and the Hall
This has a serious impact on the normal operation of the IC. It is also possible to adjust the unbalanced output voltage from outside the IC, but this reduces the value of the IC. Therefore, it is necessary to suppress the unbalanced voltage generated in the Hall element as much as possible.
It is essential for improving IC performance. Among the causes of unbalanced voltage in Hall elements, factors such as the thickness of the active layer of the Hall element, non-uniformity in concentration distribution, etc., and electrode position shift have been significantly improved in practical terms due to advances in integrated circuit technology. and circuit design in advance,
This is a big problem because it is possible to design with yield in mind at the pattern design stage, and it is also possible to determine defective products through inspection before the assembly process, which prevents losses during the assembly process, which increases manufacturing costs. It is not. However, after the resin sealing process, strain due to the difference in thermal expansion coefficient between the sealing resin and silicon is applied to the semiconductor element 1, so there is a problem that the balanced voltage of the silicon Hall element 7 becomes unbalanced. Conventionally, in order to reduce the unbalanced voltage of the Hall element caused by such strain, a technical means has been proposed in which the silicon Hall element 7 is arranged in a crystal orientation where the strain sensitivity is minimized. This technical means utilizes the fact that the piezoresistance coefficient becomes almost zero by setting the crystal plane of the semiconductor element 1 to {110} and setting the current direction of the silicon Hall element 7 to the (100) or (110) crystal orientation. This is what I did. However, since the piezoresistance coefficient for all stress components cannot be made zero, unbalanced voltages generated by stress cannot be avoided, which poses a problem that hinders the improvement of precision and performance of Hall ICs. The present invention has been made in view of these points, and has a structure that minimizes the value of unbalanced voltage generated after the resin sealing process of a semiconductor element including an N-type silicon Hall element, and is highly practical. The present invention provides a resin-sealed semiconductor device. The present invention can be summarized as follows. One side of a silicon single crystal near the {100} plane or a semiconductor device whose substrate is the {100} plane is 45° from the [100] crystal orientation, or [100]
Parallel or perpendicular to the crystal orientation, parallel or perpendicular to a straight line in which the current direction passes through the center of the semiconductor element and is parallel or perpendicular to one side of the element, and
An integrated circuit including an N-type silicon Hall element formed such that its center is on or near the straight line is formed in the semiconductor element, and this semiconductor element is sealed with an envelope made of an insulating resin. This resin-sealed semiconductor magnetosensitive device achieves the above-mentioned objective by eliminating the adverse effects on N-type silicon Hall elements and the like caused by resin-sealing distortion by having such a structure. In addition, two N-type silicon Hall elements are formed in the same semiconductor element as described above with the center axis of the cross shape as the axis of line symmetry, and the current flowing in each N-type silicon Hall element is aligned with the center axis. This is a resin-sealed semiconductor magnetic sensing device that achieves the above objective by extracting Hall output in series with parallel flow. Hereinafter, the present invention will be explained with reference to the drawings. In the resin-sealed semiconductor magnetically sensitive device (hereinafter simply referred to as magnetically sensitive device) of the present invention, as shown in FIG. 2, for example, a semiconductor element 10 is formed on a semiconductor substrate made of silicon single crystal. Inside there are a square or rectangular N-type silicon Hall element 11 formed of an epitaxial layer, a diffusion layer, an ion implantation layer, etc., a circuit for amplifying the Hall output, a transistor, a diode, etc. constituting a peripheral circuit, etc.
It accumulates resistors, etc. The semiconductor element 10 is mounted and fixed on a base 12 made of metal or the like, and is bonded to metal leads 13 serving as electrode terminals by means of thin metal wires 14 . The semiconductor element 10 is
It is sealed with an envelope 15 made of insulating resin. Here, the semiconductor element 10 uses a silicon single crystal as a substrate, and the crystal orientation and the semiconductor element 1
The orientation of each side of 0 is one of those shown in FIGS. 3A to 3D. For example, in the case shown in FIG. 3A, the crystal plane orientation of the semiconductor element 10 is {100}, and each side of the semiconductor element 10 is parallel or perpendicular to the (100) crystal orientation. Similarly, Figure B shows the crystal orientation of each side in the case of the {811} crystal plane orientation, Figure C shows the crystal orientation of each side in the case of the {511} crystal plane orientation, and Figure D shows the crystal orientation of each side in the case of the {511} crystal plane orientation. {110}
In the case of crystal plane orientation, the crystal orientation of each side is shown. In the N-type silicon Hall element 11, a pair of current electrode terminals 16a and 16b are formed facing each other near opposing sides of the N-type silicon Hall element 11. Furthermore, a pair of output voltage electrode terminals 17a and 17b are formed on the other two opposing sides. In addition, 18a and 18b in the figure represent the semiconductor element 1.
These are the center lines that pass through the center of 0 and are parallel or perpendicular to each side, and these are temporarily defined as the x ₁ axis and the x ₂ axis. The x ₁ axis 18 a and the x ₂ axis 18 b are orthogonal to each other at the center of the semiconductor element 10 to form a cross-shaped central axis 19 . As is clear from FIG. 2, the N-type silicon Hall element 11 has its current direction aligned with the x ₁ axis 18a or the x ₂ axis 1
8b, and the center of the N-type silicon Hall element 11 is aligned with the x ₁ axis 1.
8a or the x ₂ axis 18b (here, on the x ₁ axis) or in the vicinity thereof. According to the magnetic sensing device 20 configured in this way,
N-type silicon Hall element 11 caused by stress
The unbalanced voltage V ₀ of is determined by the piezoresistive effect. Now, as shown in FIG. 4, the output voltage electrode terminal 17 is connected to the N-type silicone Hall element 11.
a, 17b direction is x ₁ coordinate axis, current electrode terminal 16
An x 1 -x 2 _-x 3 coordinate axis is defined in which the a and 16b directions are the x ₂ coordinate axis, and the direction perpendicular to these coordinate axes is _{the x 3 coordinate axis} . The unbalanced electric field E ₁ (x ₁ ) in the direction of the x ₁ coordinate axis is calculated from the piezoresistive effect using the density J ₂ (x ₁ ) of the current flowing through the Hall element. That's what I find. Here, ρ is the resistivity of the N-type silicon Hall element 11 π ₆ 〓 is the piezoresistance coefficient tensor, τ 〓
(x ₁ x ₂ ) is a stress tensor component and generally varies depending on the position within the semiconductor element 10. Note that τ ₁ =σ _x
1 , τ ₂ = σ _x2 , τ ₃ = σ _x3 , τ ₄ = τ _x2x3 , τ
₅ = τ _x3x1 and τ ₆ = τ _x1x2 . From equation (1), the unbalanced voltage V ₀ is becomes. From equation (2), in order to make V ₀ zero, π ₆ 〓 or ∫ ^w _−w τ〓 (x ₁ , x ₂ ) dx ₁ is from β=1 to β=6
It would be good if everything became zero. Figures 5A to 5D show the crystal orientation dependence of the piezoresistance coefficient π ₆ 〓 of N-type silicon. Figure C corresponds to the {511} plane, and figure D corresponds to the {110} plane. From the crystal orientation dependence characteristics of the piezoresistance coefficient shown in FIGS. 5A to 5D, the piezoresistance coefficient (π ₆
〓) (β = 1 to 6) is the minimum value.
Shown in the table.

[Table] From the same table, for {100} plane [100] direction and {110} plane [100] direction or [110] direction, π ₆₁ = π ₆₂ = π
₆₃ = π ₆₄ = π ₆₅ = 0, π ₆₆ ≠ 0, and in the direction of 45° from [110] of the {811} and {511} planes, |π ₆₆
｜＞｜π ₆₁ ｜, ｜π ₆₂ ｜, ｜π ₆₃ ｜, ｜π ₆₄ ｜, ｜
It can be seen that π ₆₅ ｜〓0. In any case, the effect of π ₆₆ is the largest, so equation (2) is expressed as V ₀ 〓−ρJ ₂ π ₆₆ ∫ ^w/2 _−w/2 τ ₆ (x ₁ , x ₂ ) dx ₁ in each of the above directions. (3) On the other hand, when we formed a large number of stress sensors using the piezoresistance effect on the surface of a semiconductor element and experimentally examined the stress distribution on the surface of the semiconductor element by resin sealing, we found that the state of the distribution of each stress component was It became clear that there was an extremely good symmetry within the structure. In this experiment, the rectangular or rectangular semiconductor elements 10 are arranged approximately in parallel to each other approximately at the center of the rectangular or rectangular envelope 15. FIG. 5E shows the distribution of the stress component τ ₆ within the semiconductor element obtained from this result. In addition,
The specifications of the sample used for the measurement in FIG. 5E are as follows. Semiconductor element 10 is 3×3mm thick and 300μ
m, the envelope 15 is a DIP24pin package and the thickness is
The 3.5 mm metal base 12 is made of phosphor bronze with a thickness of 250 μm and is located approximately at the center of the envelope 15 and approximately at the center of the envelope 15 in the thickness direction. The sealing resin was formed from phenol novolac epoxy resin at 175°C. As is clear from FIG. 5E, the semiconductor element 10
The distribution of the stress component τ ₆ within the x ₁ axis 18 is shown in Figure 2.
Since the distribution is symmetrical with sign inversion with respect to the a and _x2 axes 18b, as shown in FIG. 2, the center of the N-type silicon Hall element 11 is on _{the x1} axis 18a or By arranging the current direction parallel to the x ₁ axis 18a or the x ₂ axis 18b, equation (3) can be expressed as V ₀ = ρJ ₂ π ₆₆ 〓∫ ^o _−w τ ₆ (x ₁ , x ₂ )dx ₁ +∫ ^w/2 _p τ ₆ (x ₁ , x ₂ )dx ₁ 〓〓0. That is, the direction x ₁ axis 18a or x ₂ of one side of the semiconductor element 10 whose substrate is silicon single crystal
By setting the axis 18b as either the x ₁ crystal axis or the x ₂ crystal axis shown in FIG. 3, and arranging the center of the N-type silicon Hall element 11 so as to substantially coincide with the coordinate axes 18a and 18b, resin sealing strain can be reduced. The unbalanced voltage of the N-type silicon Hall element 11 caused by this can be almost completely eliminated. According to the magnetic sensing device 20 of the present invention configured as described above, it is possible to almost completely eliminate the unbalanced voltage of the N-type silicon Hall element 11 caused by the stress applied to the semiconductor element 10 after resin sealing. The performance of the element 10 before the resin sealing process can be maintained almost as it is and can be utilized even after the resin sealing process. Further, since it is not necessary to make full use of special resin sealing technology, the present invention has the advantage of being highly productive and highly practical, and can be applied to various Hall ICs. Next, examples of the present invention will be described. In addition, in the following Examples 1 to 4, unless otherwise specified, the following specifications are used. The envelope is made of phenol novolac epoxy resin with a thickness of 3.5 mm.
DIP (Dual Inline Package) 16pin temperature 175
Form at °C. The semiconductor element has a size of 3 mm x 3 mm and a thickness of 300 μm, and is fixed approximately parallel to the envelope at approximately the center of the envelope. The metal base and floor were made of phosphor bronze. The N-type silicon Hall element has a thickness of 5 μm.
An N-type epitaxial layer with a thickness of 0.5 Ωcm was used. The size of the N-type region of the N-type silicon Hall element is 230 μm.
×230μm, and the distance between the two current electrode terminals is 190μm.
m, the output voltage electrode terminals are arranged at a spacing of 200 μm on the line of symmetry between the two current electrode terminals. In the measurement, a voltage of 10V was applied between the current electrode terminals, and the magnitude of the unbalanced voltage generated between the output voltage electrodes before and after the resin sealing process was measured. Measurements range from 25 to 50
It is shown as the average value of several samples. Example 1 As shown in FIG. 6A, a silicon semiconductor device 61
Define coordinate axes x-axis 63a and y-axis 64b that pass through the center 62 of the semiconductor element 61 and are parallel to each side of the semiconductor element 61,
= 1000μm, passing through y = 1000μm, y-axis 64b, x
The N-type silicon Hall element 65 was arranged so that the centers were points ak and 1 on straight lines 63b and 64b parallel to the axis 63a, respectively. There are two types of current electrode terminal directions of the N-type silicon Hall element 65: parallel to the y-axis 64b and parallel to the x-axis 63a, and in each case, the semiconductor element 61 is on the silicon {100} plane and the x-axis direction is [ 100] and the case where the x-axis orientation was [100] on the silicon {110} plane. The evaluation results were as shown in Table 2. From this result, the arrangement of the N-type silicon Hall element 65 and the current direction are shown in FIG. 6B.
parallel to the axis 63a or the y-axis 64a, and the center of the N-type silicon Hall element 65 is parallel to the x-axis 63a or the y-axis
It can be seen that installation on axis 64a is most desirable. Furthermore, it can be seen that a considerable effect is observed up to about 13 regions of the size of the element centered on the x-axis 63a and the y-axis 64a. (Region 66 in Figure 6) From this experiment, it was found that the N-type silicon Hall element 6
It can be seen that the arrangement of No. 5 may be any of the cases shown in FIG. 6B. Note that in FIG. 6B, the x-axis 63a and the y-axis 64a are coordinate axes that pass through the center of the semiconductor element 61 and are parallel or perpendicular to each side of the semiconductor element 61, as in FIG. 6A. Further, the semiconductor element 61 uses a silicon single crystal as a substrate, and its plane orientation is {100} or {100},
The x-axis orientation is parallel or perpendicular to the [100] crystal axis, respectively.

[Table] Example 2 N-type silicon Hall element 7 as shown in FIG.
4 and 75 are arranged at the center of the semiconductor element 71 and on the y-axis 73 at an angle θ with respect to the x-axis 72. Here, the plane orientations of the semiconductor element 71 are {100} and {110},
u fixed to N-type silicon Hall elements 74 and 75
−v coordinate system direction [100] and [100] respectively
Or parallel or perpendicular to the direction. 0 as θ
Table 3 shows the results of experiments conducted at angles of 15°, 30°, and 45°. From this, it has been found that it is desirable that the current direction of the N-type silicon Hall elements 74 and 75 be parallel or perpendicular to one side of the semiconductor element 71.

[Table] Example 3 The arrangement of the Hall element is set to θ=0 in FIG. 7, the crystal plane orientation of the silicon semiconductor element 71 is set to the {811} and {511} planes, and the x-axis direction is set at 45 degrees from the [110] crystal axis.
Parallel or perpendicular to the direction of °. Table 4 shows the measurement results of the unbalanced voltage V ₀ generated by the resin sealing at this time. From the same table, {811} plane, {511}
It was found that the effect on the {100} surface is almost the same as that on the {100} surface.

[Table] Example 4 The structure of the Hall element is as shown in FIG. 8, in which two N-type silicon Hall elements 81 and 82 of the same shape are arranged in parallel, and voltage electrode terminals 84 and 85 are connected with metal wiring. do. The Hall output at this time is obtained from the electrode terminals 83 and 86. Hall element 8
1 and 82 were arranged as shown in af and mq of FIG. 6, and the unbalanced voltages were measured using the combinations shown in Table 5. The current flows through the respective current electrode terminals 87, 88.
are connected in parallel and between these terminals 88 and 87.
Flow by applying a voltage of 10V. N-type silicon Hall elements 81 and 82 were arranged so that the current direction was parallel to the y-axis as shown in FIG. 6A. The crystal plane orientations of the semiconductor element 61 were {100} and {110} planes, and the x-axis direction was parallel or perpendicular to the [100] crystal axis, respectively. The measurement results are shown in Table 5.
As can be seen from the comparison with the results in Table 2, it is possible to eliminate unbalanced voltage even if the two Hall elements 81 and 82 are arranged symmetrically on the y-axis. In addition,
The two Hall elements 81 and 82 may be arranged symmetrically on the x-axis. At this time, the current direction may be made parallel to the x-axis. In the N-type silicon Hall elements 81 and 82 having such a structure, the unbalanced voltage generated due to stress is expressed as in equation (3): becomes. Here, π ₆ is a symmetric distribution with sign reversal on the x ₂ axis, that is, x ₁ = 0, so becomes. In the above equation, x ₀ is the distance from the y-axis to the center of each Hall element in FIG. 8B, and W is the distance between the voltage electrode terminals of each Hall element.

[Table] Note that the present invention is not limited to Examples 1 to 4 above,
For example, the semiconductor element may be rectangular instead of square, and the resin-sealed envelope may also be square instead of rectangular. Furthermore, the N-type silicon Hall element may be formed not only from an epitaxial layer but also from an impurity diffusion layer or an ion implantation layer, and its shape and size may be determined according to its design specifications.
However, since distortion occurs at the peripheral edge of the semiconductor element and the unbalanced voltage varies widely, it is preferable to form it inside the semiconductor element by at least the thickness thereof. Furthermore, when using a differential amplifier in the first stage of a Hall output amplifier circuit, it is desirable that the two transistors be installed symmetrically to the center line of the semiconductor element, and the P-type bias resistor element also be installed symmetrically to the center line. . In particular, the piezoresistance coefficient for a P-type resistor is minimum in the silicon [100] crystal axis direction, so when it is on the {100} plane, it is formed parallel or perpendicular to the semiconductor element, and when it is on the {110} plane, it is formed in the [100] direction. It may be formed parallel to the crystal orientation. As explained above, according to the resin-sealed semiconductor magnetic sensing device according to the present invention, the unbalanced voltage generated due to the resin-sealed strain of the N-type silicon Hall element formed in the silicon semiconductor element is lowered, and the N-type silicon Hall element formed in the silicon semiconductor element is lowered. It is possible to provide a highly practical resin-sealed semiconductor magnetosensitive device that can sufficiently maintain the electrical characteristics of a Hall IC including a silicon Hall element even after resin-sealing.

[Brief explanation of the drawing]

1A is a sectional view of a conventional resin-sealed semiconductor magnetic sensing device, FIG. 1B is a plan view of the device, FIG. 1C is an enlarged view of the main part of the device, and FIG. 3A to 3D are plan views of such a resin-sealed semiconductor magnetosensitive device, and FIG. 4 is an explanatory diagram showing the relationship between the crystal plane orientation and the crystal orientation of each side. 5A to 5D are characteristic diagrams showing the dependence of the piezoresistance coefficient on crystal orientation; FIG. 5E is a distribution diagram showing the distribution of stress components within the semiconductor element; 6A and 6B are explanatory diagrams of one embodiment of the present invention, and FIGS. 7, 8A and 8B are explanatory diagrams of another embodiment of the present invention. 10... Semiconductor element, 11... N-type silicon Hall element, 12... Base, 13... Metal lead,
14...Thin metal wire, 15...Envelope, 16a, 1
6b...Current electrode terminal, 17a, 17b...Voltage electrode terminal, 20 ...Resin-sealed semiconductor magnetosensitive device.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate made of a silicon single crystal sealed with an insulating resin member, a crystal plane formed on the semiconductor substrate having a {100} crystal plane, and one side of which has a [100] crystal orientation. In a resin-sealed semiconductor magnetosensitive device comprising a square or rectangular semiconductor element parallel or perpendicular to the semiconductor element and an N-type silicon Hall element formed within the semiconductor element, the N-type silicon Hall element is The current direction of the N-type silicon Hall element is directed to the parallel or perpendicular region through the center of the semiconductor element. 1. A resin-sealed semiconductor magnetic sensing device characterized by flowing along the same direction. 2. The resin-sealed semiconductor magnetic sensor according to claim 1, wherein the width of the central region is 1/6 of the distance from the central axis passing through the center of the semiconductor element to one side facing the central axis. Device. 3. A patent claim in which a semiconductor element is sealed approximately at the center of a square or rectangular envelope made of an insulating resin member such that each surface of the semiconductor element is approximately parallel to each surface of the envelope. A resin-sealed semiconductor magnetically sensitive device according to item 1 or 2. 4. A semiconductor substrate made of a silicon single crystal sealed with an insulating resin member, and a crystal plane formed on the semiconductor substrate whose orientation is a {100} plane, and one side of which is parallel or perpendicular to the [100] crystal orientation. In a resin-sealed semiconductor magnetosensitive device comprising a square or rectangular semiconductor element and an N-type silicon Hall element formed within the semiconductor element, two identical N-type
A pair of N-type silicon Hall elements are formed, and each N-type silicon Hall element is passed through the center of the semiconductor element, and the central axis of a cross formed by a center line parallel to one side of the semiconductor element and a center line perpendicular to the semiconductor element is the axis of line symmetry. 1. A resin-sealed semiconductor magnetically sensitive device, characterized in that the current direction of each N-type silicon Hall element is parallel to the central axis of the semiconductor element, and the current direction of each N-type silicon Hall element is parallel to the current direction of the N-type silicon Hall element. 5. A patent claim in which a semiconductor element is sealed approximately at the center of a square or rectangular envelope made of an insulating resin member such that each surface of the semiconductor element is approximately parallel to each surface of the envelope. The resin-sealed semiconductor magnetically sensitive device according to item 4.