JPS62164381A - Clamping circuit in analog/digital converter - Google Patents

Abstract

PURPOSE:To attain a digital conversion with high stability and high dynamic range by controlling a conversion minimum grade level in an A/D converter at the optimum level. CONSTITUTION:A digital video signal from an A/D converter 2 is compared with the output of a clamp level setting circuit 16 at a comparator 15, and when the output of the A/D converter 2 is larger, signals of H and L are outputted respectively to AND gates 17 and 18. A clamp pulse from a clamp pulse generation circuit 19 is inputted to the AND gates 17 and 18, and either of analog switches 20 or 21 is turned on, and a voltage of positive polarity from a reference power source 22, or a voltage of negative polarity from a reference power source 23 is supplied to an estimating capacitor 26, and an electric charge is accumulated or discharged. The output voltage of the capacitor 26 is inputted to an adder circuit 11 through a buffer amplifier 27, and the lowest grade DC level of the video signal is decided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a clamp circuit for setting a clamp level when digitally converting an analog video signal obtained from one return fishing means.

[Technical Background of the Invention] In recent years, television video signals have been digitally converted to emphasize edges in displayed images, or to enhance i1i! in still images. Techniques that damage image processing, such as subtraction processing that highlights only the areas where a change in intensity has occurred, are becoming popular, and this digitization technique for video signals has become popular even in general home televisions. In particular, in medical images, it is necessary to identify the minute tissues of the subject, so there is a demand for higher precision in digital image processing year by year, and in fact, the resolution of the image is extremely high. It has become to.

Therefore, in the analog/digital converter (hereinafter referred to as A/D converter), which is the step on the 1st side of the lζth ff that performs image processing, the advanced clamping technology that determines and fixes the reference level for digitization at 8q is required. ization has been required.

FIG. 4 shows a conventional clamp circuit. 2 is an A/D converter, 3 is a coupling capacitor that cuts the DC component of the video signal, 4 is a switching element for clamping, 5 is a resistor that indicates the impedance of the circuit, 6 is a standard 7fi source that determines the clamp level, 7 indicates a clamp pulse for specifying the clamp portion of the video signal. Next, the clamping operation of the iron frame signal will be explained with reference to FIG. The analog video signal 8 output from the television camera generally includes only an alternating current component, and either does not include a direct current component or is uncertain.

In addition to this video signal 8, most of the signals are horizontal synchronization signals @(
HD signal)9. Vertical synchronization signal (contains various synchronization signals such as VD double signal. Such video signal 8 is input to A/D'
In order to achieve efficiency J: digitalization with the limited dynamic range of the two-way converter, it is necessary to A/D convert only the video signal valve, excluding synchronizing signals and the like. Therefore, the video signal is clamped so that the lowest level of the video signal 8 matches the lowest level of the A/D converter 2. This is called a clamp operation, and it has the basic configuration as shown in FIG. 4 mentioned above, and is normally operated as shown in FIG. i
The flat part between 8 and 8 is clamped to fix the level using direct current.

[Problems in the background art] In the conventional circuit shown in FIG.
As shown in FIG. 5, the above-mentioned specific portion of the composite video signal consisting of the video signal 8 and the HD signal 9 is fixed using the video signal 8 and the HD signal 9. To explain in detail, control l1 (not shown)
Clamp pulse 7 supplied from the unit at a predetermined timing
When the switching element is turned on by , the potential of the composite video signal is fixed to the voltage Ek of the reference power supply 6 during that time. At this time, the output from TV camera 1 and the reference voltage E
The potential difference from k becomes a potential difference across the coupling capacitor 3 and is charged in the capacitor 3, and is retained as a DC component even if the switching element 4 is turned off afterwards, so that the subsequently input video Signal 8 begins to rise above the level of reference voltage Ek. If the voltage Ek, which is this clamp level, is set to the lowest level of the input of the A/D converter 2, the lowest level of the video signal valve corresponds to the lowest level of the digitized output.

In such conventional technology, switching elements and A/
The clamp level may fluctuate due to the low characteristics of the D conversion converter itself, and the DC component held in the coupling capacitor may also be affected by the impedance R of the circuit shown in Figure 4.
There is a drawback that the time constant R changes until the next clamp pulse after the HD signal arrives, and the video signal includes a slope component called a dip.

[Object of the Invention] The present invention has been made in view of the circumstances of
The object of the present invention is to provide a clamp circuit that enables digital conversion with high stability and high dynamic range by optimally controlling the lowest conversion level of a 9j converter.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention includes an analog/digital converter that digitally converts an analog video signal received from a television camera, and an input terminal for inputting the output of this analog/digital converter. and a comparison control means for controlling the error to a minimum by comparing it with a predetermined clamp level; A clamping operation that operates the clamp level determining means for outputting the level and the comparison control means at a predetermined timing according to the horizontal synchronization signal superimposed on the video signal! 111 means.

[Miura of the Invention (1i!) Based on FIG. 1, a case where the configuration of an embodiment of the present invention is applied to a digitalized x!9 diagnostic device will be explained. The same numbers are used for the components.

Although not shown, the image intensifier (1, 1,) captures the transmission information obtained when the X-rays emitted from the X-ray tube pass through the subject. The optical image converted by the X-ray television camera 10 is imaged. Then, the DC level of the analog composite video signal outputted from the Xa television camera 10 is determined by the adder circuit 11 via the coupling capacitor 3, and is input to the A/D converter 2. The digital composite video output from this A/D converter 2 (t@ is the output from the digital processor 1
2, the processing described below is executed. Then, the digital video signal that has been subjected to the desired image processing is sent to the next stage D.
The signal is converted into analog by the /A converter 13 and output to the monitor 14 for display.

1) An overview of the digital processor 12 will be explained with reference to FIG. That is, the output video signal of the A/D converter 2 is input to the arithmetic unit 121, and the output of this Enkyo Unit I-121 is one of the first . One is output to the second frame memory 122, 123, and the other is output to the image enhancement circuit 124.

The performance unit h 121 selects which one to output to based on a control signal from a system control unit (not shown).

And the first. The outputs of the second frame memories 122 and 123 are again input to the calculation units 1-121. Also,
The output of the image enhancement circuit is output to a D/A converter 13 on the ship for display.

The output of the A/D converter 2 described above is supplied to the comparison control means CC having the following configuration, and is first connected to the first input terminal of the comparator 15. A ramp level setting circuit 16 is connected to a second input terminal of the comparator 15 so that a clamp level corresponding to the digital data can be appropriately set. Furthermore, the output of this comparator 15 is connected to one input terminal of two NO gates 17,18. The other input terminals of this AND game 1-17, 18 are connected to the output of a clamp pulse generation circuit 19 which inputs the analog composite video signal output of the X-ray television camera 10 and generates a clamp pulse. Each output of these two AND switches 1-17.18 is connected to two analog switches 20.
Each input of the analog switch 20.21 is connected to a positive and negative reference power source 22.23 via a resistor 24.25, respectively. Also, each analog switch 20.21
The outputs of are connected to each other and to the input of a buffer amplifier 27 via an integration capacitor 26.

Moreover, the output of this buffer amplifier 27 is Iy+3! It is connected to the negative side input of the adder circuit 11.

Next, the operation of the above-mentioned constituent device will be explained with reference to FIG. 3 as well.

X-ray television camera 10 that captures the object's IjI information
outputs a decomposed image signal including an analog video signal as shown in FIG. 3(a). One side of this video signal is
A predetermined DC level is output to the A/D converter 2 via the charged coupling capacitor +13 and the addition circuit 11.

The other side of the composite video signal is the clamp pulse generation circuit 1.
9, this circuit generates a trigger pulse at a timing delayed by a predetermined short time from the HD signal (see Figure 3 (b)), and forms a clamp pulse based on this (see Figure 3 (b)). (see Figure 3 (C))) is supplied to the next stage.

Therefore, the digital video signal output from the A/D converter 2 is input to the comparator 15 and compared with an arbitrarily settable level output from the clamp level setting circuit 16. The clamp level is generally set several gradations above the minimum output of the A/D converter 2. For example, in a 12-bit A/D converter, the minimum output is I
Q II: If the maximum output is '4095'', set the clamp level to 5''. Then, the comparator 15 compares whether the output of the A/D converter 2 is greater than 5" or not, and the output of the A/D converter 2 is at the clamp level "5".
If larger, AND goo 1-1 through line A
An I''ioh level signal is output to one input of the AND gate 18, and an I'' level signal is output to one input of the AND gate 18 via a line B.
An ow level signal is output.

It should be noted that if the comparison result is the opposite, the effect is opposite to that described above.

Each AND inputs the output of this comparator 15 and the clamp pulse from the clamp pulse generation circuit 19 mentioned above.
When the AND logic is established for one of the switches 1-17 and 18, one of the analog switches 20 and 21 is turned on. As a result, if the AND gate 17 is established, the positive polarity voltage from the reference power supply 22 is applied to the resistor 24. The signal is supplied to the 8I calculation capacitor 26 via the analog switch 20, and the electric charge is accumulated to increase the potential. Conversely, if the AND gate 1B is established, the negative polarity voltage from the reference power supply 23 is applied to the resistor 25. The charge is supplied to the integration capacitor 26 via the analog switch 21, and the charge is discharged. Note that the A/D converter 2 converts the 10 MHz A/D during the period in which the clamp pulse of a predetermined width is output.
'! ! Since the output is updated many times according to the switching frequency, the output of the comparator 15 changes each time, and the two analog switches 20 and 21 are alternately set to 0N10FF. As a result, the voltage accumulated in the accumulation capacitor 26 is converted into an averaged analog output, and the noise appearing in the digital output is removed by this averaging action. The output voltage of the integration capacitor 26 is suitably amplified by the high input impedance buffer 1 amplifier 27 and inputted to the negative input terminal of the adder circuit 11 to determine the lowest current level of the video signal. The above control is performed continuously when a clamp pulse is generated from one clamp pulse generation circuit, and the analog switches 20 and 21 are turned off during the period when there is no clamp pulse, so this voltage is applied to the product capacitor. 'j-26, and the clamp level of the addition circuit 11 is fixed during that time.

By such "clamp and hold",
The lowest level of the video signal is fixed at a set clamp level and digitized.

When the lowest level of digital conversion is held in this way, the video signal 8 that arrives at the A/D converter 2 after that is a high level that does not include noise from the comparator 1°5, analog switches 20, 21, etc. Accurate and stable digital conversion is performed and supplied to an arithmetic unit 121 within the digital processor 12. For example, a video signal (mask f
The image signal after contrast agent injection (contrast 1 to image) is stored in the first frame memory 122 and the second frame memory 123, and calculations are performed according to an address signal from a control unit (not shown). A unit 121 performs subtract processing between the mask image and the contrast l-image. As a result, only the blood vessels in which the contrast agent is present are obtained;
The image enhancement circuit 124 at the next stage performs processing to make the image more visible, for example, to make areas with high spatial frequencies stand out.

Thereafter, the digital image signal processed by the D/A converter 13 is converted into an analog signal and displayed on the monitor 14.

According to the embodiment device described above, for example, a 12-bit A/D converter has a resolution of 4096 gradations, and the conventional method eliminates temperature drift and sub-components of A/D conversion products and various switch elements. However, in order to compare and feed back the digital outputs as described above, temperature drift is corrected, and conventionally, while operating the A/D converter, Previously, the clamp voltage had to be adjusted to 1υ'':aIII using the volume, but now it is now possible to set the desired clamp level in advance without having to adjust it.

Furthermore, since the bold circuit can be made into a high-impedance circuit regardless of the video 1 word line, it is possible to minimize the dip component due to fluctuations in the clamp level of the unclamped 111]l7il from one clamp to the next clamp. It has become possible. In this way, the clamping accuracy can be set to ±1 gradation including the noise even if the noise component is 1N gradation or more. Therefore, the higher the resolution of the A/D converter, the greater the effect. Furthermore, by using a lamp level setting circuit like this in a digital X-ray diagnostic system and performing subtraction processing between mask images and contrast images, even minute blood vessels that cannot be identified with normal fluoroscopic images can be detected. It can be abstracted, further increasing the diagnostic effect.

It should be noted that the present invention is not limited to the above embodiments, and can be modified in various ways without changing the gist. For example, in the above embodiment, the case where the J-clamp circuit according to the present invention is applied to an X-ray diagnostic apparatus is explained.
The application is not particularly limited, and can be applied to any device that uses an A/D converter.

[Effects of the Invention] According to the present invention, digital conversion can be performed with extremely high stability and a high dynamic range.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing details of the digital processor in FIG. 1, and FIG. 3 is an embodiment of the present invention! FIG. 4 is a diagram showing a conventional clamp level setting circuit, and FIG. 5 is a diagram for explaining the clamp operation. 2...△/D converter, 10... X-ray television camera 1
1...Addition circuit, 1...Clamp pulse generation circuit CC...Comparison control means

Claims (1)

[Claims] An analog/digital converter that digitally converts an analog video signal obtained from a television camera, and a comparison control means that inputs the output of this analog/digital converter and controls the error to a minimum by comparing it with a predetermined clamp level. a clamp level determining means connected between the television camera and the analog/digital converter and outputting a predetermined clamp level according to the output of the comparison control means; and a clamp level determining means for superimposing the comparison control means on the video signal. and a clamp operation control means that operates at a predetermined timing according to the horizontal synchronization signal that is generated.
Clamp circuit in analog/digital converter.