JPS62164333A - Data transmitting circuit - Google Patents

Abstract

PURPOSE:To transmit data without fail even when a receiving side device is connected to an optional connector by providing a circuit to output a logical signal different according to the fact whether or not the receiving side device is connected to the connector, executing the gate control by the circuit output and controlling the transmission of the data. CONSTITUTION:When a receiving side device A1 is mounted, a grounding terminal AS1 comes to be a zero electric potential, the output data of a transmitting side device A0 are interrupted and the output data of the receiving side device A1 are outputted from an output terminal CO1 by the route of G3 G4. When the receiving side device A1 is not mounted to a connector S1, the grounding terminal AS1 is not grounded, and therefore, the input of an inverter G1 comes to be the electric potential of Vcc, namely, an '1' level. Consequently, the output comes to be '0' and an AND gate G3 is closed. Instead, the '1' level enters an AND gate G2 and the gate is opened. Namely, the signal data from the front stage are outputted from the output terminal CO1 at the route of G2 G4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transmission circuit that serially transmits signals from a transmitting device to a plurality of receiving devices.

BACKGROUND OF THE INVENTION There are systems that serially transmit digital data signals from one device to a plurality of other devices. FIG. 2 is a diagram showing an example of a conventional configuration of such a data transmission system. In the figure, A0 is a transmitting side device, and A1 to A1 are receiving side devices. Co is the synchronization signal output terminal of the sending device Ao,
Ct to Cn are each receiving steel f? At the synchronization signal input terminal of tAt"An, the synchronization signal clock S output from the synchronization signal output terminal Co of the sending device Ao is connected to the clock signal line C.
/1-C/n to the synchronization signal input terminals C1 to Cn of each receiving side device A1=An.

Oo is the data output terminal of the sending device Ao, 01 to O
n→ is a data output terminal of the receiving steel fittings A r to An→, and 11 to 1n are data input terminals of the receiving side device Δt −A IH. The data output Qo of the sending device Ao comes out from the output terminal Oo and enters the data input terminal 11 of the first sending device As via the data signal line /l.
First receiving side WA position Δ! The data output Q1 is outputted from the data output terminal OI and inputted to the data input terminal 12' of the second receiving side device A2 via the data signal line /2. Thereafter, data is similarly transmitted between adjacent receiving devices.

In the conventional system connected in this way, bit serial data is transmitted in synchronization with the synchronous clock S. In this case, the input and output parts of the receiving side devices A1 to An are the same and are configured as shown in FIG.

In the figure, SR is a shift register, C1 is a clock signal input, Si is an input of serial data SD, So is a serial data output, and Pa is a parallel data output into the device, which is output as data Do.

In the data transmission circuit configured in this way, the transmission input Δ
The side neck Ao outputs a serial signal from the data output terminal Oo in synchronization with the synchronous clock S output from the Domei signal output terminal Go. In this way, the data is sent from the device Ao to the receiving device An, An-+.

...Shift register S in each device in the order of A2 and A+
When data is sent to R, all receiving devices A! ~A
The data to be given is set in the shift register SR between n.

If the connection method shown in Figure 2 is realized on the motherboard system. The result will be as shown in FIG. In the figure, M is a motherboard, and So to 3n are connectors attached to the motherboard M. Of these connections, So is connected to the sending device Δ0, and 81 to Sn are connected to the corresponding receiving devices Δ1 to Δn, respectively.

I11~l! n is the data signal line between the same devices as shown in FIG. 2, CI! + to ClIn are clock signal lines.

The connectors 5o to 8n may be attached to the motherboard M by screwing them from both ends, or by soldering connector pins onto the motherboard M. In the former case, the signal lines IIl-lin,
The connections between C/+ and czn are wire connections, and in the latter case, pattern wiring. Pattern wiring is generally more reliable. These connectors SO to Sn are usually female type with a slit (dashed line in the figure) in the center, whereas the end of the connector on the device side is a male type as shown in Figure 5. The male and female are connected by mating.

(Problems to be Solved by the Invention) In a motherboard system as shown in FIG. 4, a problem occurs when the number of receiving devices to be connected is small relative to the number of connectors of the receiving devices. There is no problem if the receiving side devices are mounted sequentially from connector S1, but if there is an unmounted connector between the receiving side devices, the signal will not be transmitted to the receiving side devices connected to the connectors after the connector. Put it away.

The present invention has been made in view of these points, and
The purpose is to realize a data transmission circuit that can reliably transmit data even if the receiving device is connected to any connector in serial data transmission between the transmitting and receiving devices mounted on the motherboard.

(Means for Solving the Problems) The present invention that solves the above-mentioned problems has the following advantages: ! When connecting two or more receiving devices on one motherboard via connectors, each connector on the receiving device has a different logic level when the device is connected and when it is not connected. The present invention is characterized in that a circuit is provided for outputting , and the output of this circuit is used as a signal to control data transmission.

(Function) The present invention provides a circuit that outputs different logical beliefs depending on whether the receiving side device is connected to the connector, and performs gate control based on the output of this circuit to control data transmission.

(Embodiment) FIG. 1 is a configuration block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 4 are not shown with the same reference numerals. In the figure, C1 to co-1 are gate control circuits provided for each corresponding connector. These gate control circuits c1 to Cn-1 can be realized by printed wiring on the motherboard M and by hanging the components. Note that the synchronization clock signal is not directly related and is therefore omitted. Since all the gate control circuits have the same configuration, the gate control circuit c1 of the connector S1 will be explained here.

In the figure, I+ is an input terminal into which the bit serial data Qo output from the transmitting device Ao is input, and AS+
is a ground terminal connected to a common (ground), and O+ is an output terminal that outputs data from the receiving device A1.

There is also a clock input terminal for receiving a clock, but it is not shown here. G1 is an inverter whose input is connected to the ground potential via a ground terminal A S l. Further, the potential of the power supply voltage cc is also connected to the input of the inverter G1 via a resistor R+.

G2 receives the bit serial data Qo of the transmitting device Ao at the C1al terminal at one input, and receives the same signal as the input signal of the inverter G1 at the other input, and G3 has the inverter G+ at one input. output,
The output data from the receiving device Δ1 is input to the other input Cl1
The AND gate G4 which receives via the l+ terminal is an OR gate which receives both outputs of the AND gates G2 and G3.

Serial data Q1 to be applied to the next connector S2 is output from the OR gate G4 via the CO1 terminal.

The operation of the circuit configured in this manner is as follows.

First, a case will be described in which the receiving 1lllI device A1 is installed. In this case, since the O potential from the ground terminal A S 1 is input to the inverter G1, its output becomes the "'1" level and opens the AND gate G3.

As a result, the output data from the receiving device A1 passes through the AND gate G3 and enters the OR gate G4. At this time,
Since the AND gate G2 contains the ground potential (“0′ level), the AND gate G2 is closed and the output data of the transmitting device Ao is blocked. Therefore, in this case, the output data of the receiving device A1 is →Output terminal C at G4 route
It is output from Or.

Next, a case will be described in which the receiving device A+ is not mounted on the connector S1. In this case, ground terminal A
Since S t is not grounded, the input of inverter Gs is V
The potential of cc becomes the "1" level. Therefore, its output becomes "0" and the AND gate G3 is closed.

Instead, “1” level is entered in AND gate G2,
The gate opens, and the signal from the previous stage (here, the sending device A
o's output data) passes through AND gate G2 and enters OR gate G4. Then, output data is output from OR gate G4. That is, in this case, the signal data from the previous stage is output from the output terminal C01 via the route G2→G4.

As is clear from the above description, according to the present invention, when the receiving device is connected to connector $1, the signal passes through the receiving device, and when the receiving device is not connected, the signal passes through the receiving device.
The signal from the previous stage passes through the gate circuit CI and is output as is to the next stage. Such operation is exactly the same for the gate control circuits C2 to Cn→.

In the embodiment of (above) E, an example is taken in which the devices are connected in series using a synchronous bit serial signal. However, the present invention is not limited to this, and the present invention is not limited to this. may also be used.

(Effects of the Invention) As explained above, according to the present invention, a circuit is provided that outputs different logic signals depending on whether the receiving side device is connected to the connector, and the gate control is performed by the output of this circuit. By configuring the receiver to control the data transmission, data transmission can be reliably performed even if the receiving device is connected to any connector, which has an extremely large practical effect.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
The figure shows an example of the conventional configuration of a data transmission circuit, Figure 3 shows an example of the configuration of the receiving side device, Figure 4 shows how the connector is connected to the motherboard, and Figure 5 shows the configuration of the receiving side device. FIG. Ao...Sending device A1-80...Receiving device M...Motherboard 81-3n...Connector CI-C9-1...Gate control circuit R1...Resistor G+...Inverter G2
．． G3...AND GATE G4...OR GATE Patent applicant Yokogawa Hokushin Electric Co., Ltd.

Claims (1)

[Claims] When a sending device and multiple receiving devices are connected to a single motherboard via connectors, each connector on the receiving device has a difference when the device is connected and when it is not connected. What is claimed is: 1. A data transmission circuit comprising: a circuit for outputting a logical level; the output of the circuit is used as a gate signal to control data transmission;