JPS62162904A - Device for discriminating pattern defect - Google Patents

Abstract

PURPOSE:To quickly discriminate a pattern defect with a small scale circuit by making prescribed feeding of patterns to be inspected and comparing the same with the standard pattern within the corresponding permissible mis registration range thereby decreasing the overlapping inspections of the patterns to be inspected. CONSTITUTION:The local region patterns of nX1 picture elements are successive ly fed at l picture element intervals in the horizontal direction from the patterns to be inspected on a shift memory 13. These patterns and the corresponding local region pattern including the permissible misregistration range of the shift memory 12 for the standard pattern are compared in a comparing and discrimi nating device 22 by which the coincidence and discordance are discriminated. The results of the discrimination are successively inputted to the shift memory and are two-dimensionally arranged so that all of the regions of 1Xn picture elements are subjected to the discrimination of whether the coincidence signal or not by vertical scanning. The defect in the two-dimensional region F(x0, y0) of nXn picture elements is quickly discriminated with the small scale circuit by a pipeline system at the decreased overlapping inspections of the patterns to be inspected.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an apparatus for inspecting patterns on printed circuit boards, integrated circuits, etc., and particularly relates to an apparatus for inspecting patterns on printed boards, integrated circuits, etc. This invention relates to a pattern defect determination device that determines a defect if there is a difference.

[Background of the invention]

FIG. 12 shows the overall configuration of an example of a pattern inspection device, but in this case, the scale of the circuit for pattern comparison becomes unnecessarily large.

That is, the pattern to be inspected 2 placed on the XY table 1 is imaged by the pattern detector 4 through the objective lens 3 . The image signal is binarized by a binarization circuit 5 and becomes a pattern signal to be inspected 10. The pattern signal to be inspected 10 is synchronized with the standard pattern signal 9 read out from the standard pattern generator 6 in synchronization with the signal from the synchronization signal generator 8.

Defect inspection is performed by comparison in the defect determination device 7.

Incidentally, in the conventional pattern defect determination apparatus, the actual situation is that the pattern to be inspected and the standard pattern are superimposed and the inspection is performed in real time in synchronization with the input of each pattern signal.

FIG. 13 shows an outline of a conventional defect determination device. The contents of the signals corresponding to the inspected pattern signal 10 and the standard pattern signal 9 in FIG. 12 are respectively expanded into a two-dimensional array on the shift memory 13.
The local area in the pattern to be inspected has a predetermined number of pixels (n×n
) window F. , 0. In the same way, I! A pattern corresponding to the local area is also cut out from the quasi-pattern, and a pattern comparison is performed between the two patterns for each corresponding pixel.

However, in general, errors in manufacturing the pattern to be inspected,
The circuit configuration shown in the figure is adopted in order to tolerate positional deviation errors (±m pixels) in both the X and Y directions that occur due to pattern detection errors. That is, the size is (2m + 1)
The entire surface within the permissible positional deviation range of (2m + 1) pixels has a size of (n×n).

And the window G mrTat G11t m-1"・t is shifted by one pixel in each of the X and Y directions.
aoto? The pattern cut out from each of ".G-□1.-□01.-m and the pattern from the window FOyO are compared in the comparison/judgment unit group 14.

The judgment results of each comparison judgment device are logically summed at the OR gate 15 and obtained as a comparison judgment signal 11. If the patterns match in any of the comparison judgment devices, the comparison judgment signal is in a so-called high level state. This will be obtained as follows.

However, in each comparison/judgment device, as shown in FIG. 14, it is necessary to perform an exclusive OR operation in the exclusive OR gate group 16 for each (n×n) pixel in the cutout pattern. Further, in addition to requiring a large number of gates 17 for each comparison/judgment device, 02 exclusive OR gates are also required. This means that the standard pattern cutting window G mym+ Gm-
1pms...+ G-1et - This means that (2m+1)' comparison/judgment units are required for the entirety of m, and furthermore, n"X(2m+1)' exclusive OR gates are required. It will be done.

For example, the window size is 5 x 5 pixels (n = 5), and the positional deviation tolerance is ±55 pixels in the X and Y directions (m = 5).
Then, the number of exclusive OR gates alone is 3025 (= 5" x (2X 5 + 1)")
pcs are required. This means that as circuit patterns become finer and more dense, the pixel size at the time of pattern detection becomes smaller, and the tolerable positional deviation m tends to become relatively larger. It means expansion.

Incidentally, a known example related to this type of device is “Auto+amatic Inspection of Mask Defects”.
Mask Defects) (S P I E
Vol, 100 Sem1-conductor
Microlithography II 1977, P26-36) and ``Defect Detection Method for Circuit Patterns by Extracting and Comparing Local Features'' (IEICE Paper: 1977-ron 395. P-117).

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern defect determination device that eliminates the above-mentioned drawbacks of the prior art and can perform pattern defect detection at high speed and in real time with a simplified circuit configuration.

[Summary of the invention]

For this purpose, the present invention aims to reduce the circuit scale by reducing the number of repeated inspections of the pattern to be inspected. The pattern is sequentially cut out at a period of one pixel, and this cut out local area pattern and
This is designed to inspect the entire surface of the pattern to be inspected by comparing the corresponding standard patterns within the permissible positional deviation range and determining the presence or absence of defects from the comparison results.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 11.

First, the outline of the present invention will be explained with reference to Fig. 2.The present invention is designed to perform pattern defect determination processing in real time in synchronization with pattern detection using a pipeline method, and the outline thereof is as follows. be.

That is, from the pattern to be inspected on the shift memory 13, a local area pattern f of nX1 pixels is first obtained in the horizontal scanning direction.
o is successively cut out at two-pixel intervals and held.

A comparison is simultaneously made between this and each local area pattern detection cut out by the shift memory to the same size as the above area from within the positional deviation tolerance range of the standard pattern.
This is performed by the comparison and determination device 22.

As a result, a binary judgment value representing match/mismatch is obtained.

Thereafter, the determination values are sequentially input to a shift memory for local area pattern defect detection and are arranged two-dimensionally in correspondence with the inspection pattern. On the other hand, from this array data, an area of I×n pixels (1 in the X direction and n in the Y direction) is successively cut out in the vertical scanning direction, and it is determined whether or not all of the judgment values are match signals. .

By combining as described above, a comparison result of a two-dimensional local area F (Xot yo) of n×n pixels can be obtained.

To explain more specifically, nX1 from the pattern to be inspected
For the pixel cutout area fO, the corresponding position on the #A quasi-pattern has n for cutting out (2m+1) local areas within the Y-direction positional deviation tolerance ±m pixels.
Window of X1 pixels g ll+ g m-1t...
2g-1 are provided in parallel, and the window g++++...
- Comparisons are made simultaneously between the patterns from each of 9g-1 and the patterns from area f.

Each result is simultaneously recognized and processed in parallel by shift memories and cutout determination circuits provided corresponding to windows gm+gm-1, . . . 2g-1.

Furthermore, the pattern from the area fO is cut out as it is, and a window gram g n+-1v...9g-
1 The pattern from each is the positional deviation tolerance in the X direction (+m
The pattern is shifted by one pixel within the range of ~-m pixels) and compared with the pattern from the area fO, and these comparison results are also processed for recognition by the cutout judgment circuit via the shift memory as in the previous case. It has become so.

The recognition processing results corresponding to windows gmasg+a-1t...9g-1 are then logically summed and serially processed.
Through an in/parallel out shift register.

By performing the logical sum again, the final comparison judgment signal 23 (FIG. 2) is obtained.

Now, to explain the present invention in detail, FIG. 1 shows the basic configuration of an embodiment of a defect determination apparatus according to the present invention. Below, the cutout area n x n and positional deviation tolerance + m
~-m is n=5. The case where m=4 will be explained.

The standard pattern signal 9 (upper left in FIG. 1) and the test pattern signal 10 are each yl=1 from the top of the two-dimensional pattern:
Xi=lt2+”'+kyi=2;
X4=1g 2H..., etc., are shifted and input in series to the shift memory 12, 13 in the defect determination device in synchronization with the clock, pixel by pixel.

Here, the standard pattern signal 9 is input to the shift memory 12 after passing through the shift register 18 .

The shift register 18 is a serial-in/serial-out type having a length of 4 (=m) bits, and functions to delay the standard pattern signal 9 by 4 pixels relative to the pattern signal IO to be inspected. There is.

Furthermore, the shift memory 12 is configured with eight (=2 m) stages of shift registers each having a length corresponding to one scanning line width IH. Standard pattern signal 9, 2
It is designed to be arranged into dimensional image data.

Furthermore, the shift register group 19 sequentially cuts out 5 (=n) pixels in the horizontal direction and 9 (=2m+1) pixels in the vertical direction from this array pattern by pipeline processing in synchronization with the clock. It consists of bit-length serial-in/parallel-out shift registers 19-1 to 19-9.

On the other hand, the shift memory 13 has a configuration in which four (=m) stages of shift registers each having a length of one scanning line width IH are provided. The pattern signal to be inspected 10 corresponds to four pixels in the vertical direction with respect to the standard pattern signal from the shift register 18.
That is, the signal is delayed by four times and is serially output from the shift memory 13.

The shift register 20 is a 5 (=n) bit long serial-in/parallel-out register for receiving the output signal from the shift memory 13 and cutting out pixels.

Therefore, with the above circuit, for each 5×1 pixel pattern to be inspected cut out on the shift register 20, each of the 5
A standard pattern of x1 pixel is a pixel group shifted by 14 pixels in the horizontal direction and +4 to -4 pixels in the vertical direction.

These pattern cutting operations are shown in FIG. 5(a).

This will be specifically explained using the example shown in (b). This figure shows a case where there is no positional shift between corresponding pixels on the standard pattern (a) and the pattern to be inspected (b), and the same pattern exists.

f (Xop yo) of 5×1 pixels from the top of the pattern to be inspected
Consider the timing at which the signal is extracted to the shift register 20 (bottom left in FIG. 1). Shift register 19-1 to 19
-9, as shown in FIG. 5(a), g(xo-
4+ yo+4)+ g(xo-4t yo+3)t・
・・・+g(xo 4+yo 3) each 5×1
A pixel pattern is cut out.

In shift registers 20.19-1 to 19-9.

The pattern is sequentially X OexO+ in synchronization with the clock signal.
The image is cut out while moving one pixel at a time in the horizontal direction. After one horizontal scanning direction has been cut out, the image is further moved by +1 pixel in the vertical direction and returned to the beginning in the horizontal direction, and the horizontal movement and cutting are repeated again in the same manner. As a result, the entire surface of the test pattern and standard pattern is scanned.

By the way, register 21 (Fig. 1) is shift register 2.
The pattern cut out at 0 is sampled and input every 9 (=2m+1) clocks, and the cut out pattern is held until then.

This holding pattern and shift registers 19-1 to 19
-9 The patterns cut out for each are compared to the judgment circuit 22.
-1 to 22-9 comparison circuit 22-1-1.22-
2-1..., 22-9-1 are compared simultaneously.

Now, considering the extraction patterns in the register 20 and the shift register 19-1, the extraction pattern f (Xop yo) in the register 20 is constant for 9 clocks, but the extraction pattern in the shift register 19-1 is constant. is g(xo 4+ yo+4)t g(x.

3+yo+4) r...v g (Xo+ yO+ 4
) *...

It changes every clock in the order of g (xo'' 4p yo + 4).

Therefore, during the nine clocks, the comparison circuit 2 determines whether a position shifted by +4 pixels in the vertical direction matches each pattern in the range shifted by 14 to +4 pixels in the horizontal direction.
It can be obtained sequentially from 2-1-1.

Similarly, the shift registers 19-2 to 19-9 cut out each pattern in the range shifted by -4 to +4 pixels in the horizontal direction at each position shifted by +3 pixels to +4 pixels in the vertical direction, and the comparison circuit 22-2-1,・
. . , 22-9-1, the match determination results are sequentially obtained.

FIGS. 6(a) and 6(b) are for explaining the above operation.
This figure shows the state after 5 clocks have elapsed after the pattern yo) was held. The shift registers 19-1 to 19-9 each have g(Xoy yo+4Lg
(xo+yo+3)+...+g(xo+yo
4) is cut out, and the state of the circuit at this time is shown in FIG.

Register 20. Shift register 19-1 to 19-9
are f Cxoe yo) + g(Xot
yo +4)*g(Xot Vo”3)e...r
Each pattern of gcxoe yo 4) is cut out and sent to the comparison circuit 22-1-1.

. . , 22-9-1 outputs the match determination results as shown in the figure.

In the examples shown in FIGS. 6(a) and 6(b), it is assumed that there is no relative positional deviation between the standard pattern and the pattern to be inspected. Therefore, only the comparator circuit 22-5-1 (FIG. 7) outputs the match determination signal "1", and the others output the mismatch signal rOJ. Note that the comparison circuits 22-1-1, . . . , 22-9
-1 have the same configuration.

Incidentally, the comparator circuit 22-1-1, as shown in FIG.
The configuration is such that an exclusive OR is performed for each pixel, and a match determination result is obtained by performing a logical product using a NOR gate.

The output results of the comparator circuits 22-1-1 and the like are sequentially input to shift memories 22-1-2 (FIG. 1) and the like provided correspondingly.

The shift memories 22-1-2, . . . , 22-9-2 have the same circuit configuration, and are composed of five stages of shift registers each having a width of one scanning line and a length of IH, as shown in FIG. After this match determination signal is expanded two-dimensionally, the AND gate 22 of the 5-bit determination results in the vertical direction from the expanded data is
1-3 to 22-9-3 and output in synchronization with the clock (FIG. 1).

This output result becomes a match determination signal for a 5×5 (n×n pixel) bit cutout pattern for each cutout position on the standard pattern.

The operation of this circuit is shown in FIGS. 8 and 9 with respect to the specific example shown in FIGS. 5(a) and 5(b).

FIG. 8 shows that the match determination signal (FIG. 7) is the shift memory 22.
-Shift memory 22- after pattern scanning has progressed for 4 scanning line (4H) periods after being input to 5-2.
This shows the internal state of 5-2. "1" in the fifth stage shift register indicates a match determination signal shifted by 4H and output. That is, FIG. 5(a)
, f(Xot yo) and g(xot yo) in (b)
yo) is the match detection result.

Similarly, in the fourth row, it is f (x6. yO+ 1
) and the corresponding standard pattern g (Xot yo
+ 1), and the third row, the second
In the first stage, it is f(Xot yo +
2), f(Xot yo+3), f(Xot
g(xo+yo+2) corresponding to each of yo+4),
The result is a match between g(xo+yo+3) and f(Xot yo+4).

In addition, “0” represents each f(Xot yo) to f(Xot
yo+4) indicates that it has been determined that there is no corresponding pattern at each position of -1 to -4 pixels in the X direction at the same -y coordinate.

Now, FIG. 9 shows the state of the shift memory 22-5-2 after (LH-1) clocks from the state shown in FIG. And f(xoyyo) to f(Xoyyo+4) corresponding to the 5×5 cutout pattern of the pattern to be inspected
(Hereinafter, defined as F(Xot yo)) exists in the corresponding position of the standard pattern as shown in the AND gate 22.
-5-3 The output value of "0" output during the 4 clock periods before 6 Figure 9 and the 4 clock periods after this is standard for the above F(Xoy yo) pattern. This indicates that there is no corresponding pattern on the same y-coordinate on the pattern, but at positions where the X-coordinate is −4 to −1 pixels and shifted by +1 to +4 pixels.

The operation of the comparison/judgment circuit 22-5 has been explained above.
Similarly, at −9, the y coordinate is −4 to −1° +1 to +
At each position shifted by 4 pixels, the match determination result of the pattern of F(Xo+yo) in the allowable X-direction positional shift range of -4 to +4 pixels is sequentially outputted in synchronization with the clock.

Here, the explanation will be given again by returning to FIG.

The OR gate 22-10 is a comparison judgment circuit 22-1 or 2
It calculates the logical sum of each output value of 2-9, and if there is a corresponding pattern at each position shifted from 14 pixels to +4 pixels as the tolerance range for positional shift in the X direction, "1" is set, and when there is no, "0" is set. 14 pixels to +4 as the tolerance range for positional deviation in the X direction.
This determination result at each pixel position is synchronized with the clock, output over nine clock periods, and input into the shift register 22-11.

When the determination result of this 9 clock period is input to the shift register 22-11, the output result is determined in the X and Y directions.
The above F(Xo+yo) within the range of 4 to +4 pixels
6, that is, the presence or absence of the corresponding pattern in Figure 5 (a
), As is clear from the operating state shown in FIG. 1O corresponding to the specific example shown in (b), the shift register 22-11
As a result of "1" being input from the OR gate 22-1o, the pattern matching judgment value "1" is input to the OR gate 22-12.
This is something that can be obtained more easily.

The above-mentioned judgment is performed sequentially for each pattern to be inspected that is sampled and input to the register 2I shown in FIG. While determining this, the entire surface of the pattern to be inspected is inspected.

By the way, in the pattern defect determination described above, F(Xot
yo) sampling interval a is set to a positional deviation tolerance of 2m.
It cannot be set smaller than +1. For this reason, F(xot y
If the window width n in o) is n (2m +1), there will be an area that cannot be inspected.

To resolve this kind of problem, open Window F (
It is necessary to set the sampling interval 0 of xo+yo) to Q*2m+1, and to achieve this purpose, a circuit configuration as shown in FIG. 11 may be used.

Figure 11: Configuration example when the size of the extraction window of LtF(xot yo) is 5 x 5 (that is, n = 5), and the positional deviation tolerance m is ±5 pixels (comparison judgment range 2m + 1 = 11 pixels) , and the sampling interval of F(Xo+yo)=4 pixels is realized.

In this case, shift register 18' and shift memory 1
Months 2' and 13' are each 5 bits long, 10 stages, 5
It has a stage configuration, but the main difference is that the shift register group 1
9', shift register 20' and register 21' are 1
It is said to be 3 bits long. These 13 bits are divided into three 5-bit units with some bits overlapping as shown in the diagram (19', Fig. 11), and are simultaneously processed in parallel by comparison/judgment devices 16A-16c corresponding to the divisions. Comparison and judgment processing is performed.

Although the present invention is as described above, the shift register groups 19 (FIG. 1) and 19' (FIG. 11) and the shift registers 20 and 20' are not necessarily required in theory. However, in the actual IC and element, the shift
- January 2.12', 13.13' The individual shift registers configuring 19.12' and 13.13' can take a parallel output format due to the limit on the number of input/output pins, so a parallel output shift register group 19. 19' and shift registers 20 and 20' are provided.

Up until now, a large number of exclusive OR gate ICs have been required, but with the present invention, the number has been significantly reduced.
The number of interconnects between ICs will also be significantly reduced.

〔Effect of the invention〕

As described above, the present invention has the advantage that pattern defects can be detected at high speed and in real time by reducing the circuit scale by comparing the pattern to be inspected with a standard pattern.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of an embodiment of the main part of the pattern defect determination apparatus according to the present invention, FIG. 2 is a diagram for explaining the outline of the main part of FIG. 1, and FIG. FIG. 4 is a diagram showing a specific configuration for comparing the inspection cutout pattern and the standard cutout pattern, FIG. 4 is a diagram showing the configuration of a shift register for arranging comparison results two-dimensionally, and FIG.
6(a) and 6(b) are diagrams for explaining the pattern cutting operation, in which (a) corresponds to the standard pattern and (b) corresponds to the pattern to be inspected, respectively.
b) is a diagram for explaining the operation after 5 clocks have passed in Figures 5 (a) and (b), respectively, and Figure 7 is a diagram showing the main part of Figure 1 after 5 clocks have passed from the state in Figure 5. FIG. 8 is a diagram showing the internal state of the shift memory after four scanning line periods have elapsed since the coincidence judgment signal in FIG. 7 was output, and FIG. From the state shown (LH
-1) A diagram showing the internal state of the shift memory after the clock has elapsed; Figure 10 is a diagram for explaining the connection relationship between the OR gate and the shift register; Figure 11 is another embodiment of the main part of Figure 1. FIG. 12 is an overall configuration diagram of an example of a conventional pattern inspection device, FIG. 13 is a schematic configuration diagram of the main parts of FIG. 12, and FIG. 14 is a comparison of the cutout pattern to be inspected and the standard cutout pattern. FIG. 2 is a diagram showing a specific circuit configuration for doing so. 12, 12', 13.13'...Shift memory (for pattern two-dimensional array), tg, ts'...Shift register (for delay), 19.19'...Shift register group (standard pattern cutting out) ), 20.20'・
・・Shift register (for cutting out the pattern to be inspected),
21.21'...Register (for holding cutout pattern to be inspected), 22.22A to 22G...Comparison and judgment device, 22-1 to 22-9...Comparison and judgment circuit, 22-1-
1.22-2-1. ..., 22-9-1... Comparison circuit (for cutout pattern comparison), 22-1-2.2
2-2-2. ..., 22-9-2... Shift memory (for comparison result two-dimensional array), 22-1-3.22-2-
3. ..., 22-9-3...AND gate (for comparison result extraction judgment), 22-10.22-12...
OR gate, 22-11...shift register.

Claims (1)

[Claims] 1. The imaged video signal of the pattern to be inspected is converted into a binary value, and a relative positional deviation within a certain level is allowed as the pattern signal to be inspected from a standard pattern signal generated in synchronization with the pattern signal. This is a pattern defect determination device designed to compare patterns in a state in which a standard pattern signal is delayed by m (m: positive integer) pixels and a shift register with a capacity of one horizontal scanning line width is used. 2
While inputting a shift into shift memories connected in m stages in cascade, the delayed standard signal and each shift register output are each cut out to a parallel output type shift register having a capacity of n (n: positive integer) pixels or more. ,
The pattern signal to be inspected is shifted into a shift memory in which m stages of shift registers with a capacity of one horizontal scanning line width are connected in cascade, and the output of the final stage shift register is cut out to a parallel output type shift register with a capacity of n pixels or more. A register is made to hold every l (l; positive integer) pixel clock period, and corresponding n pixel divisions are formed between the parallel output of the register and each of the parallel outputs of the 2m+1 shift registers related to standard pattern cutting. The pattern comparison results for each n pixel section are shifted into a shift memory which is provided corresponding to 2m+1 shift registers and has n stages of shift registers each having a capacity of one horizontal scanning line width connected in cascade. , the outputs of each of the shift registers are ANDed, the AND results from each of the 2m+1 shift memories are ORed, and the parallel outputs are ORed and shifted into a shift register with a 2m+1 pixel capacity. ± horizontally and vertically by
A pattern defect determination device characterized by a configuration in which a pattern to be inspected having a size of n×n pixels is compared with a standard pattern while allowing a positional shift of m pixels.