JPS62159570A - Image processor - Google Patents

Abstract

PURPOSE:To detect an optional designated area by detecting an area of a set density range and the area surrounded by this area as the second area. CONSTITUTION:A density decision circuit 31 detects reading data (b) of half tone. Namely, the reading data (b) from a video processing circuit 20 is com pared with two threshold levels bT1 and bT2 (bT1>bT2) and the reading data (b) of the density of bT2<=b<bT1 is detected. Herein, specially, bT1 is the same level as the threshold level for a simple binarization. Thereby, a thin mark, what is called, of the range which is not decided to be a black in the simple binarization is detected. In bT2, the data is set to a suitable level so as to gener ate no malfunction due to a stain of a base of an original or the irregularity in the density or the like. When the reading data (b) of the half tone is detected, a signal (e) is set to '1' (H level). In an area detecting circuit 32, an area of a part of the half tone is detected by the signal (e).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing apparatus that specifies an arbitrary area on a document and extracts or erases an image of the area.

■Conventional technology For example, there are copying machines that extract only the image of a desired area without cutting and pasting the original, or create a copy with only the image of that area erased, and facsimile machines that transfer only the desired image. Image processing equipment is required.

The most important point in this type of device is the detection of a designated area.

In conventional image processing devices of this type, areas are specified using coordinates using a numeric keypad provided on the operation board, or a scanned original image is displayed on a CRT display device, and a cursor or light pen is used while looking at the image. , specifying an area using a mouse or the like. According to the former method, it is troublesome to read and input the coordinates of the specified area of the document. In fact, the area that can be specified is limited to simple shapes such as rectangles. Further, according to the latter method, the device becomes large and complicated and the cost increases, and real-time processing is not possible, so it is not suitable for copying devices, facsimile machines, etc. used in ordinary offices.

As a solution to this problem, Japanese Patent Publication No. 33333/1983 discloses a device for detecting an area based on an L-shaped display of a predetermined color written on a document. According to this, an area can be designated by simply writing a mark on the document. However, since the L-shaped display is made of two adjacent sides of a rectangle, the specified area is inevitably limited to a rectangle, and
There are disadvantages such as the need for color discrimination means to detect the L-shaped mark of a predetermined color.

(1) Purpose of the Invention The object of the present invention is to provide an image processing device that performs real-time processing and is capable of detecting any designated area.

■Structure of the Invention In order to achieve the above object, the present invention provides a reading means for dividing a document image into minute areas, reading the image density of the area, and outputting density data corresponding to the density; Comparison means for determining whether or not the area is included in the set concentration range; First area detection means for detecting, as a first area, an area in which minute areas corresponding to density data included in the set range are continuous; a second region detecting means for detecting a second region including the region and surrounded by the first region; a first image processing mode in correspondence with the second region according to an operator's instruction; 1 image processing mode setting means for respectively setting a second image processing mode different from the first image processing mode in association with the area; and processing according to the image processing mode set by the image processing mode setting means. The image processing apparatus is configured to include: an image processing means for applying the following to the density data and outputting the processed data.

According to this, since the area of the set density range and the area surrounded by the area are detected as the second area, it is possible to detect any designated area.

For example, if you use a color felt-tip pen or the like with a density within the set density range to surround an arbitrary area on a K+ document with a mark, that area will be detected as a second area, making the operator's operations less complicated. Area specification and area detection can be performed without changing the area.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 3 shows a block diagram of the configuration of an image processing apparatus that is an embodiment of the present invention. 10 is a scanner, and as shown in FIG.
The image is formed on the CCD line sensor 3 via Read from left to right at a density of 16 pixels/mm (main scan). The read signal a becomes an analog signal having an amplitude corresponding to the density of each pixel.

20 is a video processing circuit which converts the read signal a into an A/D
This is a circuit that generates 6-bit (64 Pa tone) read data b (the higher the value, the higher the density) by performing conversion (analog-to-digital conversion), background removal processing, shading correction processing, MTF correction processing, etc. be.

30 binarizes the read data and sets the black pixel to "1: H level"'self1iIj; a to "OWL level" (
This is a data controller that generates write data d by extracting (trimming) specified areas, erasing (masking), etc. from the binary image data (binary image data).

40 modulates the laser beam with AO according to the write data d (l: recording, 0: non-recording) and prints it on the recording paper 1
- It is a laser printer that

Above image processing′! In A10, there is a control device for controlling each of these components, and a scanner 10. Since the video processing circuit 20 and the laser printer 40 are well-known technologies and are not directly related to the features of the present invention, detailed explanations and illustrations thereof will be omitted.

FIG. 1 is a block diagram showing the configuration of the data controller 30 shown in FIG. 3. As shown in FIG. In this figure, within each block, the number of the drawing showing the details of that block is indicated in parentheses.

Simply put, the data controller 30 detects a mark in a predetermined density range written on the original 1 or an area surrounded by the mark, and performs 1-rimming or masking on the original image based on this. . In this embodiment, a mark made with a color felt pen (hereinafter referred to as a color mark) is assumed as a mark in a predetermined density range. This is because the Color Fell 1-pen is already available in various densities, which makes it easy to mark a predetermined density range and is advantageous in practice.

The density determination circuit 3■ detects halftone read data b. That is, read data b from the video processing circuit 20
and two threshold level work 1 and b work 2 (
In contrast, bTl>bT, ), bTl, ≦b < bT
Detect reading data b of concentration I. In particular, b-1 is set to the same level as the threshold level for simple binarization. As a result, so-called faint marks are detected in a range that would not be determined as black by simple binarization. Furthermore, bT2 is set at an appropriate level to prevent malfunctions due to dirt on the background of the document, uneven density, etc.

When halftone read data b is detected, signal e is set to “1”.
() I level).

The area detection circuit 32 detects the area of the halftone portion based on the signal e.

For example, even if a halftone is detected in a minute area of one to several pixels due to background dirt or the like and a signal elJ<< is generated, in this case it is not detected as a halftone area.

That is, in the case of a halftone over a certain area or more, a second fixed area including that area is detected as a halftone area. Furthermore, when marking the black print with Color Fell 1 to pen, the black print part is still black and has a high density. If the halftone area is divided by black in this way, the halftone area is expanded to include part of the black part for detection.

When a halftone area is detected, the signal f is set to "1" (II level).

The flag control circuit 33 is a circuit that controls the setting/resetting of the flag memory 34 at the primary stage.

In other words, by the signal f that detected the halftone area.

A flag is set not only for that area but also for an area including the inside of the closed loop surrounded by the halftone area, and control is performed such as resetting the flag for areas outside the area.

Hereinafter, the halftone area and the area surrounded by the halftone area will be referred to as a mark specification area.

The flag memory 34 is a one-line memory in the main scanning direction, and a flag indicating a mark designated area is set or reset. Therefore, it is updated every line (sub-scanning). The output signal of the flag memory 34 is a signal corresponding to the mark designated area.

FIG. 4 is a conceptual diagram showing the configuration and operation of the flag memory 34 in relation to a document.

The size of the document is not limited to the size shown in the figure, but in this case, one main scanning line is 50
00 pixels (density of 36 pixels/IIITo).

In this, XO+Xl+ ...X4999 is
Each direction! Indicates the address (main scanning address) of
yOrV1+V2+ . . . indicates the address of each line in the y direction (sub-scanning address).

The flag memory 34 of this embodiment is as shown in FIG.
,1,2. ...1 line memory consisting of all 2500 bits 1 to 2499, and X to flag memory 1 bit 1
It corresponds to 2 pixels in each direction. This is to save memory capacity and peripheral circuit configuration, and does not necessarily have to be this configuration.

The contents of this flag memory 34 are updated every sub-scan.

Note that in this case, in order to save memory capacity in peripheral circuits, even lines (that is, yo) are used.

There is a slight difference between the processing of y2+y4...) and the processing of odd lines (ie, yt t :/3+y5...). For this reason, although the representations of the even and odd lines of the flag memory 34 in FIG. 4 are changed, the same processing may be performed.

1 rimming/masking circuit 35 includes flag memory 3
The binary image data is gated by the output signal of 4, and the first
Generate write data 8I.

On the other hand, the hollow processing circuit 36 is a circuit that generates hollow data e2 that converts a thick image as shown in FIG. 22a into a bordered image as shown in FIG. 22b, and is suitable for this type of circuit. Since there are various types known, the details will be omitted.

The hollow selection circuit 37 gates the hollow data e2 according to the output signal of the flag memory 34, and generates second write data e3.

The output selection circuit 38 selects the first write data e1 or the second write data e3 and outputs it as the write data d.The microprocessor (CPU) 39 selects the density setting circuit 31 based on the input from the operation board. The setting of the threshold level, the selection of trimming or masking of the trimming/masking circuit 35, the selection of data of the output selection circuit 38, etc. are instructed, but the signal lines are not shown.

Each block shown in FIG. 1 will be explained in more detail below.

FIG. 5 shows the configuration of the density determination circuit 31, and FIG. 6 is a timing chart showing an example of the operation of the density determination circuit 31.

CPI and C20 in FIG. 5 are comparators, and when A≧B at the input terminals A and B, the output terminal A
≧B output becomes logic "1: H level", and when A<H, the terminal output becomes "OWL level". GAP, G.A.
2 indicates a gate.

Input terminal A of each comparator CPI and C20
Read data b from the video processing circuit 20 is applied to. Further, the input terminal B of the comparator CPI is supplied with a threshold level b for simple binarization, and the input terminal B of the comparator CP2 is supplied with a threshold level bT2 for color mark discrimination.

In this example, bTl was 31. br2 is set to 10 (-example).

Comparator CPI output e. is a simple binary signal (that is, binary image data) of read data b, and II 1
'7 corresponds to the black pixel II Q II corresponds to the white pixel.

This comparator CPI output e. branches to gate G
It is applied to gate GA2 (AND gate) via AI (inverter). Therefore, the gate GA2 output e is "B" when the read data b has gradations 10 to 30 (that is, when it is a halftone pixel), and "O" when it is not (that is, when it is a binary image pixel). ” (hereinafter e is referred to as halftone detection data).

FIG. 6 is a ternary chart in which the horizontal axis is a main scanning address, and shows output signals QQ and e for an example of read data b. The vertical axis for read data b is from 0 to
It shows 63 gradations and is binary image data e. The vertical axis for each of the and halftone detection data e indicates the binary value of l10 (H/L level: the same applies hereinafter). As a result, when the read data b is equal to or higher than the one-dot chain line (gradation level 31), e. It's l...

It can be seen that when e is "O" and is between the one-dot chain line and the two-dot chain line c gradation 10), GQ is II Ogp, and when e is 1r1u and less than the two-dot chain line, it is rr Orr.

FIG. 7 shows the configuration of the area detection circuit. In this, SF is a shift register and GA is a gate.

LA indicates a latch, and RAM indicates a RAM (random access memory).

9 and 10 are timing charts showing the timing of each signal used in the following explanation. Referring to FIGS. 9 and 10, the clock SI is a clock signal whose period is equal to two main scanning pixels, and S,
= II 1 r' is the even numbered pixel shown in Figure 2, s
, = “o” corresponds to reading odd-numbered pixels. Therefore, the halftone detection data e changes in half a cycle of the clock S1. The clock S2 is a clock obtained by dividing the clock S1 by half. Signal 1 (underlined indicates inversion, and overlined terminals in the figure indicate L active, 2 and below are the same) is a signal that controls the output enable of each latch, and is a signal that controls the output enable of each latch.
, LA3 and LA5, the output terminals output Q ll , Q2 r .

The signal Σ rising is a write control signal to the RAM. The signal is a chip select signal. Signals A1-1□ are 12-bit RAM address signals, and correspond to one unit of bin 1 (two pixels are one unit) of the flag memory 34 shown in FIG.

In FIG. 10, Sy is a line synchronization signal and Tr indicates a period. The hatched portion of each filtered signal indicates that the signal is not generated.

FIG. 11 is a timing chart for explaining the detection operation of the mark designated area in the main scanning direction by the area detection circuit 32 shown in FIG. The following description will be made mainly with reference to FIGS. 7 and 11.

As an example, assume that the halftone detection data e is as shown in FIG. Note that the numbers in the timing chart indicate the main scanning address of the corresponding pixel (reading pixel).

The halftone detection data e here is the main scanning address -
3 (that is, address 2/197 of the previous line), due to background dirt, := l/ 1+'', and at main scanning addresses 1 to 10 and after 20, color marks are detected and e=
At rL 1 n and main scanning addresses 11 to 19, the color mark is divided by dot printing and the signal becomes =r″0″. Therefore, the binary image data e at main scanning addresses l1-19. is ``bi''.

The shift 1 register SFI takes in halftone detection data e every two pixels in response to the clock S1. therefore,
The output signals of SF1 output terminals QA to QO are from the past 8
Corresponds to pixels. As described above, this processing is performed by thinning out pixels to simplify the circuit.

After all, in SFI and Ga3, determination is made whether or not it is a halftone image over 4 clocks of Sl, that is, over 8 pixels, and when a halftone image over 8 pixels is detected, the GA3 output signal f1 becomes " It becomes o”.

SF2 and Ga4 are also Tarotsuku S! It operates at the cycle of

That is, in SF2 and Ga4.

With respect to the timing when fl="I", it is determined whether or not there are 8 clocks of Sl including that timing, that is, 166 pixel halftones.

Even if a color mark is broken in the middle and divided by white, or if a minute area within a color mark is white or black, this is ignored and the color mark is detected as if it were continuous. It's for a reason. When a signal f1 as shown in FIG. 11 is input to SF2, Ga4 outputs a signal f2 as shown in the same figure.

Ga2 and SF3 operate in synchronization with clock S2, and in these cases, the color mark is separated by a black line or the like due to printing.

The color mark in that area is compensated for. For example, in newspapers, etc., color marks may be separated by a dividing line, and this is to connect the color marks in the separated portions. However, the width of the separation of color marks by black varies, and no matter how large the width is,
If the above compensation is performed, there is a risk that the mark designated area to be detected will extend far beyond the intended area.

Therefore, in this embodiment, the black mark dividing the color mark is
The upper limit was set to 1.

That is, in the case of f 2 = LL l l, o ==
II I g, 1''' from the input terminal of SF3
is taken in, shifted by four clocks of S2, and an output signal f3 is taken out from the output terminal QO. The signal f3 is a signal for compensating for the division of the color mark by black, and in this embodiment, it compensates for the division up to approximately 4×S2=16 pixels. Furthermore, as mentioned above, the mark specified area on the boundary with black is detected as an area enlarged from the actual area by SF2 and Ga4, so if this area is included, the color mark area will be approximately 20 pixels. Compensate for the division by black (that is, do not compensate for the division beyond: the upper limit).

The OR gate GA6 output signal f4 has been subjected to expansion of the halftone area and compensation for division caused by black 1.

The data corresponding to the main scanning address -4 successively becomes a logic rr 1 u signal. This signal f4 is a signal indicating the halftone area in the main scanning direction.

The signal f in FIG. 11 is transmitted through three latches LA2 . Due to LA4 and LA6 delays. signal f
4 shifted by three clocks of Sl.

Next, the operation of detecting a halftone area in the sub-scanning direction by the area detection circuit 32 shown in FIG. 7 will be described.

In FIG. 7, the first shift register in the sub-scanning direction (that is, corresponding to the shift register SFI in the main scanning direction) is controlled by LAI and RAM1, and the second shift register in the j41 scanning direction is controlled by LA3 and RAM2. (corresponding to SF 2 k above) is transferred to the third shift register (corresponding to SF 2 k above) in the sub-scanning direction by LA5 and RAM3.
(corresponding to SF3 above). Also, gate GA7. GA8. GA9 and GAIO are respectively gates GA3.GAIO in the main scanning direction. GA4. Compatible with GA5 and GA6.

First, the operation of the first shift register using LAI and RAM1 will be explained with reference to FIGS. 12 and 13.

FIG. 12 is a timing chart showing the operation of each part when the address signal of the RAM is in the vicinity of A x 1 in the main scanning of an even numbered line, and FIG. Similarly, the RAM address signal is a timing chart showing the operation of each part in the vicinity of Ax1. In addition.

01, Q2, Q3 and Q4 in FIGS. 12 and 13 are output signals of LAI, and D2-4 are input signals of input terminals D2-D4 of LAI.

The latch timing of latch LAI is k (inversion of clock S1), that is, corresponds to the fall timing of clock S1. At this timing, the LAI input terminal
The above-mentioned signal ft (GA6 output) is taken in. The reading line signal f4 at this time is expressed as f4°. From this meaning, the signal f4 one line after this reference is f4', and the signal f4 two lines before is r4-z,4
The signal f4 before the line is expressed as f4-4. The output quantity of the output terminal Q1 of the 2nd line before is expressed as Qx-the output quantity of the output terminal Q1 of the 214th line before is expressed as Ql-4, etc.

As shown in Figure 12, a write control signal to RAM is generated when the line is even (see Figure 10), and the new outputs Q1 to Q3 of LAI are written to RAM 1 for the next shift. . Next, when this data is read from RAM1, it is applied to the input terminals D2 to D4 of latch LAI, so it is shifted by one bit.By repeating this, LAI and RAM A direction shift register is configured. In other words, when the output of output terminal Q1 is f4°, Q2 "Q 1-2= f 4-2+ Q3 = Q2 -" = Q1 -' = fa
-'+Q4''Q3-2 =Q2 -' =QI
-' = f4 -' +.

In this embodiment, the write control signal is generated only for even-numbered lines, and data is captured every other line.Similarly to the case where data e is captured every other pixel in the main scanning direction, This simplifies the circuit.

Referring to FIG. 13 (the next line in the timing chart shown in FIG. 12), on an odd line, no write control signal is generated and RAM 1 performs only a read operation. That is, for odd lines, the data read from RAM1 is shifted by 1 bit (1 bit in the sub-scanning direction) and latched by LAI.

In other words, when the output terminal Q1 is f41, Q2 "Q
+ −” = f 4−” rQ3 = Q2−” =
Q1-' = f4-'.

Qa ``Q3-2=Q2-' =Q+ -s =fa
' r. These outputs are input to GA7.

Referring again to FIG. 12, LAI is s, =: 1
Since the output is enabled when it is 10 rH, Q1~Q
4 is valid during the period of Σ, == 110 rr as shown in the figure, so the GA7 output signal f5 is also valid during this period, and conversely, during the period of S, = 111 u, as shown in the hatched part. This will be the invalid period. Valid like this/
In order to solve the problem of the invalid period and the problem of timing uncertainty due to the switching speed of LAI and GA7, the timing of f is shaped in LA2.

Shifting is performed by the same operation as described above in the second shift register consisting of LA3 and RAM2 and the third register consisting of L, A5 and RAM3.

Also, LA4 and LA6 perform timing shaping in the same way as LA2.

Incidentally, in the above-mentioned SF3, data was taken in every four pixels in synchronization with the clock S2.

Similarly, in the third shift register consisting of LA5 and RAM3, every 4 pixels in the sub-scanning direction (that is, every 4 lines)
Import data to. Therefore, the write control signal SWI and chip select signal of RAM3 include the first
As shown in FIG. 0, the signal is generated every four clocks of the line synchronization signal Sy, that is, the signal has a period of four lines.

To summarize, the area detection circuit 32 shown in FIG. 7 detects halftone areas in the main scanning direction and the sub-scanning direction, SFI and GA3 are in the main scanning direction, and LAI, RAMI and GA7 are in the sub-scanning direction. In the scanning direction, halftone images (noise) with small areas are excluded and only halftone images covering a certain area or more are detected; SF2 and GA4 are in the main scanning direction, and LA3. Once a halftone area is detected in the sub-scanning direction, RAM2 and GA8 exclude non-halftone (noise) caused by minute white or black around it, and create an area that includes the detected halftone area and is somewhat larger than this area. Detected as a halftone area; GA5 and SF3 are GA5 and SF3 in the main scanning direction.
9. LA5 and RAM3 divide the division (noise) of the halftone area by black into a certain division rjJ in the sub-scanning direction.
Compensation is performed so that it can be regarded as an intermediate tone. As a result of the above, the signal f becomes a halftone area signal that compensates for image noise on the original.

FIG. 8 shows the flag control circuit 33 and flag memory 34.
The configuration is shown below.

The halftone area signal f generated by the area detection circuit 32 is input to the flag control circuit 33, and the GA16. The data is taken into the flag memory (RAM4) 34 via the L signal 10. As mentioned above, the RAM 4 is a one-line memory in which one unit is two pixels.

A write address is designated by address signals A1-12.

When the contents of RAM4 are read, QA15. GA16
．． It is latched into LAII via LAIO and output as a signal indicating the mark designated area.

GAI2. Set/reset 2F consisting of GA13
/F (flip-flop) has a function of detecting the period from the start of scanning until the first halftone area is detected in the main scanning direction. That is, the F/F output signal 112 is reset by the line synchronization signal (inverted) and reset by the halftone area signal f. Here, strictly speaking, due to GΔ11, NAN with fζ
Although it is reset by hl by D, this is a matter of circuit technique, and it can be considered that it is functionally set by f.

LA7°LA8. which receives address signals A, ~12 as inputs.
The circuit consisting of C20 detects the period from the rearmost halftone area to the end of scanning in the main scanning direction. That is, the address of each halftone area is launched into LA7 by the signal h1. Therefore, at the end of scanning one line, the last address in the halftone area in that line is latched in LA7. Since this rearmost address is also cleared by LL in preparation for scanning the next line, the rearmost address is latched into LA8 by the line synchronization signal Sy.

That is, the rearmost address of a certain line is used to detect the period from the rearmost address to the end of scanning in the next line. In other words, the period from the end of the current halftone area to the end of scanning is detected using the data of the -th previous line. This is because it is a circuitous process to determine which halftone area is the last halftone area unless the line is scanned to the end. However, as described above, even if there is an error of one line, the error of one line is sufficiently small and can be ignored compared to the designation of the area by the mark, the detection accuracy thereof, and the purpose of the area designation.

C20 compares inputs A and B, and when A>B, output terminal A>B=“O” (L level: however, the output terminal is shown overlined in FIG. 8).

In other words, the signal h3 from the GA14 is a signal indicating the period from the leading edge to the first halftone area and from the last halftone area to the rear end of a certain line, and during these periods, 113=="Q" become. Conversely, outside this period, h3="bi'".

LA9 is a latch for timing shaping to compensate for signal delays caused by C20 and GA14.

The output signal h4 from GA15 and GA16 is.

[If the RAM4 output is ``1'' when = ``1・'' and during the period when h3 = ``l'', regardless of the value of f''
Sera 1~ is done in Bi'. The signal [14 is stored in the RAM 4 via the latch LAIO as a signal g indicating the flag of the current line. Further, in parallel with this, g is output as a mark designation area signal via LAII.

The operations of the flag control circuit 33 and the flag memory 34 shown in FIG. 8 will be explained by giving a specific example with reference to the timing chart shown in FIG. 15. In FIG. 15, main scanning line t based on Qo + Q+ is 1 line later, Q2 is 2 lines later than that, and Q2 is 2 lines later.
This is the main scanning line after the line. Also, although the signals h4g and h have different timing and waveforms, they can be considered the same, so they are denoted as h4 (g, h), and below, the signal h4g and h4 are considered to be the same.
That's what I will say.

Halftone area signal f is each main scanning line QO*Q1+Q2
Assume that the detection is performed as shown in the figure. In this, A1° + AI 1 + AI 2 is the address of the first halftone area corresponding to each line (the value of the RAM address signal: the same applies hereinafter), and A 2' HA 2
' I A 22 Address of the last halftone area corresponding to each line.

LA7 updates and latches the address of the halftone area for each line by the halftone area signal f (actually h+), and the output from the output terminal Q (LA7-Q) is as shown in the figure. LA8 uses the line synchronization signal sy to control the rearmost (7) 7dl/s (A2) of the halftone area for each line.
' + A2 + A2 '') Then, the output of the output terminal Q (LA8-Q) is delayed by one line as shown in the figure. Therefore.

As shown in the figure, the output terminals A>B of the comparator CP3 are set to 1 to 1 at the rising edge of the line synchronization signal, and at the timing corresponding to the last address of the halftone area for each line (actually, the address one line before). This is the signal to be reset.

Since the signal h3 is the logical sum of the A>B output and the F/F output, it is set at the timing corresponding to the address of the first halftone area of each line, as shown in FIG. The U-line Q is a signal that is reset at the timing corresponding to the address. It is assumed that the RAM 4 outputs the illustrated signal (the flag of the previous line Q-,) in response to this. First, the signal f becomes II l gg at the timing corresponding to the address A1°, so the signal h4 is set; at the same time, the signal h3 becomes 'blank', and the signal f becomes 11
Since the RAM4 output becomes "BI" before it becomes 0H, h4 is set continuously; the signal h3 is set to "BI" at the timing corresponding to the rearmost address A2-1 of the halftone area of the C-+ line. o”.

Assuming that address A2-1 is before the rearmost address A2° of the Qo-line halftone area, the signal f is
The signal h4 is reset at the timing of OII, that is, at the timing corresponding to address A2°. signal h
Since a (""g) is updated and stored in the RAM 4, the next line (Q+U line) is +1 rr in the RAM 4 at the timing corresponding to the address AI0.

At the timing corresponding to the address A2°, a signal that becomes Pa0'' is outputted.This process is repeated thereafter.

For the sake of simplicity, in Fig. 15, we have taken as an example a case where there are halftone areas (that is, places where f = "bi') at two distant locations in one line, but the signal h3 is It is set corresponding to the address of the first and last halftone area regardless of the number of tone areas. For example, one
If there is a halftone area only in one area, it is set corresponding to its first and last addresses (in this case, the first and last addresses may match).

In this embodiment, a write operation to the RAM 4 is performed during an even number line, and a read operation from the RAM 4 is performed during an odd number line. Therefore, for odd lines,
A new flag h4 is generated from the data f of the current odd line and the flag data written or set/reset on the previous even line. A new flag h4 is generated from the flag data on even-numbered lines up to. This allows R
Control signals WE and C3 of AM4 (indicated by overline in FIG. 8) are shared with RAM1 and RAM2,
The circuit is simplified. In other words, for a reading resolution of 16 lines/m, a detection error of about 1 line is allowed, for example.

A write operation may be performed for each line.

FIG. 16 shows O-shaped and linear color marks attached to a document, and FIG. 17 shows a mark designation area extracted based on the color marks in FIG. 16.

A more specific description will be given with reference to these drawings.

First, when focusing on the -Vo line (above the O-shaped color mark), there is no detection of the halftone area, so the signal f is I
It remains as I 011. For this reason, F/F(GA l
2 &GA 13) remains reset, the signal h2 and signal h3 are always rt On, and the mark designation area signal becomes O''.At this time, LA7 remains clear (that is, address 0) and LA8 latch Therefore, in the next line, immediately after the start of main scanning, A>B=
"O" and i, 1. h3 becomes “0”.

Assume that a halftone area is detected for the first time on the 'Il line. In this line, the halftone area is divided by the black line, but as mentioned above, in this example, the
As shown in Figure 4, when a halftone is detected over an area of 8 x 8 pixels, the area of 16 x 16 pixels including this is determined to be a halftone area (that is, f = "1"). ), this division has no effect. When focusing on the y1 line, since h3="0"' is always set as described above, the signal f becomes a flag for the current line, and is outputted as a mark designated area detection signal at the same time as being written into the RAM 4.

Furthermore (according to sub-scanning) the line of interest is y! If you move down sequentially, the new flag will be updated and stored in RAM4, so
For example, when focusing on the y2 line.

The halftone area is only on both sides, but after setting the flag according to the signal f, the area sandwiched between the halftone areas on both sides, that is, the section where h3=II 11#, is stored in RAM4.
Since a flag is set according to the output, an area surrounded by color marks can be detected as a mark designated area.

The y3 line is a line that passes through the breaking point, but since the halftone area is expanded as described above, it is not affected by this.

As in the y4 line, when the interval between the halftone areas on both sides becomes smaller, the signal h3 is generated correspondingly.
Even if the RAM 4 output is larger than this width, the mark designated area will be detected correctly.

At line y5, the line of interest moves away from the O-shaped color mark, and the signal f remains at sr O, . For this reason, F
/F (GA l 2 & GA 13) remains reset, so signal h2 and signal h3 are always LL O
J, and the mark designation area signal becomes "o" regardless of the RAM 4 output. The RAM 4 is reset by writing the flag at this time.

The y6 line is a line that passes through a linear filled color mark, and there are characters in the color mark, but as mentioned above, by expanding the halftone area, the mark specified area can be detected without being affected by this. I can do it.

As described above, according to one aspect of the present invention, it is possible to detect a halftone and a portion surrounded by halftones, and the shape thereof is not limited to a rectangle but can be various. Further, the number of portions surrounded by halftones in one document is not limited. Moreover, since the detection is performed in parallel with the original reading operation, there is no need to perform area detection in advance by, for example, pre-scanning. In other words, for example, it is possible to extract a designated area and simultaneously copy the image of that area. In addition, in this embodiment, a mark made by Color Fell 1-pen is targeted, but this mark has a specific density range and its color is irrelevant, and furthermore, a special sensor, light source, etc. are required for detection. does not require. This mark is set in the range that is determined to be white by simple binarization, so
No mark appears in the digitized data, and no mark appears on the copy printed based on the 2-layer conversion. Furthermore, since the mark is extended to detect the halftone area, even if the mark is divided by white or black, the area can be detected effectively.

Figure 18 shows an example of area specification.
, B, and C are examples of encircling with color marks, and E is an example of filling with color marks. As shown in the figure, various almost arbitrary shapes can be specified.

For example, when specifying an area by filling, you can specify the area you want to specify even if the characters, character pinch, and line pitch of the area you are trying to specify and its surroundings are inconsistent, and it is difficult to accurately enclose the area with a mark that is thicker than -. It is easy to fill in only the areas.

You can also fill it in with a light colored felt pen,
Black characters and the like that are originally printed there remain at a high density and are determined to be black both by the naked eye and by binarization processing, so areas can be specified without losing data in the filled-in areas. Note that when it is not possible to directly mark the document, it is sufficient to cover it with a transparent sheet, for example, and mark from above.

Figure 19 shows a part of the operation board, including trimming,
The part marked as masking is the key top. The image processing apparatus shown in FIG. 3 has a 1 to rimming mode in which the image in the mark designated area is extracted and copied, and a masking mode in which the image in the mark designated area is erased and copied. The keys shown in FIG. 19 are for specifying these modes, and have an alternate switch groove structure. That is, for example, when the 1 to rimming keys are operated in a state where neither the trimming mode nor the masking mode is set, the trimming mode is set.

If the 1 to rimming keys are operated while the trimming mode is set, the trimming mode will be canceled. Further, when the masking key is operated without setting either the trimming mode or the masking mode, the masking mode is set, and when the masking key is operated while the masking mode is set, the masking mode is canceled. If the masking key is operated while setting trimming mode, 1
- If the rimming mode is canceled and the masking mode is set, and the trimming key is operated while the masking mode is set, the masking mode is canceled and the trimming mode is set. In addition, while the trimming mode is set, the lamp inside the trimming key top lights up.
When masking mode is set, the lamp inside the masking key top lights up.

As shown in FIG. 20, the CPU 39 in FIG. 1 sets the signal 1 to rr 1 , . 1 to signal rr O11, 2 to signal LL
I Set to 11. In addition, if neither mode is set, both "1" and "2" are set for the signal.
o”.

FIG. 21 shows the trimming/masking circuit 35 shown in FIG. Details of the hollow selection circuit 37 and the output selection circuit 38 are shown.

1 to rimming/masking circuit 35 has a QA of 17°GA
I8. GA19. It is composed of GA20 and GA21. In trimming mode, the signal k I "" 1
``2='l Q IT for r signal, so GA2
From 0, the mark designation area signal is output as is. In masking mode, signal 1. , == II Q
Since the signal 2=“1”, the GA 20 outputs the inverted mark designation area signal)1. Also, when neither mode is set, signal kl="O" and signal 2="0", so GA20
From rr 1 r regardless of the mark specified area signal
r is output. QA20 output is given to GA21,
Since the binary image data Qo is applied to the other terminal of this gate, the GA20 output is "1" after all.
’, the binary image data becomes 0°, and the GA20 output becomes I
When I 017, the first write data e1, which is "o", is output. This can be summarized as shown in Table 1 below.

The hollow selection circuit 37 in Table 1 includes the GA22 and the selector SEI.
It is made up of. Binary image data (3o) is given to the input terminal A of the selector SEL, and hollow data e2 from the hollow processing circuit 36 is given to the input terminal B. When the selenium 1 terminal S is "o", the input is Terminal A is selected and output, and when select terminal S is rr 111, input terminal B1 is selected and output.

As mentioned above, the hollow processing circuit 36 is a circuit that generates data to output an image as shown in FIG. 22b from an image as shown in FIG. 22a. Only the part is extracted. Since various circuits of this type are known, their explanation will be omitted.

The operation board is equipped with a hollow selection key (not shown), and CPtJ39 sets the hollow mode in response to this key operation.
Set to L 111.

Mark designated area signal and signal 3 are both 11
+, 11, the GA22 output becomes I+ 111, so the selector SEI selects the hollow signal e2,
In other cases, the 0A22 output will be °°O'', so
SE1 selects the binary image signal (!o, that is, the second
The write data e3 is data for forming a hollow image only within the mark designated area. To summarize the above relationships,
The 6-output selection circuit 38 as shown in Table 2 below is GA2
3. It is composed of GA24 and GA25. When the hollow mode is not set, the signal is 3 = "O", so GA23 is turned on, GA24 is turned off, the harmful data d becomes equal to the first write data el, and the hollow mode is set. Then, the signal becomes 3==IIBI'', so GA23 is turned off and GA24 is turned on, and the write data d becomes equal to the second non-write data (!3).

Although not shown in the figure, B2 is connected to the B input of selector SEI.
′=lL (inverted data of binary image data: possible by connecting via an inverter),
It is possible to create an image with black and white reversed only within the mark designated area.

In the above embodiments, examples of trimming, masking, and hollowing have been shown, but it will be easily understood that various other types of edited images can be created using the mark designation area signal.

FIG. 23 shows the mark designation mode (the above-mentioned trimming mode) in the image processing equipment shown in FIG.

An example of specifying (masking mode, hollow mode, etc.) and linking other modes is shown below.

The background removal mode is a function that updates the white level to the background density when the target is a document with a background color such as a newspaper or graph paper, but in the mark specification mode of this embodiment, the color mark That is, since the designated area is detected by reading the halftone mark, the first important point is the setting of the white level. In other words, this prevents errors in the mark designation mode due to background color, background smudges, t-shields, etc., and improves reliability.

In addition, the effect of improving the performance can be obtained. The binarization determination level refers to the threshold level bTl in FIG. 51 and FIG. 6. Although not shown, the operation board is equipped with a density adjustment key for adjusting the density of the output image, and when this key is operated, the level of the threshold level bTl is updated and set. For example, to obtain a dark output image from a thin original, bTI is set to a small value, and conversely, to obtain a pale output image from a dark original, bTI is set to a large value.

However, in mark specification mode, halftones that are darker than the background of the original are detected, and in binarization, are judged to be white. The detected concentration range is wide, and there is more leeway regarding the felt-tip pen for specification and the method of entry. Therefore, in the mark designation mode, the binarization determination level, that is, the threshold level bTI, is set to a predetermined value regardless of the state of the density adjustment key.

The above is a description of an embodiment of the device of the present invention.

In addition, in the explanation in -H, for example, the address signal A
Generation circuits 1 to 12, generation circuits for various timing control signals, initial state settings for main and sub-scanning, etc., and control of main and sub-scanning widths in relation to document size.

Goo to image signal 1-condition, 2 when generating write data d
value image data e. Things that are known, self-evident, or easily possible with the prior art, such as the delay conditions of the blank data 82, etc., are not related to the gist of the present invention and may complicate the explanation and cause confusion. For the sake of clarity, the description and illustrations have been omitted by 10 times.

In addition, in the description of the embodiments, unless otherwise specified.

The H (high) level is set to logic "1", and the L (low) level is set to logic "0"'.

(D) Effects of the Invention As described above, according to the present invention, since the area of the set density range and the area surrounded by the area are detected as the second area, it is possible to detect hair in any specified area. For example, if you use a color felt-tip pen or the like with a density within the set density range to surround an arbitrary area on the document with a mark, that area will be detected as the second area.
Area designation and area detection can be performed without complicating operator operations.

Furthermore, as described in the example description, if an area that cannot be surrounded by the mark is filled in with the Color Fell 1-pen, that area will be detected as the second area, so area specification is not possible. It's very simple.

Furthermore, as described in detail in the description of the embodiment, since real-time processing is possible with a simple circuit, it can be installed in copying machines, facsimile machines, etc. used in ordinary offices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a partial configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a conceptual diagram showing the reading of K (document 1) by the CCD line sensor 3. FIG. 3 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention. 5 is a conceptual diagram showing a memory map of the flag memory 34 shown in FIG. 5. FIG. 5 is a block diagram showing the configuration of the density determination circuit 3 shown in FIG. 1. FIG. 7 is a block diagram showing the configuration of the area detection circuit 32 shown in FIG. 1. FIG. 8 is a block diagram showing the configuration of the area detection circuit 32 shown in FIG. 1. FIG. 9 is a block diagram showing the configuration of the area detection circuit shown in FIG. 7. FIG. 9 and FIG. 1O are timing charts showing the relationship between various control signals. 14 is a conceptual diagram showing the expansion of the intermediate 1=] area. FIG. 15 is a timing diagram showing the operation of the flag control circuit 33 and flag memory 34 shown in FIG. 8. This is a chart. FIGS. 16 and 17 are conceptual diagrams for explaining detection of mark designated areas using color marks. FIG. 18 is a plan view showing an example of area designation using color marks. 19 The figure is a plan view showing a part of the operation keys provided on the operation board. Figure 20 is a truth table showing the relationship between the setting mode and the signal kl+ of 2. Figure 21 is the 1 shown in Figure 1. Hemming/masking circuit 35. It is a block diagram showing the configuration of the hollow selection circuit 21 and the output selection circuit 38. Figures 22a and 22b are conceptual diagrams for explaining the hollowing process. is the microcomputer 39 shown in FIG.
7 is a flowchart illustrating an example of operation when setting a mark designation mode. l: Original 2; Imaging lens 3: CCD line sensor lO: Scanner 20: Video processing circuit 10.2
0: (reading means) 30: data controller 31: J degree determination circuit (comparison means) 32: area detection circuit (first area setting means) 33: flag control circuit (overlap detection means) 34 Nifrag memory
(Line memory) 33.34: (Second area detection means) 35; Trimming/masking circuit 36: Hollowing processing circuit 37: Hollowing selection circuit 38: Output selection circuit 31.36, 37, 38: (Image processing means) 39
: Microcomputer (image processing mode setting means) 40: Laser printer GAI-GA25: Gates SFI-SF3: Shift registers CPI-CP3: Comparators LA1-LAII: Latch

Claims (10)

[Claims] (1) Reading means that divides the original image into minute areas, reads the image density of the area, and outputs density data corresponding to the density; Comparison that determines whether the density data is included in the set density range. Means: A first area detection means that detects as a first area an area in which minute areas corresponding to density data included in a set range are continuous; A second area that includes the first area and is surrounded by the first area; a second area detection means for detecting an area; a first image processing mode associated with the second area, and a first image processing mode associated with other areas, according to an operator's instruction; image processing mode setting means for respectively setting a second image processing mode different from the second image processing mode; and image processing for performing processing on the density data according to the image processing mode set by the image processing mode setting means and outputting the processed data. An image processing device comprising: means; (2) When the minute area corresponding to the concentration data included in the setting range is continuous beyond a two-dimensional predetermined area, the first area detection means determines the area made up of the minute area as the first area. An image processing apparatus according to claim (1), which detects an image. (3) When the minute area corresponding to the concentration data included in the set range is continuous beyond the two-dimensional minute area, the first area detection means detects the area consisting of the minute area and the area consisting of the minute area. The image processing apparatus according to claim 1, wherein an area made up of a plurality of minute areas adjacent to the configured area is detected as the first area. (4) The first region detecting means outputs data corresponding to the detected first region of the micro region in the x direction; and the second region detecting means outputs data corresponding to the detected second region. a line memory that updates and stores the data in association with the x-direction arrangement of the minute areas, and a first area corresponding to the data by the data read from the line memory and the data corresponding to the first area. and an overlap detection means for detecting an overlap in the x direction with a second area corresponding to the data, and when the overlap detection means indicates no overlap, an area equal to the first area corresponding to the data is detected as a second area corresponding to the data. If the overlap detection means indicates that there is an overlap, x indicates the first area corresponding to the data with overlap.
The area indicated by the minimum value of the coordinate and the maximum value of the x-coordinate is
The image processing apparatus according to claim 1, wherein the image processing apparatus detects the area as a region. (5) The image processing mode setting means sets a first image processing mode for binarizing the density data corresponding to the second area;
The image processing apparatus according to claim 1, further comprising setting a second image processing mode in which density data corresponding to areas outside the second area are set to a white level. (6) The image processing mode setting means sets a first image processing mode in which the density data corresponding to the second area is set to a white level;
The image processing apparatus according to claim 1, further comprising setting a second image processing mode for binarizing density data corresponding to outside the second area. (7) The image processing mode setting means corresponds to a first image processing mode in which the density data corresponding to the second area is set as hollow image data that leaves only the edges of the original image, and a second image processing mode in which the density data corresponding to the second area is set as hollow image data that leaves only the edges of the original image. An image processing apparatus according to claim 1, wherein a second image processing mode is set for binarizing density data. (8) The image processing mode setting means includes a first image processing mode for binarizing and inverting the density data corresponding to the second area, and a binarizing process for the density data corresponding to outside the second area. The image processing apparatus according to claim 1, wherein a second image processing mode is set. (9) The comparison means sets a density range whose upper limit is a density below a threshold value of the binarization process.
The image processing device according to item (6), item (7), or item (8). (10) When the image processing mode setting means sets the first processing mode and the second processing mode, the comparison means:
Claim No. (1) which sets a predetermined concentration range
Paragraph, Paragraph (5), Paragraph (6), Paragraph (7) or Paragraph (8)
) The image processing device described in item 2.