JPS62158818U - - Google Patents
Info
- Publication number
- JPS62158818U JPS62158818U JP4659186U JP4659186U JPS62158818U JP S62158818 U JPS62158818 U JP S62158818U JP 4659186 U JP4659186 U JP 4659186U JP 4659186 U JP4659186 U JP 4659186U JP S62158818 U JPS62158818 U JP S62158818U
- Authority
- JP
- Japan
- Prior art keywords
- ground electrode
- capacitor
- common ground
- array
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
第1図は、本考案の一実施例に従つたコンデン
サ・アレイであつて、その実装用端子及び外装絶
縁体を省略した複数のチツプ実装型コンデンサに
対する共通アース電極と個別電極の配置を示す概
略平面構成図、第2図は、第1図のコンデンサ・
アレイに於いて、その裏面に設けられたアース電
極の構成を示す為の裏面アース電極構成図、第3
図は、第2図の裏面アース電極構造に各コンデン
サに対するクロストーク抑制機能を付与させるよ
うに構成した第2図と同様な裏面アース電極構成
図、第4図は、従来構造によるチツプ実装型コン
デンサ・アレイの共通アース電極と個別電極の配
置を示す第1図と同様な概略平面構成図、そして
、第5図は、第4図のコンデンサ・アレイの裏面
に共通アース電極を有しない状態を示す図である
。
1:コンデンサ・アレイ、2:個別のコンデン
サ、3:コンデンサの各電極、4:共通アース電
極、4A:裏面アース電極、5:端面の電極接続
部。
FIG. 1 is a capacitor array according to an embodiment of the present invention, and is a schematic diagram showing the arrangement of a common ground electrode and individual electrodes for a plurality of chip-mounted capacitors in which mounting terminals and exterior insulators are omitted. The plan configuration diagram, Figure 2, is the capacitor/condenser shown in Figure 1.
Figure 3 shows the configuration of the ground electrode on the back surface of the array.
The figure shows the configuration of a back ground electrode similar to that in Figure 2, in which the back ground electrode structure shown in Figure 2 is configured to provide a crosstalk suppression function for each capacitor, and Figure 4 shows a chip-mounted capacitor with a conventional structure.・A schematic plan configuration diagram similar to FIG. 1 showing the arrangement of the common ground electrode and individual electrodes of the array, and FIG. 5 shows a state in which there is no common ground electrode on the back side of the capacitor array in FIG. 4. It is a diagram. 1: capacitor array, 2: individual capacitors, 3: each electrode of the capacitor, 4: common ground electrode, 4A: back ground electrode, 5: electrode connection on end surface.
Claims (1)
サを並列接続するようにしたコンデンサ・アレイ
に於いて、上記共通アース電極を各コンデンサの
裏面にも形成するように構成したことを特徴とす
るコンデンサ・アレイ。 A capacitor array in which a plurality of chip-mounted capacitors are connected in parallel to a common ground electrode, characterized in that the common ground electrode is also formed on the back surface of each capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4659186U JPS62158818U (en) | 1986-03-28 | 1986-03-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4659186U JPS62158818U (en) | 1986-03-28 | 1986-03-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62158818U true JPS62158818U (en) | 1987-10-08 |
Family
ID=30866393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4659186U Pending JPS62158818U (en) | 1986-03-28 | 1986-03-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62158818U (en) |
-
1986
- 1986-03-28 JP JP4659186U patent/JPS62158818U/ja active Pending