JPS62158539U

JPS62158539U -

Info

Publication number: JPS62158539U
Application number: JP4421886U
Authority: JP
Priority date: 1986-03-26
Filing date: 1986-03-26
Publication date: 1987-10-08

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示すブロツク図
、第２図は従来の装置を示すブロツク図。１はキーマトリクス、２はタイミング信号発生
器、３はデータバツフア、４は入力モード管理部
、５はＣＰＵ、６は入力モード設定スイツチ、１
１はスキヤンデータ、１２は戻り信号、１３はロ
ード信号、１４は入力モードデータ、１５はキー
データ及び入力モードデータ。尚、各図中同一符
号は同一又は相当部分を示す。 FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional device. 1 is a key matrix, 2 is a timing signal generator, 3 is a data buffer, 4 is an input mode management section, 5 is a CPU, 6 is an input mode setting switch, 1
1 is scan data, 12 is a return signal, 13 is a load signal, 14 is input mode data, and 15 is key data and input mode data. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A key matrix in which a plurality of key switches are arranged in a matrix, and an address signal whose numerical value changes sequentially to scan whether each key switch is in an off state or an on state according to the arrangement order of each key switch in this key matrix. A timing signal generator that generates scan data, and latches the value of the scan data as key data at the time when a signal indicating that the key switch is in the on state is obtained while scanning the key matrix using the scan data. data buffer,
an input mode management unit that outputs set input mode data; a means for inputting the key data and the input mode data to generate a code corresponding to the input; and an input mode management unit that outputs arbitrary input mode data for the input mode management unit. A keyboard input device equipped with an input mode setting switch for setting.