JPS62157473A - Clamping circuit - Google Patents

Abstract

PURPOSE:To execute a comparator operation without fail by attaining a clamp which possesses a characteristic of having a fully large quantity of a charge time constant or a discharge time constant during a clamp pulse inputted time to clamp without losing stepped information a line sequential color difference signal whose reference level differs every 1H. CONSTITUTION:Time constant during charging a capacitor 2 (charge time constant) is set fully large, for example, about 10H-20H. When the line sequential color difference signal reproduced in a magnetic disk is supplied to a signal terminal 1, this signal is clamped by the transistor 4 through the capacitor 2. However, the base electric potential of the transistor 4 keeps prescribed electric potential only when the clamp pulse is inputted to the base of the transistor 9, namely, only when the level goes high. During the other period, the electric potential goes down until the transistor 4 comes to be a total OFF-condition. In actuality, therefore, a kind of diode clamp operation is executed only when the clamp pulse is inputted, namely, in the high level time, and the electric potential of the outputted signal is maintained in the low level time.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a clamp circuit for clamping video signals, and more particularly to a clamp circuit for clamping line-sequential color difference signals employed in electronic still cameras and the like.

B0 Summary of the Invention The present invention relates to a clamp circuit for clamping a line-sequential color difference signal employed in an electronic still camera or the like. By clamping one blanking portion, line-sequential color difference signals can be clamped without losing step information.

BACKGROUND ART Conventionally, electronic still cameras have been known that have an imaging device such as a charge-coupled device (C0D) and record arbitrary still images on a magnetic disk.

This electronic still camera employs a line-sequential color difference signal in which color difference signals 5it-y1-5B-Y are alternately arranged every horizontal scanning period (IH) as shown in Figure 3). Here, the color difference signal SRY is obtained by subtracting the luminance signal component from the red signal component.
The color difference signal 5n-y is obtained by subtracting the luminance signal component from the blue signal component.

Regarding each color difference signal 5R-Ys 5B-Y,
The maximum amplitude is shown in each figure. On the other hand, during playback,
It is necessary to obtain a pulse (If pulse) from the reproduced signal to determine whether the color difference signal is 5R-Y or 8B-Y. For this reason, the color difference signal 5R-YIS B-Y is provided with a level difference from the pedestal level, which is the reference level, and during playback, detection is performed using the step in the blanking part. There is.

D1 Problems to be Solved by the Invention By the way, in the If) pulse generation circuit for generating more pulses, conventionally the line sequential color difference signals 5R-y, 5B-
Y clamping is not performed, and the stepped portion of the signal input through capacitor coupling (so-called C couple) is used as is. Therefore, the signal A P L (Aver
There is a drawback that the absolute DC level at the step portion changes depending on the peak level (Peak Level), and the operation of the comparator at the subsequent stage becomes uncertain. In order to ensure the operation of this comparator, it is sufficient to perform clamping, but a normal diode clamp cannot be used because the clamping is performed at the bottom end of the image area. Furthermore, in the normal keyed clamp (pulse clamp) using a clamp pulse every 1H as shown in FIG. 3(B), the step information of the line sequential color difference signals 5rt-y and 5R-Y is lost. . Furthermore, it is possible to perform keyed clamping using clamp pulses at every IH as shown in Figure 3 (Q), but the number of scanning lines constituting one screen is an odd number of 525 and differs from frame to frame. The blanking portion of the color difference signal is clamped.

Therefore, neither can be used.

SUMMARY OF THE INVENTION The present invention has been proposed in view of the above-mentioned conventional problems, and provides a lamp circuit that can clamp line-sequential color difference signals having different reference levels every 1H without losing step information. The purpose is to

Means for Solving the E0 Problem In order to achieve the above-mentioned object, the clamp circuit of the present invention clamps line-sequential color difference signals with different reference levels every horizontal scanning period, and the clamp circuit clamps the line-sequential color difference signals with different reference levels in each horizontal scanning period. It is characterized by performing clamping having a sufficiently large time constant or discharge time constant.

20 Effects According to the present invention, for example, the blanking portion of one of the line sequential color difference signals consisting of a color difference signal with a low reference level and a color difference signal with a high reference level is clamped.

0. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a two-amplifier circuit according to an embodiment.

In FIG. 1, a signal input terminal 1 to which a line-sequential color signal is supplied is connected via a clamp capacitor 2 to the base of an emitter follower transistor 3 and to the emitter of a clamp transistor 4, respectively. The base of the transistor 40 is connected to the emitter of a transistor 6 via a resistor 5. Also, this transistor 6
The emitter of the transistor 7 is connected to the collector of the transistor 7, and the base of the transistor 7 is connected to a DC power supply 8 which provides a reference potential. The emitters of the transistor 9 to which the clamp pulse is supplied to the pace and the transistor 11 to which the DC power supply 10 is connected are commonly connected to the collector of the transistor 12. The collector of the transistor 11 is connected to the connection point between the transistor D and the resistor 5.

Further, the emitter of the transistor 3 of the emitter follower is connected to the collector of the transistor 13 and the signal output terminal 1.
4 are connected to each other. Furthermore, the time constant (discharge time constant) during discharging of the capacitor 2 is, for example, IOH ~ 20
It is set sufficiently large, about H. Further, the clamp level is determined to be E-2VBE by the voltage value E of the DC power supply 8 and the pace-emitter voltage VBE of the transistor 5.

In the clamp circuit configured as described above, when a line-sequential color difference signal reproduced from, for example, a magnetic disk is supplied to the signal input terminal 1, this signal is passed through the capacitor 2 and sync-clamped by the transistor 4. However, the pace potential of the transistor 4 becomes a predetermined potential only when a clamp pulse is input to the pace transistor 90, that is, only when it becomes a high level, and during that period, it reaches a potential that sufficiently turns off the transistor 4. It's going down. Therefore, in reality, a type of diode clamping operation is performed only when the clamp pulse is input, that is, when the level is high, and the potential of the input signal is held when the level is low.

This will be explained in detail with reference to FIG. As shown in FIG. 2 (5), the line-sequential color difference signal supplied to the signal input terminal 1 is such that the color difference signals 5u-y-l, 5B-Y are alternately lightning-proofed every 1H, and the line-sequential color difference signal is at the reference level. Level differences are provided for each Bedistal level. In addition, the base of the transistor 9 has an IH4j as shown in FIG.
A clamp pulse of f is supplied. The clamp pulses are synchronized so that each color difference signal 5R-Y+5B-Y becomes high level in the blanking portion where the signal level becomes a bedrock level. As mentioned above, a clamping operation is performed at this time, but in reality, only the blanking portion of the color difference signal S R'''Y with a low pedicle level is clamped. The level of the blanking part of the signal SRY is
When the clamp level becomes lower than the broken line shown in Figure (5), the transistor 4 turns on and the charging time constant decreases, so the capacitor 2 is charged according to the potential difference and the blanking part is charged. The level is raised,
It is clamped to the clamp level. As described above, this clamp level is determined by the voltage value E of the DC power supply 8, the voltage value of the transistor 6, and the pace-emitter voltage VBE of the transistor 6, and becomes E-2VBE. on the other hand,
Since the level (pedicle level) of the blanking portion of the color difference signal 5n-y has a high potential, the discharge time constant of the transistor 4 becomes large in the off state, and the input potential is maintained as it is.

In this way, the clamp circuit of this embodiment performs so-called bottom clamping, and the clamp pulse is If-]
Even though it is a @ pulse, the blanking portion of the color difference signal 5R-y at every IH can be clamped by a mirror so-called diode clamp.In addition, the step information can be retained without being lost.

Note that the present invention is not limited to the embodiments described above, and so-called peak clamping can also be performed. In this case, it goes without saying that the circuit configuration may be such that the charging time constant of the capacitor is large and the discharging time constant is small when the clamp pulse is input.

H0 Effects of the Invention As is clear from the description of the embodiments described above, the clamp circuit of the present invention performs clamping having a sufficiently large charging time constant or discharging time constant when a clamp pulse is input. , it is possible to clamp line-sequential color difference signals whose reference levels differ from day to day without losing step information. Therefore, for example, the operation of the subsequent comparator can be made more reliable.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a clamp circuit according to an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the clamp circuit. FIG. 3 is a time chart showing an example of a line-sequential color difference signal and a clamp pulse. 2... Capacitor Y9*11... Transistor 8... DC power supply

Claims (1)

[Claims] A clamp circuit for clamping line-sequential color difference signals having different reference levels for each horizontal scanning period, characterized in that the clamp circuit performs clamping having a characteristic of having a sufficiently large charging time constant or discharging time constant when a clamp pulse is input.