JPS62157141U - - Google Patents

Info

Publication number
JPS62157141U
JPS62157141U JP4561786U JP4561786U JPS62157141U JP S62157141 U JPS62157141 U JP S62157141U JP 4561786 U JP4561786 U JP 4561786U JP 4561786 U JP4561786 U JP 4561786U JP S62157141 U JPS62157141 U JP S62157141U
Authority
JP
Japan
Prior art keywords
chip
island
magnet piece
magnetic layer
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4561786U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4561786U priority Critical patent/JPS62157141U/ja
Publication of JPS62157141U publication Critical patent/JPS62157141U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Die Bonding (AREA)
JP4561786U 1986-03-27 1986-03-27 Pending JPS62157141U (US07534539-20090519-C00280.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4561786U JPS62157141U (US07534539-20090519-C00280.png) 1986-03-27 1986-03-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4561786U JPS62157141U (US07534539-20090519-C00280.png) 1986-03-27 1986-03-27

Publications (1)

Publication Number Publication Date
JPS62157141U true JPS62157141U (US07534539-20090519-C00280.png) 1987-10-06

Family

ID=30864516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4561786U Pending JPS62157141U (US07534539-20090519-C00280.png) 1986-03-27 1986-03-27

Country Status (1)

Country Link
JP (1) JPS62157141U (US07534539-20090519-C00280.png)

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