JPS62152367A - Chopper - Google Patents

Abstract

PURPOSE:To enable a switching element to be controlled without detecting load voltage, by turning the switching element OFF in a specified delay time after current flowing when the switching element is ON comes to a reference value. CONSTITUTION:The output of a power source Vs is fed to a load DL via a chopper circuit CHP. Current flowing to an inductance serving as an energy storage element when a switching element on the chopper circuit CHP is ON is detected by a detection means D1, and the detected value is compared with a reference value coming from reference voltage Vr. In a delay time set by a delay circuit DLY after detected current comes to a reference value, the switching element of the chopper circuit CHP is turned OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a chopper device with an improved control circuit for switching elements, and is particularly suitable for controlling constant load power or constant load voltage.

(Background Art) Conventionally, a chopper device as shown in FIG. 10 has been widely used. In the figure, Vs is a DC power supply, and D[, is a load. As the load DL, discharge lamps (especially high-intensity discharge lamps H
I D = High Intensity D i
scharge lamp), but the same is true for pond loads. ■a is the load voltage (discharge lamp voltage), ■ga is the load current (discharge lamp current), and W gummy is the load power (discharge lamp power). Chitapper circuit C
11P is a switching element SW such as a transistor,
energy? It includes an inductance L for ff M, a flywheel diode FD, and a chopper output smoothing capacitor C, and these circuit elements constitute a well-known step-down chopper circuit. Is is the current flowing through the switching element SW, ■p is the current flowing through the flywheel diode FD, and T +- is the current (11-:=I n + I s) flowing through the inductance L.

In the chopper device as described above, there is a technical demand for obtaining output characteristics such that the load power W included a is constant even if the load characteristics of the discharge lamp DI- vary. This is because the load characteristics of the discharge lamps DL vary greatly depending on their characteristics, and the relationship between the luminous flux and the load power (Qm/W) is fixed, so the load power W9a
This is because if it is not constant, the luminous flux will differ between lamps, which is inconvenient.

Therefore, as shown in FIG. 11, it has been proposed to add a constant load power control circuit to the chopper device to control the load power W to be constant. In the circuit of FIG. 11, O20 is a reference pulse generator, which includes a general-purpose timer IC (Signetics NE555, etc.), a resistive element and a capacitor added to this, as illustrated within the broken line in the same figure, Square wave voltage Vos of a predetermined frequency
generate c. FF is a 70-tube R37 lip, CMP is a voltage comparator, and AMP is an operational amplifier.

FIGS. 12(a) to 12(e) are explanatory diagrams of the operation of the circuit shown in FIG. 11. Hereinafter, the fjS11 diagram circuit will be explained together with the child circuit operation with reference to FIGS. 12(a) to 12(e).

Now, the R input of the RS 71j knob 70 knob FF is at L level, and the output Vosc of the reference pulse generator O8C (Fig. 12 (
Assume that a)) is at the L level, therefore, the R87 lip FFf) S input is at the L level. Also, R87
The switching element SW is turned off at the Q output VppML level of the lip 70-tube FF.

When the output V osc of the reference pulse generator O8C becomes H level, the S input of the S7 lip 70-tube FF goes to I level, the R87 lip 70-tube FF is set, and its Q output Vpp (fPJ12 figure ( e)) becomes the F■ level.As a result, a bias current flows to the switching element SW via the bias resistor Rsu+, so the switching element SW is turned on and inductance current 1. starts to flow.At the current IL. Energy is supplied to the load D L and the capacitor C, and energy is stored in the inductance.Tdl is a current transformer for detecting the inductance current 1, and detects the detection voltage Vdl. Also, Rdl
, Rd2 are voltage dividing resistors for detecting the load voltage VIZa, and obtain a detection voltage VdQa (FIG. 12(b)). The detection voltage V d Q a is inverted and amplified by the operational amplifier AMP, and an output voltage Vao is obtained. The operational amplifier AMP has a reference voltage source Vrer connected to its non-inverting input (+ side), and a DIN resistor Ra connected between its output and its inverting input (- side) to constitute an inverting amplifier. Inductance current 1. The detection voltage VdL of the load voltage VQa and the output voltage Vao obtained by inverting and amplifying the detection voltage VdQa of the load voltage VQa are:
It is input to the voltage comparator CMP (@12 (C)), and Vd
When L≧Vao, the output of the voltage comparator CMP ■co(
FIG. 12(d)) shows the H level. By this, R
37 lip 70 knob FF R input! -■ level, R37 lip 70 knob FF is reset, its Q output ■FF goes to L level, and switching element SW
is off. Then, the energy stored in the inductance L is released to the load DL and the capacitor C via the 7-light wheel diode D until the output V osc of the pulse generator O8C reaches the next level I. The same operation will be repeated from now on.

Therefore, in the circuit of FIG. 11, the value of the inductance current I at which the switching element SW is turned off is determined depending on the magnitude of the load voltage V, 9a, and the switching element performs PWM operation. That is, the load voltage VjJa
As becomes smaller, the voltage \'ao becomes larger, and when the inductance current IL is large, the switching element SW is turned off.

Conversely, as load voltage VQa increases, voltage V
ao becomes small, and when the inductance current IL is small, the switching element SW is turned off.

Therefore, if the load voltage VQa is small, the inductance current IL is large, and if the load voltage VQa is large, the inductance current ■L becomes small, and eventually the load voltage ■Qa
Regardless of the above, fluctuations in the load power Wpa can be reduced, and even if the load characteristics change, constant power can be supplied to the load DL.

Let me explain this in some quantitative detail. The chopper circuit CHP in the circuit of FIG. 11 is equivalently shown in FIG. 13(a). When the switching element SW is on, the circuit shown in FIG. 13(b) is configured, and the inductance current IL is 1. is the inductance current 1.of the line 11f7 which is generated when the switching element SW is turned on. The time t is 0 at the moment the switching element SW is turned on.

Here, the conduction time of the switching element SW is assumed to be ton, and 1. The inductance current when the switching element SW is turned off is 1. If the threshold value is I, = I
At the time t=ton when T is reached, the switching element SW is turned off, and the chopper circuit CHP equivalently becomes as shown in FIG. 13(c). At this time, the current ID flowing through the flywheel diode FD is
It is the same as the inductance current IL, and becomes. When the switching element SW is off, the current ID
%, that is, the inductance current 1. When calculating the open time tF when is flowing, since I L = I in equation (3), here, the non-conduction time of the switching element SW to [,
Tosc the operating cycle of the chopper circuit CHP.

If ("ton+to[)", the operating period tosc is a fixed length determined by the oscillation period of the reference pulse generator O8C, so the off period tofr of the switching element SW is
torf=tosc-ton. ton+tF≦t
Since osc, the current I. The value of is . When the inductance current IL is flowing, til
l t F niha, ()<tF≦torr constraint Kaari, only when tF=torf, the above equation (5) is applied, and (if 1<tF<toff, I o =
becomes <).

Hereinafter, in order to simplify the explanation, for convenience, I.

=0, that is, 0<tF<to[.

At this time, due to (6), the inductance current is 1. The size of will be determined. The diagram fjS14 shows the temporal change of this inductance current ■L.

Now, the load current I in a is proportional to the energy supplied by the chopper circuit CI-IP (because the smoothing capacitor C is connected in parallel across the load DL). Therefore, it can be considered that (load current I gua) = (average value of inductance current IL). From formula (6) and Figure 14, the average value ILA of the inductance current ■ is: =Igua...(7
), and if the power factor of the load DL is 1, then WQa=VQ
, aXIQa, the load power is expressed by the following formula. If the threshold current ■, is not controlled by the load voltage ■including a, as in the circuit shown in fjS11, then if the load voltage ■ρa rises, the load power W Q
It is clear that a increases.

Now, for comparison, two values Vffia are used as the load voltage.
= V (1, +tV Qx< Tata L V l + <
V Qz) Consider it.

Threshold current1. is constant, each load voltage V included a=V! 2. ．． ．． Load power W for Vβ2
12 a ” W Q , 1.W Q 21 becomes.On the other hand, as in the circuit shown in fjS11, the load voltage V!l
If the threshold current T becomes small when a is large, the load voltage ■a=■ri1. The threshold current IT for V included is T ``+ l T2 (I [> T T2
), load power W Q a is W Q 1. - W Q 2
As 2, it becomes. Equation (10) = Equation (12), but Equation (11)> Equation (+3) is 1. >1.
It is clear from the fact that it is 2. That is, fjr111
By performing the control shown in FIG. 1111, it is possible to reduce changes in load voltage Vinc a, that is, changes in load power WQa with respect to load fluctuations. Furthermore, if equation (12) = equation (13), it is possible to keep the load power WQa constant. This is achieved by controlling the following.

By adopting such a control method, the output characteristics of the chopper device can be improved as described above, but the control circuit becomes complicated because it is necessary to constantly detect the load voltage VMa. There is a problem with doing so. Furthermore, if fluctuations in the power supply voltage are taken into account, the number of detection points increases, resulting in further complexity.

(Objective of the Invention) The present invention has been accomplished in order to solve the above-mentioned problems, and its purpose is to suppress fluctuations in load power due to load fluctuations and power supply fluctuations. It is an object of the present invention to provide a chopper device that can realize control using a simple configuration without directly detecting load voltage or the like from the load.

(Disclosure of the Invention) To explain the chopper device according to the present invention with reference to illustrated embodiments, as shown in FIGS. 1 to 9, a DC power source V
s, a load DL, a switching element SW that is turned on and off at high frequency, and an energy storage element that is supplied with energy from the DC power supply Vs when the switching element SW is on and supplies energy to the load DL when the switching element SW is off. In a chopper device equipped with an inductance L, a current IL flowing through an energy storage element is detected when a switching element SW is turned on, and a predetermined delay time td is set from the time when the detected current 1 +- reaches a predetermined reference value I□. A control circuit is provided to turn off the switching element SW after the lapse of time.

:jS] A basic configuration diagram for explaining the present invention in detail is shown in FIG. In the figure, Vs is a DC power supply, DI- is a load, and CHP is a chopper circuit. Chopper circuit CH
As P, a step-down chopper circuit as illustrated in FIG. 1() or any other arbitrary chopper circuit can be used. The current detection means D1 detects the current L flowing through the inductance when the switching element is turned on, and generates a detection voltage. The voltage comparator CMP compares this detected voltage with the base voltage vT, and produces a comparison output when the detected voltage reaches the base voltage VT. In the delay circuit DLY, the comparison output of the voltage comparator CMP is delayed by a predetermined delay time td.
output with a delay of The switching element control means Csw turns on the switching element SW at fixed time intervals using the output of the base pulse generator O8C, and controls the delay circuit DLY.
The switching element SW is turned off by the output.

As a result, as in the conventional example, the load voltage V! : By detecting la, the threshold current 1. The same effect as when variable is obtained can be obtained. That is, the inductance current 1.
contains the component of the load voltage VQa as shown in equations (1), (3), and (6) above, so it can be extracted with a simple configuration and used to control the switching element SW. I can do it.

As before, for convenience, ■, = 0.0 < tF < to
The principle of the present invention will be quantitatively explained using sC. The inductance current ■L is...C15). Here, the maximum value of IL is Ip1. By the delay time td, the threshold current 1. Differently, ...(16) becomes. Therefore, the switching element sw is off,
The period 1F during which the inductance current is I t ≧0 is as follows. (17) Now, if we calculate the average value 1 + - 8 of the load current lff1a as before, we get t T, osc V Ma (V s - V 2a)
=■include a...(1
8) As is clear from this, r+-A is the threshold current 1. and delay time td.

Furthermore, if the delay time td=o in equation (18), it completely matches equation (7) described in L. As before, W Qa=
r, (LaX V ff1as tosc (19). When the power supply voltage Vs, fundamental period tosc, and inductance L are constant, a certain load voltage Vg, a=V
! 2. ．． In, as in the conventional example, the delay time td=0
(TT=IT1) and, as in the present invention, when the delay time opening td>0 (IT=IT2), both have the same value of the load power W Q a = W Q l. If so, IT+>IT2, (td=0) (td>03 ...(20) From this, ...(21) can be set.If the load voltage Vfia is high, When a=VJZ2, (td=o) (td>O) (22) Here, if we compare the magnitude of W Q 2 and W Q ), we get
XJL(Vs VJZ2)・(Ir+IT2)・
...(23) In this formula (23), V Q2 > V Q +
Since t V s > V 42211Tl > IT2, the value of equation (23) is positive.

Therefore, WQ2>V#-r. That is, the load voltage V
It can be seen that even if Qa increases, if the control of the present invention is used, the increase in load power WQa can be suppressed, as in the case of the above-mentioned complicated conventional example.

FIG. 2 is an explanatory diagram showing this operation. As shown in FIG. 2, in the present invention, as the load voltage Vffia increases, the maximum current value rp decreases. It can be seen that this is the same operation as in the conventional example, when the load current VQa increases, the threshold current IT decreases.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 3 is a circuit diagram of a chip shipper device according to a first embodiment of the present invention. Elements that are the same as those of the conventional example are given the same reference numerals and detailed explanation thereof will be omitted. In this embodiment, the detected voltage VdL of the inductance voltage i1 is compared with a threshold voltage VdL by the voltage comparator CMP.

This voltage Vd corresponds to the threshold current rT mentioned above. The output Vco of the voltage comparator CM_P is input to the pulse delay circuit DLY. The pulse delay circuit DLY compares the outputs of the reference voltage source VI and the CR integration circuit including the fundensor CI and the resistive elements R, , R2, as illustrated in the broken line in Fig. f53, for example. It generates an output V DLY delayed by a time td with respect to the output Vco of the voltage comparator CMP. Output ■ of this pulse delay circuit DLY. LY
is connected to the R input of the R87 lip 70-tube FF. The output V osc of the reference pulse generator O8C is connected to the S input of the R87 lip-flop FF. The control electrode of the switching element SW is RS 7 'J tube 7
It is connected to the Q output of the 0-tube FF, and this Q output VF
By changing the F level by one degree from the H level to the L level, the power can be turned on or off.

FIGS. 4(a) to 4(e) are explanatory diagrams of the operation of the circuit of FIG. 3. The operation of the circuit shown in FIG. 3 will be explained below with reference to FIGS. 4(a) to 4(e). Now the reference pulse generator O8
The output Vosc of C (Fig. 4 (a)) is at L level, the output V DLY of delay circuit DLY is at L level, and the output VFF of RS flip 70-tube FF is at L level, so switching element SW is off. shall be taken as a thing.

When the output Vosc of the reference pulse generator os'c becomes high, the R37 lip 70-tube FF is set, and its Q output VF, -h (becomes H level).As a result, the switching element SW is turned on, and the DC A current flows from the power supply S to the load DL and the capacitor C via the switching element SW and the inductance L, and energy is accumulated in the inductance.

At this time, a voltage VdL proportional to the inductance current ■L is detected by the current detection transformer TdL. This voltage VdL and the threshold voltage V0 of the reference voltage source are compared by a voltage comparator CMP (Figure 54 (b).
)). When VdL≧vd, the output Vco (FIG. 4(C)) of the voltage comparator CMP becomes H level. In the pulse delay circuit DLY, the output Vco of the voltage comparator CMP is ■]
After a predetermined delay time td has elapsed, the output V DLY (FIG. 4(d)) becomes H level. As a result, the R input of the R87 lip 70-tube FF becomes H level, the R37 lip 70-tube FF is reset, and its Q output VFF < Fig. 4 (e)) goes to L level, and the switching element SW is turned off. . below,
Repeat the same action.

As a result, after the inductance current IL reaches the threshold current, the switching cord SW is turned off after a predetermined delay time td has elapsed. Therefore, as described above, it is possible to reduce fluctuations in load power WMa with respect to load fluctuations. Furthermore, unlike the conventional example, it is not necessary to directly detect the load voltage V9a, so the circuit configuration becomes simple.

The fjSs diagram shows a circuit diagram of a second embodiment of the present invention.

Elements that are the same as those in the previous embodiment are given the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the inductance current IL is detected by the resistor Rd, and the detected voltage V
dL is the operational amplifier AMP, the capacitor Cd, and
A differential circuit including resistive elements Rdl and Rd2 is manually operated. The output voltage ■ao of the differentiating circuit is a voltage proportional to the slope of the inductance current IL. This voltage Vao is
The voltage is integrated by an integrating circuit including an integrating capacitor C, a resistive element R, and an integral control switch St, and an integrated voltage (■■) is generated across the capacitor CI. This integrated voltage ■■ is compared with the threshold voltage ■T by a voltage comparator CMP. The output Vco of the voltage comparator CMP is connected to the 8-channel power of the R37 lip 70 tube FF. The output V osc of the reference pulse generator O8C is connected to the S input of the RS7 lip 70-tube FF. The Q output of the R37 lip 70-tube FF is also input to the pulse delay circuit DLY. Pulse delay circuit 1)
L Y is the Q output VFF of the R87 lip 70-tube FF.
An output Vat-y is generated which is delayed by a time td. The output V DLY of this pulse delay circuit D L Y is connected to the control electrode of the integral control switch S1.

The control electrode of the switching element SW is RS 717p7
It is connected to the Q output of the 0-tube FF, and turns on/off by switching the Q output VFF to H level/L level.

6(a) to 6(g) are explanatory diagrams of the operation of the circuit of FIG. 5. The operation of the circuit shown in FIG. 5 will be explained below with reference to FIGS. 16(a) to 16(g). Now the reference pulse generator O8
Assume that the output V osc of C is at L level, the output Vco of voltage comparator CMP is at L level, and the Q output VFF of R37 lip 70 tube FF is at L level, so that switching element SW is off. Output V o of reference pulse generator O8C
When the sc reaches the tr level, R87 lip 70 knob FF
Since the S human power becomes H level and its Q output VFF becomes H level, switching element SW is turned on. As a result, the switching element SW,
A current flows through the load DL and the capacitor C through the inductance l, and energy is stored in the inductance. The current I + - flowing through the inductance is converted into a detection voltage Vdl by a current detection resistor Rd. This detection voltage VdL is converted into a voltage Vao proportional to the slope of the inductance current IL by a differentiating circuit including an operational amplifier A MF', a capacitor Cd, and resistance elements Rdl and Rd2. After the Q output VFF of the R37 lip 70 tube FF becomes H level and a predetermined delay time td has elapsed since the switching element SW was turned on, the output of the pulse delay circuit DLY becomes F (level,
Integral control switch S1 is turned on. As a result, the capacitor C1 is charged from the initial value () volts via the integrating resistor R2 with a voltage VaO that is proportional to the slope of the inductance current ■L. The voltage across the capacitor CI, that is, the integrated voltage vI, is compared with the reference voltage T by the voltage comparator CMP, and the integrated voltage is compared to the reference voltage T.
When it reaches ``output Vc of voltage comparator CMP.''

becomes the ToI level. At this time, the R power of the RS flip 70 knob FF becomes H level, so the R37 lip 70
The knob FF is reset, its Q output VFF rises to the level, and the switching element SW is turned off. Repeat the same operation below.

As a result, when the load voltage VJZa increases, the slope of the inductance current 1 becomes smaller and the voltage Vao becomes lower, so the time required for the integrated voltage V to reach the reference voltage 2 becomes longer, and the switching element SW As a result, the same effect as the first embodiment can be obtained.

FIG. 7 shows a circuit diagram of a third embodiment of the invention.

This embodiment is designed to also compensate for voltage fluctuations in the DC power supply Vs. Elements that are the same as those in the previous embodiment are given the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the power supply voltage \ls of the DC power supply Vs is connected to the voltage dividing resistor R.
It is detected at s+-Rs2.

This detection voltage is the operational amplifier AMP? In resistance Ra,
and an inverting amplifier including a reference voltage source V ref,
The signal is inverted and amplified to obtain an output voltage Vao.

On the other hand, the inductance current 1. is detected by a resistor Rd, and the detected voltage VdL is compared with the voltage Vao by a voltage comparator CMP. Output Vc of voltage comparator CM P
o is delayed by a predetermined time td in the pulse delay circuit DI-Y and applied to the R input of the R37 lip 70-tube FF. Similar to the previous example, R37 lip 70 tube F
The S input of F is the output V o of the reference pulse generator O8C.
sc is connected, and this R37 lip 70 tube Q
The switching element SW is on/off controlled by the output.

The operation of the circuit in FIG. 7 is almost the same as the fjS1 embodiment. However, the detection voltage VdL of the inductance current IL is obtained by the resistor Rd, and when the power supply voltage Vs changes, it is inverted by the inverting amplifier including the operational amplifier AMP, the ding resistor Ra, and the reference voltage source Vref. The difference is that the voltage VaO corresponding to the threshold voltage 7 of the fjS1 embodiment is changed by amplification. That is, when the power supply voltage Vs is large,
When the voltage Vao corresponding to the threshold voltage vd becomes small and the power supply voltage Vs is small, the voltage Vao corresponding to the threshold voltage vT becomes large. therefore,
In the above equation (19), ! , becomes a parameter,
Only for a certain load voltage VQa, fluctuations in load power WQa with respect to fluctuations in power supply voltage Vs can be suppressed.

(Only one point fluctuated 0). Thereby, it is possible to compensate for fluctuations in the power supply voltage Vs more easily than in the conventional example.

FIG. 8 shows a circuit diagram of a fourth embodiment of the present invention.

In this embodiment, the compensation of the power supply voltage Vs in the 13th embodiment is as follows.
This is realized by making the delay time td variable instead of using seven threshold voltages. Elements that are the same as those in the previous embodiment are given the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the pulse delay circuit DLY is connected to the capacitor C.
9L, a CR integration circuit including a resistance element RDLIIRDL2, and a voltage comparator CMPD. As a reference voltage of the voltage comparator CMPD, a voltage Vao obtained by inverting and amplifying the divided voltage of the power supply voltage Vs is used. . When the power supply voltage Vs is large, the voltage Va obtained by inverting and amplifying the partial voltage of this voltage is
o is small, and therefore the time for the voltage VDL across the capacitor C8L to become equal to the voltage Vao, that is, the delay time td, becomes short. Conversely, when the power supply voltage Vs is small, the voltage Vao is large, and the voltage V across the capacitor CDL is
The time when DL becomes equal to the voltage Vao, that is, the delay time t
d becomes larger. Therefore, from the above equation (19), only for a certain load voltage VQa, the variation in the load power W included a with respect to the variation in the power supply voltage Vs becomes (), and the same effect as in the third embodiment can be obtained by varying the delay time td. This can also be achieved by

FIG. 9 is a circuit diagram of a fifth embodiment of the present invention.

The third and fjS4 embodiments described above have a threshold current of 1. By making either the threshold voltage V, which corresponds to . In the fifth embodiment, these threshold voltages V and delay times t
cl and cl are both made variable, and the variation in load power WQa at all load voltages VQa is made almost zero. In this embodiment, instead of the threshold voltage V□ in the f:IS8 diagram circuit, the above-mentioned inverted and amplified voltage V
This uses ao. Regarding the operation of this embodiment,
The operations of the third embodiment and the fourth embodiment are performed simultaneously. That is, when the power supply voltage Vs is large, the delay time td is controlled to be short and the thren third current IT is small, and when the power supply voltage Vs is small, the delay time td is controlled to be small.
The control is performed so that d is large and the third lead current IT is large. Changes in the delay time td with respect to the power supply voltage Vs and the current 1. If the changes in are properly designed, it is possible to make the load voltage VJZa and the load power W included a substantially constant when the power supply voltage Vs fluctuates in the above equation (19). Such control is
In the conventional example, this was accomplished by adding very complicated means, but the present invention can easily realize this.

(Effects of the Invention) As described above, in the present invention, the switching element is turned off after a predetermined delay time has elapsed after the current flowing when the switching element is turned on reaches the reference value. The reference value, delay time, etc. can be set so that output fluctuations due to load fluctuations are suppressed, and the switching elements can be controlled without detecting the load voltage as in the case of conventional methods. This has the advantage that voltage control, constant load power control, etc. can be easily realized even in conventional uplinks.

[Brief explanation of drawings]

fjt11 is a basic configuration diagram of the present invention, FIG. 2 is an explanatory diagram of the same operation as above, and FIG. 3 is a circuit diagram of the first embodiment of the present invention.
5 is a circuit diagram of the second embodiment of the present invention, FIG. 6 is a diagram of the same operation as above, fjS7 is a circuit diagram of the third embodiment of the present invention, and FIG. 8 is an explanatory diagram of the same operation as above. is a circuit diagram of the fourth embodiment of the present invention, FIG. 9 is a circuit diagram of the :55 embodiment of the present invention, FIG. 1() is a circuit diagram showing the basic configuration of the conventional example, and FIG. 11 is a circuit diagram of the conventional example. A circuit diagram showing a detailed configuration, FIG. fjS12 is an explanatory diagram of the same operation as above, FIGS. 13(,) to (c) are equivalent circuit diagrams of the same as above, and FIG. Vs is a DC power supply, DL is a load, SW is a switching element, I- is an inductance, TdL is a transformer, r (d is a resistance, CMP is a voltage comparator, DLY is a pulse delay circuit,
FF is R87 lip 70 lip.

Claims (4)

[Claims] (1) A chopper that includes a DC power supply, a load, a switching element that is turned on and off at high frequency, and an energy storage element that is supplied with energy from the DC power supply when the switching element is on and supplies energy to the load when the switching element is off. The device includes a control circuit that detects a current flowing through the energy storage element when the switching element is turned on, and turns off the switching element after a predetermined delay time has elapsed from the time when the detected current reaches a predetermined reference value. A chopper device characterized by: (2) In the device according to claim 1, the control circuit includes a delay circuit that generates a delayed output after the delay time has elapsed from the point when the switching element is turned on, and a voltage that corresponds to the slope of the detected current. A differentiating circuit that outputs an output, an integrating circuit that starts an integrating operation with the delayed output of the delay circuit, and outputs a voltage obtained by integrating the output voltage of the differentiating circuit, and when the output voltage of the integrating circuit reaches a predetermined voltage. , and a voltage comparator that outputs a signal to turn off a switching element. (3) The device according to claim 1, wherein the reference value of the detected current and the delay time are set so that the load power remains constant with respect to fluctuations in the load voltage. Chopper device. (4) In the device according to claim 1, at least one of the reference value of the detected current and the delay time is set to a power supply voltage such that the load power is constant with respect to fluctuations in the power supply voltage. A chopper device characterized in that it is variable according to.