JPS62151742U - - Google Patents
Info
- Publication number
- JPS62151742U JPS62151742U JP1986038254U JP3825486U JPS62151742U JP S62151742 U JPS62151742 U JP S62151742U JP 1986038254 U JP1986038254 U JP 1986038254U JP 3825486 U JP3825486 U JP 3825486U JP S62151742 U JPS62151742 U JP S62151742U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- board
- sub
- chip
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims 2
- 238000004070 electrodeposition Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986038254U JPS62151742U (US20030204162A1-20031030-M00001.png) | 1986-03-18 | 1986-03-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986038254U JPS62151742U (US20030204162A1-20031030-M00001.png) | 1986-03-18 | 1986-03-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62151742U true JPS62151742U (US20030204162A1-20031030-M00001.png) | 1987-09-26 |
Family
ID=30850329
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986038254U Pending JPS62151742U (US20030204162A1-20031030-M00001.png) | 1986-03-18 | 1986-03-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62151742U (US20030204162A1-20031030-M00001.png) |
-
1986
- 1986-03-18 JP JP1986038254U patent/JPS62151742U/ja active Pending