JPS62151273U - - Google Patents
Info
- Publication number
- JPS62151273U JPS62151273U JP1986037968U JP3796886U JPS62151273U JP S62151273 U JPS62151273 U JP S62151273U JP 1986037968 U JP1986037968 U JP 1986037968U JP 3796886 U JP3796886 U JP 3796886U JP S62151273 U JPS62151273 U JP S62151273U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- graphic signal
- utility
- video camera
- display mechanism
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 102100029968 Calreticulin Human genes 0.000 claims description 4
- 101100326671 Homo sapiens CALR gene Proteins 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 2
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第１図はこの考案の一実施例を示すブロツク回
路図、第２図はＣＲＴへの音声レベルの表示図、
第３図は、ピークホールドの表示の例を示す説明
図である。
図中、１０……Ａ／Ｄ変換手段、１１……実効
値整流回路、１２……Ａ／Ｄ変換器、２０……グ
ラフイツク信号発生手段、２１……マイクロコン
ピユータ、２２……ＣＲＴＣ、３０……ミツクス
回路、４０……ビユーフアインダ。
Fig. 1 is a block circuit diagram showing an embodiment of this invention, Fig. 2 is a diagram showing the audio level displayed on a CRT,
FIG. 3 is an explanatory diagram showing an example of peak hold display. In the figure, 10... A/D conversion means, 11... Effective value rectification circuit, 12... A/D converter, 20... Graphic signal generation means, 21... Microcomputer, 22... CRTC, 30... ...mix circuit, 40...view finder.
Claims (1)
変換するためのＡ／Ｄ変換手段と、 上記Ａ／Ｄ変換手段の出力に基づいて入力信号
の大きさに応じたグラフイツク信号を発生するた
めのグラフイツク信号発生手段と、 上記グラフイツク信号発生手段の出力と映像信
号とをミツクスして電子ビユーフアインダに入力
するためのミツクス回路と、 よりなるビデオカメラに於ける音声レベル表示機
構。 (2) Ａ／Ｄ変換手段がアナログの音声入力信号
を整流する実効値整流回路と、該実効値整流回路
の出力をデジタル変換し、又、必要に応じてピー
ク値をサンプリングホールドする機能を有するＡ
／Ｄ変換器とよりなる実用新案登録請求の範囲第
(1)項記載のビデオカメラに於ける音声レベル表
示機構。 (3) グラフイツク信号発生手段が、入力に応じ
て下記ＣＲＴＣを制御するマイクロコンピユータ
と、 上記マイクロコンピユータの指示に従つて入力
レベルに応じたキヤラクタを表示するためのグラ
フイツク信号を出力するＣＲＴＣとよりなる実用
新案登録請求の範囲第(1)項記載のビデオカメラ
に於ける音声レベル表示機構。[Claims for Utility Model Registration] (1) A/D conversion means for converting an analog audio input signal into a digital signal; An audio level display mechanism in a video camera comprising: a graphic signal generating means for generating a graphic signal; a mix circuit for mixing the output of the graphic signal generating means and a video signal and inputting the mixture to an electronic viewfinder; . (2) The A/D conversion means has an effective value rectifying circuit that rectifies the analog audio input signal, converts the output of the effective value rectifying circuit into digital, and has a function of sampling and holding peak values as necessary. A
Scope of claim for registration of utility model consisting of /D converter No.
An audio level display mechanism in the video camera described in (1). (3) The graphic signal generation means consists of a microcomputer that controls the following CRTC according to input, and a CRTC that outputs a graphic signal for displaying a character according to the input level according to instructions from the microcomputer. An audio level display mechanism in a video camera as set forth in claim (1) of the utility model registration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986037968U JPH055726Y2 (en) | 1986-03-14 | 1986-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986037968U JPH055726Y2 (en) | 1986-03-14 | 1986-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62151273U true JPS62151273U (en) | 1987-09-25 |
| JPH055726Y2 JPH055726Y2 (en) | 1993-02-15 |
Family
ID=30849773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986037968U Expired - Lifetime JPH055726Y2 (en) | 1986-03-14 | 1986-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH055726Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57159178A (en) * | 1981-03-26 | 1982-10-01 | Hitachi Denshi Ltd | Level indicator circuit |
-
1986
- 1986-03-14 JP JP1986037968U patent/JPH055726Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57159178A (en) * | 1981-03-26 | 1982-10-01 | Hitachi Denshi Ltd | Level indicator circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH055726Y2 (en) | 1993-02-15 |
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