JPS6214983U - - Google Patents
Info
- Publication number
- JPS6214983U JPS6214983U JP10440385U JP10440385U JPS6214983U JP S6214983 U JPS6214983 U JP S6214983U JP 10440385 U JP10440385 U JP 10440385U JP 10440385 U JP10440385 U JP 10440385U JP S6214983 U JPS6214983 U JP S6214983U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- semiconductor switch
- inrush current
- load
- rectifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
Description
第１図はこの考案の一実施例を示す回路図、第
２図はこの考案の他の実施例を示す回路図、第３
図は従来の装置を示す回路図である。
図中、Ｆ０は電源ヒユーズ、ＳＷ０は電源スイ
ツチ、Ｒ０は突入電流制限用抵抗、ＳＷ１はリレ
ースイツチ、Ｄ０は整流回路、Ｃ０は平滑用コン
デンサ、ＡＶは定電圧装置、ＲＬは負荷、ＤＣは
遅延回路、ＳＳＳは双方向性サイリスタ、ＳＣＲ
は逆阻止サイリスタ、Ｄ２はサージ用ダイオード
である。なお、同一符号は夫々相当部分を示す。
Figure 1 is a circuit diagram showing one embodiment of this invention, Figure 2 is a circuit diagram showing another embodiment of this invention, and Figure 3 is a circuit diagram showing another embodiment of this invention.
The figure is a circuit diagram showing a conventional device. In the figure, F 0 is the power fuse, SW 0 is the power switch, R 0 is the inrush current limiting resistor, SW 1 is the relay switch, D 0 is the rectifier circuit, C 0 is the smoothing capacitor, AV is the voltage regulator, RL is the load, DC is the delay circuit, SSS is the bidirectional thyristor, SCR
is a reverse blocking thyristor, and D2 is a surge diode. Note that the same reference numerals indicate corresponding parts.
Claims (1)
整流出力を平滑して負荷に供給するようにしたも
のにおいて、上記整流回路の入力側に接続された
突入電流制限用の抵抗及び上記抵抗と並列関係に
接続された半導体スイツチ並びに上記抵抗より電
源側に接続され、上記負荷への整流出力供給後、
所定時限を経過した時、上記半導体スイツチを導
通させて上記抵抗を短絡する遅延回路を備えた突
入電流制限装置。 (2) 半導体スイツチは双方向性サイリスタ又は
逆阻止サイリスタであることを特徴とする実用新
案登録請求の範囲第１項記載の突入電流制限装置
。[Claims for Utility Model Registration] (1) In a device that has a rectifier circuit that rectifies alternating current voltage and whose rectified output is smoothed and supplied to a load, an inrush current connected to the input side of the rectifier circuit. A limiting resistor, a semiconductor switch connected in parallel with the resistor, and a semiconductor switch connected to the power supply side from the resistor, after supplying rectified output to the load,
An inrush current limiting device comprising a delay circuit that makes the semiconductor switch conductive and short-circuits the resistor when a predetermined time period has elapsed. (2) The inrush current limiting device according to claim 1, wherein the semiconductor switch is a bidirectional thyristor or a reverse blocking thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10440385U JPS6214983U (en) | 1985-07-08 | 1985-07-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10440385U JPS6214983U (en) | 1985-07-08 | 1985-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214983U true JPS6214983U (en) | 1987-01-29 |
Family
ID=30977864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10440385U Pending JPS6214983U (en) | 1985-07-08 | 1985-07-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214983U (en) |
-
1985
- 1985-07-08 JP JP10440385U patent/JPS6214983U/ja active Pending
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