JPS6214971B2 - - Google Patents

Info

Publication number
JPS6214971B2
JPS6214971B2 JP53147640A JP14764078A JPS6214971B2 JP S6214971 B2 JPS6214971 B2 JP S6214971B2 JP 53147640 A JP53147640 A JP 53147640A JP 14764078 A JP14764078 A JP 14764078A JP S6214971 B2 JPS6214971 B2 JP S6214971B2
Authority
JP
Japan
Prior art keywords
signal
voltage
intermittent
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53147640A
Other languages
Japanese (ja)
Other versions
JPS5574246A (en
Inventor
Muneo Suzuki
Hitoshi Ikeda
Takeyoshi Kawamura
Yoshiharu Suzuki
Kazuhiko Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP14764078A priority Critical patent/JPS5574246A/en
Publication of JPS5574246A publication Critical patent/JPS5574246A/en
Publication of JPS6214971B2 publication Critical patent/JPS6214971B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/54Systems for transmission via power distribution lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/5416Methods of transmitting or receiving signals via power distribution lines by adding signals to the wave form of the power source
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5429Applications for powerline communications
    • H04B2203/5458Monitor sensor; Alarm systems

Description

【発明の詳細な説明】 本発明は、遠隔に設けた親器と子器間の電力お
よび信号の伝送を2線で行う信号伝送システムに
関するものであり、その目的とするところは、親
器の非常用電源が子器への給電回路を簡単な回路
で形成でき、親器のコスト低減化および小型化が
図れる信号伝送システムを提供することにある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission system that transmits power and signals between a remotely located parent device and a slave device using two wires. It is an object of the present invention to provide a signal transmission system in which an emergency power source can form a power supply circuit to a child device with a simple circuit, and the cost and size of the parent device can be reduced.

従来の信号搬送方式は、商用周波電源電圧に信
号を重畳させるものであり、警戒器を構成する親
器と子器との間に適用する場合、停電、断線など
の際に使用できなくならないように、非常用電
源、即ちバツテリなどの直流電源に切換えて機能
を維持するように構成しているが、直流電圧に切
換えられても信号を2本の線路で電力とともに伝
送する場合、非常用電源から出力される直流電圧
を商用周波電源電圧と等価な交流電圧に変換する
インバータ回路が必要になり、親器の非常用電源
からの子器への給電回路が複雑になつて、親器の
コストが高くなるとともに、大型化するという問
題があつた。
The conventional signal transmission method superimposes a signal on the commercial frequency power supply voltage, and when applied between the main unit and slave unit that make up a warning device, it is necessary to prevent the system from becoming unusable in the event of a power outage or disconnection. In most cases, the system is configured to maintain functionality by switching to an emergency power source, i.e., a DC power source such as a battery. An inverter circuit is required to convert the DC voltage output from the main unit into an AC voltage equivalent to the commercial frequency power supply voltage, and the power supply circuit from the main unit's emergency power supply to the slave unit becomes complicated, which increases the cost of the main unit. There was a problem in that as the price became higher, the size became larger.

本発明はかかる点に鑑みてなされたもので、以
下実施例により詳細に説明する。
The present invention has been made in view of this point, and will be explained in detail below with reference to Examples.

第1図において、1は親器、2は子器でこれら
を2本の線路3で接続し、この2本の線路3によ
つて親器1から子器2へ電力を供給するととも
に、親器1、子器2間の信号伝送路とするもので
ある。4は交流電源で、この電圧をトランス5で
降圧し、整流回路6で整流して定電圧回路7に接
続する。バツテリよりなる非常用電源8は非停電
時においてはダイオードD1を介してフロート充
電され、停電時にはダイオードD2を介して放電
されるようになつている。定電圧回路7はトラン
ジスタTr1,Tr2によつて構成され、トランジス
タTr2のベース;アース間にトランジスタTr3
接続し、このトランジスタTr3のベースに一定周
期の継続波を加える。この継続波によつてトラン
ジスタTr3がオンしているときのみ定電圧回路7
は作動し、直流電圧を断続して子器2へ伝送す
る。この断続波はCPU9のCoφから出力され
る。子器2でこの断続波を第3図のようなタイミ
ングパルス取込み回路10によつて子器2の
CPU11に取込み、親器1と子器2との間で行
なわれる信号伝送の同期をとるようにしている。
In Fig. 1, 1 is a master unit, 2 is a slave unit, and these are connected by two lines 3, and these two lines 3 supply power from the master unit 1 to the slave unit 2, and This is used as a signal transmission path between the device 1 and slave device 2. Reference numeral 4 denotes an AC power supply, and this voltage is stepped down by a transformer 5, rectified by a rectifier circuit 6, and connected to a constant voltage circuit 7. The emergency power source 8 consisting of a battery is float-charged via a diode D 1 during non-power outages, and discharged via a diode D 2 during power outages. The constant voltage circuit 7 is constituted by transistors Tr 1 and Tr 2. A transistor Tr 3 is connected between the base of the transistor Tr 2 and ground, and a continuous wave of a constant period is applied to the base of the transistor Tr 3 . Only when the transistor Tr 3 is on due to this continuous wave, the constant voltage circuit 7
is activated and transmits DC voltage intermittently to slave unit 2. This intermittent wave is output from Coφ of the CPU 9. This intermittent wave is transmitted to the slave unit 2 by the timing pulse acquisition circuit 10 as shown in FIG.
The CPU 11 imports the signal and synchronizes the signal transmission between the master device 1 and the slave device 2.

直流断続電圧は上記のように親器1から子器2
へ伝送され、この直流断続電圧には親器1から子
器2へ、又は子器2から親器1へ直流断続電圧に
同期して伝送される信号が重畳される。このと
き、スタート信号S0を第4図のように直流断続電
圧に重畳させ、これを子器2で受けて信号が送ら
れてくることを知る。このスタート信号S0につづ
く直流断続電圧を順次第1チヤンネル、第2チヤ
ンネル……第Nチヤンネルと定め、各チヤンネル
信号S1,S2……SNを重畳させる。信号S1,S2
…SNの周波数はそれぞれ異なつてもよく、同一
の周波数であつてもよい。同一の周波数の場合、
あらかじめ第1チヤンネルはベルを鳴動せよと
か、第2チヤンネルはランプを点灯せよという信
号などを定めておけばよい、又、第1チヤンネル
は子器2から親器1へ、第2チヤンネルは親器1
からの子器2へ信号を送るチヤンネルであると定
めておくことも可能である。
The intermittent DC voltage is applied from the main unit 1 to the slave unit 2 as described above.
A signal transmitted from the parent device 1 to the child device 2 or from the child device 2 to the parent device 1 in synchronization with the DC intermittent voltage is superimposed on this DC intermittent voltage. At this time, the start signal S 0 is superimposed on the DC intermittent voltage as shown in FIG. 4, and this is received by the slave device 2, so that the signal is sent. The DC intermittent voltages following this start signal S 0 are sequentially defined as the first channel, the second channel, . . . the Nth channel, and the channel signals S 1 , S 2 , . Signals S 1 , S 2
...The frequencies of S N may be different or may be the same frequency. For the same frequency,
It is sufficient to predetermine signals such as ringing a bell for the first channel and lighting a lamp for the second channel. Also, the first channel is sent from slave unit 2 to master unit 1, and the second channel is sent from slave unit 2 to master unit 1. 1
It is also possible to specify that this is a channel for sending signals from the terminal to the child device 2.

信号伝送を多くするために、2つの異なる周波
数f1,f2を第5図又は第6図のように組合せて重
畳することもできる。例えば、第6図のように、
直流断続電圧を4等分し、この間に重畳する信号
の周波数をf1,f2,f1,f2のようにし、f1を0、f2
を1とすると、0101という信号となつて4ビツト
の信号にできる。したがつて、第5図のように、
スタート信号S0をf1,f2,f1,f2(0101)とし、そ
の後に、f1,f1,f2,f2(0011)、f2,f2,f1,f1
(1100)、f2,f1,f2,f1(1010)、f1,f1,f1,f2
(0001)などと14種類の信号をつくることができ
る。
In order to increase signal transmission, two different frequencies f 1 and f 2 can also be combined and superimposed as shown in FIG. 5 or FIG. 6. For example, as shown in Figure 6,
Divide the DC intermittent voltage into four equal parts, and set the frequencies of the signals superimposed between them as f 1 , f 2 , f 1 , f 2 , where f 1 is 0 and f 2
When is set to 1, the signal becomes 0101, which is a 4-bit signal. Therefore, as shown in Figure 5,
The start signal S 0 is f 1 , f 2 , f 1 , f 2 (0101), and then f 1 , f 1 , f 2 , f 2 (0011), f 2 , f 2 , f 1 , f 1
(1100), f 2 , f 1 , f 2 , f 1 (1010), f 1 , f 1 , f 1 , f 2
It is possible to create 14 types of signals such as (0001).

この信号は、第1図の制御信号発生部12の発
振回路13又は14で得られる。今、発振回路1
3の発振器OSC1が298kHz(f2)で発振し、発振
器OSO2が256kHz(f1)で発振するとし、CPU9
5出力はf1とf2の切換信号を出し、この5
出力と発振器OSC1,OSC2の出力を2個のNAND
ゲートNAND1,NAND2と1個のNORゲート
NOR1で組合せ、NORゲートNOR1の出力と信号
送出命令信号6の出力とをNANDゲートNAND3
に加えて信号を送信回路15に入力し、結合回路
16によつて直流断続電圧に重畳して子器2へ送
る。この動作を図示すれば第7図のようになる。
このようにして送られた信号は、子器2の結合回
路17を介して受信回路18で受信され、CPU
11を介して負荷駆動回路19を動作させて負荷
20を制御する。このとき、子器2には、直流断
続電圧を整流回路21にて整流するとともに定電
圧回路22にて定電圧化した直流電圧が供給され
る。子器2から信号を伝送する場合には、センサ
ー、スイツチなどの検知信号発生部23の出力に
よりCPU11を動作させ、親器1と同様に制御
信号発生部24で信号を発生して送信回路25に
入力し、結合回路17によつて直流断続電圧に重
畳して親器1へ伝送し、親器1の受信回路26で
受信して負荷駆動回路27を介して負荷28を制
御する。29は親器の検知信号発生部である。
This signal is obtained by the oscillation circuit 13 or 14 of the control signal generator 12 shown in FIG. Now, oscillation circuit 1
Assume that the oscillator OSC 1 of 3 oscillates at 298kHz (f 2 ), and the oscillator OSO 2 oscillates at 256kHz (f 1 ), and the CPU 9
The 5 outputs output f 1 and f 2 switching signals, and the outputs of 5 and the outputs of the oscillators OSC 1 and OSC 2 are connected to two NAND
Gates NAND 1 , NAND 2 and one NOR gate
NOR 1 combines the output of NOR gate NOR 1 and the output of signal sending command signal 6 to NAND gate NAND 3
In addition to this, the signal is input to the transmitting circuit 15, superimposed on the DC intermittent voltage by the coupling circuit 16, and sent to the child device 2. This operation is illustrated in FIG. 7.
The signal sent in this way is received by the receiving circuit 18 via the coupling circuit 17 of the slave unit 2, and the CPU
The load drive circuit 19 is operated via the load drive circuit 11 to control the load 20. At this time, the slave unit 2 is supplied with a DC voltage obtained by rectifying the intermittent DC voltage in the rectifier circuit 21 and making it constant in the constant voltage circuit 22 . When transmitting a signal from the slave device 2, the CPU 11 is operated by the output of the detection signal generator 23 such as a sensor or switch, and the control signal generator 24 generates a signal in the same way as the parent device 1, and the signal is sent to the transmitter circuit 25. The signal is input to the main unit 1, superimposed on the intermittent DC voltage by the coupling circuit 17, and transmitted to the main unit 1, received by the receiving circuit 26 of the main unit 1, and controlled by the load 28 via the load drive circuit 27. Reference numeral 29 is a detection signal generating section of the parent device.

第8図は、親器1の検知信号発生部29、負荷
駆動回路27の具体回路を示すもので、CPU9
のAポートに解錠押釦スイツチ30、非常押釦ス
イツチ31、警戒セツトリセツトスイツチ32等
を接続し、スキヤン出力7の信号によつてトラ
ンジスタTr4を駆動し、そのときの各入力端A0
A3の電位が“L”か“H”かをチエツクするよ
うにしている。CPU9のBポート入力には、シ
ークレツト番号設定スイツチ33が接続されてお
り、スキヤン出力C01〜C04の信号によりBポート
B0〜B8の入力が“L”か“H”かのチエツクが
される。出力CポートCo8〜Co11は報知音発生回
路34が接続され、Co8ならピンポン、Co9なら
ポロロン、Co10ならブーというように音質が異な
る出力が得られるようにしている。出力Eポート
は、Eoφがインターホン/報知器切換信号出
力、Eo1が開戸表示灯点灯出力、Eo2が解錠表示
灯点灯出力、Eo3は警戒表示灯点灯出力がそれぞ
れ出力される。
FIG. 8 shows the specific circuits of the detection signal generation section 29 and the load drive circuit 27 of the main device 1, and the CPU 9
An unlock push button switch 30, an emergency push button switch 31, a warning reset switch 32, etc. are connected to the A port of the switch, and the transistor Tr 4 is driven by the signal of the scan output 7 , and each input terminal A 0 to
It checks whether the potential of A3 is "L" or "H". A secret number setting switch 33 is connected to the B port input of the CPU 9, and the B port is controlled by the scan output signals C 01 to C 04 .
It is checked whether the inputs of B0 to B8 are "L" or "H". The output C ports Co 8 to Co 11 are connected to the notification sound generation circuit 34, so that outputs with different sound qualities can be obtained, such as ping-pong for Co 8 , poro-ron for Co 9 , and boom for Co 10 . For the output E ports, Eoφ outputs an intercom/alarm switching signal, Eo 1 outputs an open door indicator light output, Eo 2 outputs an unlock indicator light output, and Eo 3 outputs a warning indicator light output.

第9図は子器2の具体回路で、CPU11のB
入力ポートには解錠検知スイツチ35、開戸検知
スイツチ36が接続され、スキヤン出力7の出
力があつたときBi1,Bi2の電位が“L”か“H”
でチエツクされる。A入力ポートにはシークレツ
トスイツチ37、警戒リセツトスイツチ38、解
錠押釦スイツチ39が接続され、出力Cポートの
出力があつたときのA入力ポートの電位が“L”
か“H”かでチエツクされる。出力DポートDo
φには電気錠駆動回路40が接続されて電気錠4
1を制御するようにし、出力EポートEo3には警
戒表示灯点灯回路42が接続されている。43は
インターホン子機である。
Figure 9 shows the specific circuit of slave device 2, and the B of CPU 11.
An unlock detection switch 35 and an open door detection switch 36 are connected to the input port, and when the scan output 7 is output, the potentials of Bi 1 and Bi 2 are “L” or “H”.
will be checked. A secret switch 37, a warning reset switch 38, and an unlock push button switch 39 are connected to the A input port, and the potential of the A input port is "L" when the output of the output C port is applied.
or “H”. Output D port Do
An electric lock drive circuit 40 is connected to φ, and the electric lock 4
1, and a warning indicator light lighting circuit 42 is connected to the output E port Eo 3 . 43 is an intercom slave unit.

今、子器2のインターホン呼出し押釦が押され
た場合について説明する。CPU11の内部プロ
グラムによつて出されたタイミングでスキヤン出
7が出て入力ポートBiがローレベルであるこ
とをCPU11にとり込む。CPU11ではこの入
力が呼出し信号であることを判別してスタート信
号および子器2から親器1へのチヤンネルのタイ
ミングで呼出し信号を制御信号発生部24で形成
し、結合回路17を介して線路3により伝送す
る。親器1は結合回路16より伝送された信号を
とり込み、受信回路26で受信してCPU9の
SNSI入力に入力する。CPU9はこの入力された
信号をカウンタでカウントして呼出し信号である
ことを判別し、呼出し信号出力Co8を出力し、報
知音発生回路34が作動し、報知器44からピン
ポンという音が出る。そこで、家人がインターホ
ン親器45で子器2側へ話をすることにより確認
して解錠押釦スイチ30を閉じる。CPU9のス
キヤン出力7のタイミングで、解錠信号がA3
とり込まれ、CPU9はこの解錠信号と、すでに
子器2から送られてRAMに記憶されている解錠
検知入力信号、開戸検知入力信号によるドアの状
態とを合せて解錠する必要のある場合は解錠命令
信号を子器2へ送る。この解錠命令信号は、第3
チヤンネルに重畳して子器2へ送られる。それと
同時に親器1では表示信号ブー音が報知器44か
ら出る。一方、インターホンから報知音に切換え
られているため、インターホン回路l1,l2を介し
てインターホン子機43のスピーカから同時にブ
ーという音が出る。子器2は解錠命令信号を受け
てCPU11でこれを判別し、解錠信号出力Doφ
を出力し、電気錠駆動回路40を動作させて電気
錠41を駆動させて解錠する。そして、解錠検知
スイツチ35が作動し、CPU11のスキヤン出
力でそれがとり込まれ、一方チヤンネルを
介して親器1に解錠されたことを示す信号が送ら
れ、これを受けて親器1は解錠表示出力Eo2を出
力し、表示灯46が点灯する。ついで、子器2側
で客人がドアを開くと、開戸検出スイツチ36が
作動し、CPU11のスキヤン出力7のタイミン
グで開戸したことを示す信号がB入力ポートBi1
にとり込まれ、そろことを示す信号を子器2から
親器1へ送る。親器1はこの信号を受けて開戸し
たことを判定し、開戸信号出力Co9、切換信号出
力Eoφを出力し、親器1、子器2共にポロロン
という音が出る。そして、開戸表示出力Eo1が出
力されるので、開戸表示灯が点灯する。ドアを閉
じると開戸表示灯は消灯する。
Now, a case where the intercom call push button of slave device 2 is pressed will be explained. A scan output 7 is output at the timing issued by the internal program of the CPU 11, and the CPU 11 receives the information that the input port Bi is at a low level. The CPU 11 determines that this input is a calling signal, and generates a calling signal in the control signal generator 24 at the timing of the start signal and the channel from the child device 2 to the parent device 1, and sends it to the line 3 via the coupling circuit 17. Transmitted by The master device 1 takes in the signal transmitted from the coupling circuit 16, receives it in the receiving circuit 26, and sends it to the CPU 9.
Enter into SNSI input. The CPU 9 counts this input signal with a counter, determines that it is a calling signal, outputs a calling signal output Co 8 , activates the notification sound generation circuit 34, and makes a ping-pong sound from the notification device 44. Therefore, the family member speaks to the slave device 2 side using the intercom master device 45 to confirm and closes the unlock push button switch 30. At the timing of the scan output 7 of the CPU 9, the unlock signal is taken into A 3 , and the CPU 9 receives this unlock signal, the unlock detection input signal already sent from the slave device 2 and stored in the RAM, and the open door detection signal. If it is necessary to unlock the door based on the input signal, an unlock command signal is sent to the child unit 2. This unlock command signal is the third
It is superimposed on the channel and sent to slave device 2. At the same time, a display signal buzzer is emitted from the annunciator 44 in the parent unit 1. On the other hand, since the intercom has been switched to the notification sound, a buzzing sound is simultaneously emitted from the speakers of the intercom handset 43 via the intercom circuits l 1 and l 2 . The slave unit 2 receives the unlocking command signal, determines it with the CPU 11, and outputs the unlocking signal Doφ.
is output, and the electric lock driving circuit 40 is operated to drive the electric lock 41 to unlock it. Then, the unlock detection switch 35 is activated, and the scan output of the CPU 11 captures this, and on the other hand, a signal indicating that the lock has been unlocked is sent to the master device 1 via the channel, and in response to this, the master device 1 outputs the unlocking display output Eo 2 , and the indicator light 46 lights up. Next, when the guest opens the door on the slave unit 2 side, the open door detection switch 36 is activated, and a signal indicating that the door has been opened is sent to the B input port Bi 1 at the timing of the scan output 7 of the CPU 11.
The slave device 2 sends a signal to the master device 1 indicating that it is ready. The main device 1 receives this signal and determines that the door has been opened, and outputs an open door signal output Co 9 and a switching signal output Eoφ, and both the main device 1 and the slave device 2 make a clicking sound. Then, since the door opening display output Eo 1 is output, the door opening indicator light turns on. When the door is closed, the door indicator light goes out.

つぎに、家人が帰宅した場合を説明する。家人
は子器2のシークレツトスイツチ37を所定の数
字を所定の順序で作動させると、CPU11のス
キヤン出力Co1,Co2,Co3で入力ポートAi0
Ai1,Ai2,Ai3の信号がとり込まれ、順次CPU1
1のRAMに記憶され、これがCPU11から第2
チヤンネルに、シークレツトスイツチ37の入力
をコード化して親器1側へ送る。親器1のCPU
9はこの信号と、シークレツト番号設定スイツチ
33の入力B0〜B3とを比較して一致していいか
どうかを判定する。一致しておけば、CPU9は
子器2に対して解錠命令信号を第3チヤンネルに
重畳して送るとともに解錠信号出力Co10、切換出
力Eoφを出力し、ブー音が親器1、子器2とも
出る。家人がドアを開けると、開戸検知スイツチ
36が作動して子器2より親器1へ信号を送り、
CPU9がこれを受けて開戸表示出力Eo1を出力
し、切換信号出力Eoφを出力して親器1、子器
2共ポロロン音が発生する。ドアを閉じると、開
戸検知スイツチ36の信号が反転し、親器1に送
られてきた信号によつて開戸表示信号Eo1がなく
なり、開戸表示灯は消灯する。そこで、親器1で
警戒セツトリセツトスイツチ32をオンにすると
警報状態に戻る。
Next, we will explain what happens when a family member returns home. When the householder activates the secret switch 37 of the slave device 2 with a predetermined number in a predetermined order, the scan outputs Co 1 , Co 2 , Co 3 of the CPU 11 are input to the input ports Ai 0 ,
The signals of Ai 1 , Ai 2 , and Ai 3 are taken in and sent to CPU1 in sequence.
1 RAM, and this is stored in the 2nd RAM from the CPU 11.
The input of the secret switch 37 is encoded on the channel and sent to the master unit 1 side. CPU of main unit 1
9 compares this signal with the inputs B 0 to B 3 of the secret number setting switch 33 to determine whether they match. If they match, the CPU 9 sends an unlock command signal to the slave device 2 by superimposing it on the third channel, and also outputs an unlock signal output Co 10 and a switching output Eoφ, and the buzzing sound is output from the master device 1 and slave device 1. Both vessels 2 come out. When a household member opens the door, the open door detection switch 36 is activated and sends a signal from the child device 2 to the parent device 1.
In response to this, the CPU 9 outputs an open door display output Eo 1 and a switching signal output Eoφ, so that both the master unit 1 and slave unit 2 generate a popping sound. When the door is closed, the signal of the open door detection switch 36 is inverted, the open door display signal Eo 1 disappears due to the signal sent to the main unit 1, and the open door indicator light is turned off. Therefore, when the warning reset switch 32 is turned on in the main device 1, the alarm state is returned.

上述のように、きわめて多数の信号を親器1、
子器2間で2線の線路により伝送できるが、これ
は親器1、子器2にそれぞれCPU9,11を使
用し、それぞれの信号をコード化し、しかも所定
のチヤンネルで伝送し、伝送された信号をCPU
9,10で判別して処理することによりできるも
のである。
As mentioned above, a very large number of signals are transmitted to the parent device 1,
Transmission is possible between slave unit 2 using a two-wire line, but this uses CPUs 9 and 11 for master unit 1 and slave unit 2, respectively, and encodes each signal and transmits it on a predetermined channel. signal to cpu
This can be done by determining and processing the numbers 9 and 10.

本発明は上述のように、遠隔に設けた親器と子
器との間を2本の線路で接続し、フロート充電さ
れる非常用電源を具備した親器から直流電圧を所
定の周期で断続させた直流断続電圧により電力を
子器に伝送するとともに前記直流断続電圧に断続
電圧の周期と異なる周波数の信号を重畳させて伝
送し、スタート信号を重畳させた直流断続電圧の
後につづく直流断続電圧に所定の信号を重畳させ
て伝送するとともに、子器にて直流断続電圧に同
期して重畳された信号を受信するようにしたもの
であり、親器から子器に給電する電圧を非常用電
源から出力される直流電圧を所定の周期で断続し
た直流断続電圧としているので、この直流断続電
圧を同期信号として親器と子器との間で信号伝送
を行うことができ、しかも、交流電圧を伝送する
場合に比べて親器の非常用電源から子器への給電
回路を大幅に簡略化することができ、コストの低
減化および小型化が容易にできるという効果があ
る。つまり、親器の非常用電源から出力される直
流電圧をそのまま子器に給電した場合には、信号
伝送時における同期をとることができなくなり、
一方、非常用電源から出力される直流電圧を交流
電圧に変換して子器に給電した場合には、インバ
ータ回路を必要とし親器の回路構成が複雑になつ
てコストが高くなるとともに大型化してしまうと
いう問題があるが、本発明にあつては、親器から
子器に直流断続電圧を給電することにより、親器
と子器との間で同期をとつて信号の伝送ができる
ようにするとともに、親器の非常用電源から子器
への給電回路を簡単なスイツチ回路(非停電時の
給電回路と同一回路)にて形成できるようにし、
親器の低コスト化および小型化ができるようにし
たものである。
As described above, the present invention connects a remotely located parent unit and slave unit with two lines, and supplies DC voltage intermittently at a predetermined cycle from the parent unit equipped with an emergency power supply that is float-charged. The intermittent DC voltage is used to transmit power to the slave device, and the intermittent DC voltage is transmitted by superimposing a signal with a frequency different from the cycle of the intermittent voltage, and the intermittent DC voltage that continues after the intermittent DC voltage on which the start signal is superimposed is transmitted. A predetermined signal is superimposed on the DC voltage and transmitted, and the slave unit receives the superimposed signal in synchronization with the DC intermittent voltage, and the voltage supplied from the parent unit to the slave unit is used as an emergency power source. Since the DC voltage outputted from the DC voltage is intermittent at a predetermined period, this intermittent DC voltage can be used as a synchronization signal to transmit signals between the parent device and the slave devices. Compared to the case of transmission, the power supply circuit from the emergency power source of the parent unit to the slave units can be significantly simplified, and there is an effect that cost reduction and miniaturization can be easily achieved. In other words, if the DC voltage output from the emergency power source of the parent unit is directly supplied to the slave unit, synchronization during signal transmission will not be possible.
On the other hand, when converting the DC voltage output from the emergency power supply to AC voltage and powering the slave unit, an inverter circuit is required, which complicates the circuit configuration of the master unit, increasing costs and increasing the size. However, in the present invention, by supplying DC intermittent voltage from the parent unit to the slave unit, it is possible to synchronize and transmit signals between the master unit and the slave unit. At the same time, the power supply circuit from the emergency power source of the parent device to the child device can be formed with a simple switch circuit (the same circuit as the power supply circuit during non-power outages).
This makes it possible to reduce the cost and size of the parent device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明信号伝送方式の一実施例のブロ
ツク回路図、第2図は同上の親器の要部回路図、
第3図は同上の子器の要部回路図、第4図は同上
の伝送信号の一例の波形図、第5図は同上の伝送
信号の他の例の波形図、第6図は同上の拡大波形
図、第7図a〜iは同上の要部信号波形図、第8
図は本発明を警戒装置に使用したときの親器の回
路図、第9図は同上の子器の回路図である。 1……親器、2……子器、3……線路、9……
CPU、11……CPU、12……制御信号発生
部、16……結合回路、17……結合回路、24
……制御信号発生部、30……電気錠解押釦スイ
ツチ、32……警戒セツトリセツトスイツチ、3
4……報知音発生回路、35……解錠検知スイツ
チ、36……開戸検知スイツチ、37……シーク
レツトスイツチ、41……電気錠、42……イン
ターホン子機、45……インターホン親機、46
……表示手段。
Fig. 1 is a block circuit diagram of an embodiment of the signal transmission system of the present invention, Fig. 2 is a circuit diagram of the main part of the same parent device,
Figure 3 is a circuit diagram of the main part of the same slave unit as above, Figure 4 is a waveform diagram of an example of the transmission signal as above, Figure 5 is a waveform diagram of another example of the transmission signal as above, and Figure 6 is as above. Enlarged waveform diagram, Figures 7 a to i are the same main signal waveform diagrams as above, Figure 8
The figure is a circuit diagram of a master device when the present invention is used in a warning device, and FIG. 9 is a circuit diagram of a slave device. 1...Main device, 2...Slave device, 3...Railway, 9...
CPU, 11...CPU, 12...Control signal generation section, 16...Coupling circuit, 17...Coupling circuit, 24
... Control signal generation section, 30 ... Electric lock release push button switch, 32 ... Warning reset switch, 3
4...Notification sound generation circuit, 35...Unlock detection switch, 36...Open door detection switch, 37...Secret switch, 41...Electric lock, 42...Intercom slave unit, 45...Intercom base unit , 46
...Display means.

Claims (1)

【特許請求の範囲】 1 遠隔に設けた親器と子器との間を2本の線路
で接続し、フロート充電されるバツテリよりなる
非常用電源を具備した親器から直流電圧を所定の
周期で断続させた直流断続電圧により電力を子器
に伝送するとともに前記直流断続電圧に継続電圧
の周期と異なる周波数の信号を重畳させて伝送
し、スタート信号を重畳させた直流断続電圧の後
につづく直流断続電圧に所定の信号を重畳させて
伝送するとともに、子器にて直流断続電圧に同期
して重畳された信号を受信するようにしたことを
特徴とする信号伝送システム。 2 直流断続電圧に重畳する信号として2種の相
互に異なる周波数の信号を組合せ、前記直流断続
電圧の1つの区間を4等分し、その4等分の間に
前記2種の周波数を重畳させて4ビツトの信号と
して伝送する如くしたことを特徴とする特許請求
の範囲第1項記載の信号伝送システム。 3 スタート信号の後につづく直流断続電圧を第
1チヤンネル、第2チヤンネル……第Nチヤンネ
ルとし、各チヤンネルに異なる周波数の信号を重
畳させる如くしたことを特徴とする特許請求の範
囲第1項記載の信号伝送システム。
[Scope of Claims] 1 A remotely located parent device and a slave device are connected by two lines, and a direct current voltage is applied at a predetermined cycle from the parent device equipped with an emergency power source consisting of a float-charged battery. Electric power is transmitted to the slave device using an intermittent DC voltage that is intermittent at A signal transmission system characterized in that a predetermined signal is superimposed on an intermittent voltage and transmitted, and a slave device receives the superimposed signal in synchronization with the intermittent DC voltage. 2. Combining two types of signals with mutually different frequencies as signals to be superimposed on the intermittent DC voltage, dividing one section of the intermittent DC voltage into four equal parts, and superimposing the two types of frequencies between the four equal parts. 2. The signal transmission system according to claim 1, wherein the signal is transmitted as a 4-bit signal. 3. The intermittent DC voltage that continues after the start signal is the first channel, the second channel, . . . the Nth channel, and signals of different frequencies are superimposed on each channel. Signal transmission system.
JP14764078A 1978-11-29 1978-11-29 Signal delivery system Granted JPS5574246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14764078A JPS5574246A (en) 1978-11-29 1978-11-29 Signal delivery system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14764078A JPS5574246A (en) 1978-11-29 1978-11-29 Signal delivery system

Publications (2)

Publication Number Publication Date
JPS5574246A JPS5574246A (en) 1980-06-04
JPS6214971B2 true JPS6214971B2 (en) 1987-04-04

Family

ID=15434898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14764078A Granted JPS5574246A (en) 1978-11-29 1978-11-29 Signal delivery system

Country Status (1)

Country Link
JP (1) JPS5574246A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115945A (en) * 1981-12-29 1983-07-09 Toyoda Gosei Co Ltd Power transmission and signal transmission and reception method to steering section
JPS58179038A (en) * 1982-04-14 1983-10-20 Matsushita Electric Ind Co Ltd Time division multiplex transmitting system
JPS6050584U (en) * 1983-09-13 1985-04-09 日立化成工業株式会社 2-wire remote control device
JPS61147512A (en) * 1984-12-20 1986-07-05 Tohoku Oki Denki Kk Electromagnet drive system
JPS6221339A (en) * 1985-07-19 1987-01-29 Oki Electric Ind Co Ltd Control signal transmission system
JPS6258172A (en) * 1985-09-06 1987-03-13 Noritsu Co Ltd Method for detecting shortcircuit of signal transmission line
JPH0263227A (en) * 1988-08-29 1990-03-02 Rinnai Corp Communication equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5338917A (en) * 1976-09-22 1978-04-10 Hitachi Ltd Information transmission system
JPS5372411A (en) * 1976-12-09 1978-06-27 Hokuriku Electric Power Co Inc:The Signal transmission system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5338917A (en) * 1976-09-22 1978-04-10 Hitachi Ltd Information transmission system
JPS5372411A (en) * 1976-12-09 1978-06-27 Hokuriku Electric Power Co Inc:The Signal transmission system

Also Published As

Publication number Publication date
JPS5574246A (en) 1980-06-04

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