JPS62149205A - Current conversion circuit - Google Patents

Current conversion circuit

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Publication number
JPS62149205A
JPS62149205A JP60289153A JP28915385A JPS62149205A JP S62149205 A JPS62149205 A JP S62149205A JP 60289153 A JP60289153 A JP 60289153A JP 28915385 A JP28915385 A JP 28915385A JP S62149205 A JPS62149205 A JP S62149205A
Authority
JP
Japan
Prior art keywords
circuit
transistor
junction
current
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60289153A
Other languages
Japanese (ja)
Inventor
Hiroshi Gomi
五味 浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60289153A priority Critical patent/JPS62149205A/en
Publication of JPS62149205A publication Critical patent/JPS62149205A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain the titled circuit with a high gain and to apply the circuit to a switching circuit or a rectangular conversion circuit or the like by providing a coupling circuit and a differential amplifier comprising plural transistors (TR) so as to attain the linear conversion. CONSTITUTION:TRs Qa1, Qa2 and Qb1, Qb2 constitute respectively the coupling circuits and bases of the TRs Qa1, Qb1 are connected to a bias power supply VB1. Further, the differential amplifier consists of TRs Qx, Qy and emitters of TRs Qa2, Qb2 are connected to the base of the TRs Qy, Qx. When a current IPa2 of a terminal Pa2 and a current Isb2 of a constant current source are made unequal to each other, one of the TRs Qx, Qy is conductive and the other is cut off momentarily and the state of currents IPx, IPy is changed over. Since the changeover has a characteristic with a rapid slope in this case, a high gain circuit is attained near the changeover, the circuit is applied to a rectangular wave conversion circuit or a signal discriminating circuit or the like and the linear conversion is attained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は電流変換回路に関し、特に半導体集積回路化(
IC化)が容易で、高利得増幅回路等に用いて適するも
のである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a current conversion circuit, and particularly to a semiconductor integrated circuit (
It is easy to integrate into an IC) and is suitable for use in high gain amplifier circuits and the like.

〔発明の技術的背景〕[Technical background of the invention]

従来の電流変換形の増幅回路の一例を第3図に示す。 An example of a conventional current conversion type amplifier circuit is shown in FIG.

第3図にあって、トランジスタQl、Q2はそれぞれベ
ースに基準バイアス電圧源VBIからの電圧が供給され
、エミッタが差動アンプを構成するトランジスタQ3.
Q4のベースに接続されている。各トランジスタQl、
Q2のコレクタは電圧源Vccに接続され、トランジス
タQ3.Q4のベースには入力端子Pl、P2が接続さ
れており、Q3.Q4のエミッタは共通に接続し、定電
流源Isxを介して基準電位点(アース)に接続されて
いる。そしてトランジスタQ3.Q4のコレクタは出力
端子P3.P4につながっている。
In FIG. 3, transistors Q1, Q2 each have their bases supplied with a voltage from a reference bias voltage source VBI, and emitters of transistors Q3, . . . , which constitute a differential amplifier.
Connected to the base of Q4. Each transistor Ql,
The collector of Q2 is connected to the voltage source Vcc, and the collector of transistor Q3. Input terminals Pl and P2 are connected to the base of Q4, and Q3. The emitters of Q4 are connected in common and connected to a reference potential point (earth) via a constant current source Isx. and transistor Q3. The collector of Q4 is output terminal P3. Connected to P4.

この第3図の回路における入・出力の関係を求めてみる
に9図より次の式が成立する。
When determining the relationship between input and output in the circuit shown in FIG. 3, the following equation holds true from FIG.

VBI−VFI−#F4=VB1−VF2−VF3  
    −・−・ (1)ヨっテVyrx−1−VTP
4=VIPz−1−VF3−・−・(2)(ただしVF
I〜vF4はトランジスタQユ〜Q4のベース・エミッ
タ間電圧である。)トランジスタのベース・エミッタ接
合(ダイオードも含む)は次式で与えられることが周知
である。
VBI-VFI-#F4=VB1-VF2-VF3
-・-・ (1) Yotte Vyrx-1-VTP
4=VIPz−1−VF3−・−・(2) (However, VF
I~vF4 is the base-emitter voltage of the transistors Q~Q4. ) It is well known that the base-emitter junction of a transistor (including a diode) is given by the following equation.

T  In VIP =−t n−・・・・(3) ’It   Is ただしKはボルツマン定数、Tは絶対温度。T In VIP=-tn-・・・(3) 'It Is However, K is Boltzmann's constant and T is the absolute temperature.

古は電子の電荷、Inはトランジスタのエミッタ電流(
実質的にコレクタ電流)、Isはトランジスタの飽和電
流であるう 第3図の回路を半導体基板上に構成するものとすればト
ランジスタQ]〜Q4は実質的に同一特性にすることが
できるから、各トランジスタのI8を等しいとおき、各
トランジスタのエミッタ電流あるいはコレクタ電流を工
1〜I 4゜入・出力端子P1〜P4を流れる電流をI
px〜IP4とすると。
In is the electron charge, and In is the emitter current of the transistor (
(substantially the collector current), Is is the saturation current of the transistor.If the circuit of FIG. 3 is constructed on a semiconductor substrate, the transistors Q] to Q4 can have substantially the same characteristics. By setting I8 of each transistor to be equal, the emitter current or collector current of each transistor is
px~IP4.

11=Ip1.l2=IP2.l3=Ip3.I4:I
F5であり。
11=Ip1. l2=IP2. l3=Ip3. I4:I
It's F5.

(3)式を(2)式に代入すると。Substituting equation (3) into equation (2) yields.

IPI・I P 4=I P 2・IF5      
 ・・・・(4)が成立する。また電流源ISIの′こ
流値は。
IPI・IP4=IP2・IF5
...(4) holds true. Also, the current value of the current source ISI is.

IS]=IP3+IP4         ・・・・(
5)であり、  (4)、  (5)式よりとなる。
IS]=IP3+IP4...(
5), and it follows from equations (4) and (5).

こうして出力端子には入力信号に応答した出力信号が得
られる。
In this way, an output signal responsive to the input signal is obtained at the output terminal.

〔背景技術の問題点〕[Problems with background technology]

前述の(6)式から分ることは、  IPIまたはIF
5を入力信号とするとIF5は線形の出力関数にならず
、電流変換形のメリットはあるものの非線形変換のため
に線形な変換ができない。またその応用性が狭いもので
あった。
What can be seen from the above equation (6) is that IPI or IF
If 5 is used as an input signal, IF5 does not become a linear output function, and although it has the advantage of being a current conversion type, linear conversion cannot be performed due to nonlinear conversion. Moreover, its applicability was limited.

〔発明の目的〕[Purpose of the invention]

本発明は線形変換が可能であって、高利得の回路を達成
でき2スイッチング回路、矩形波変換回路2判別回路等
に応用できる′4流変換回路を提供することを目的とす
る。
An object of the present invention is to provide a 4-current conversion circuit that is capable of linear conversion, can achieve a high gain circuit, and can be applied to a 2-switching circuit, a rectangular wave conversion circuit, 2-discrimination circuit, and the like.

〔発明の概要〕[Summary of the invention]

本発明は、第1.第2のトランジスタ(QY。 The present invention has the following features: 1. The second transistor (QY.

QK)を含む差動アンプと2m個(m≧1)の半導体接
合による第1.第2の接合回路(Qax。
QK) and 2m (m≧1) semiconductor junctions. Second junction circuit (Qax.

Qn2)、 (Qbx、 Qbx)と、第1のトランジ
スタのコレクタを第2の接合回路に接続し、第2のトラ
ンジスタのコレクタを第1の接合回路に接続する手段と
、第1.第2接合回路の任意の部分に接続した入力電流
供給手段と、を備え1.第1゜第2のトランジスタのコ
レクタにつながる点(PY、PK)から出力(例えば差
動出力)を取出すよ5Kt、た電流変換回路である。
Qn2), (Qbx, Qbx), means for connecting the collector of the first transistor to the second junction circuit, and connecting the collector of the second transistor to the first junction circuit; an input current supply means connected to any part of the second junction circuit; 1. This is a 5Kt current conversion circuit that takes out an output (for example, a differential output) from a point (PY, PK) connected to the collector of the first and second transistors.

〔発明の実施例〕 本発明の回路について図面を参照して説明する。尚、説
明に先立ち2文中で用いる各記号を次の通り定義する。
[Embodiments of the Invention] A circuit of the present invention will be described with reference to the drawings. Prior to the explanation, each symbol used in the two sentences will be defined as follows.

nを一連の番号を示す添字として Qn:トランジスタ。n as a subscript indicating a series of numbers Qn: Transistor.

Pn:端子。Pn: terminal.

Vcc :電源及び電圧値。Vcc: Power supply and voltage value.

V B n :バイアス電源及びバイアス電圧値。VBn: Bias power supply and bias voltage value.

In:Qnのエミッタ電流又はコレクタ電流(電流増幅
率が充分大きく実質的に両 者は等しくおける)7− ゛ と、これらの電流値。
The emitter current or collector current of In:Qn (when the current amplification factor is sufficiently large and the two are substantially equal) 7-' and the values of these currents.

値 IPn : P nを経由して流れる電流と電流源。value IPn: Current and current source flowing through Pn.

ISn:Inを特に電流源として用いたときの定電流源
及び定電流源値。
ISn: A constant current source and a constant current source value when In is particularly used as a current source.

第1図は本発明の一実施例を示すもので(A)は回路図
、(B)は特性図である。第1図(A) においてトラ
ンジスタQal、 Qn2およびQb 1゜Qb2はそ
れぞれ接合回路を成し、 Qal、 Qblのベースは
バイアス電源VBIに接続されている。
FIG. 1 shows an embodiment of the present invention, in which (A) is a circuit diagram and (B) is a characteristic diagram. In FIG. 1(A), transistors Qal, Qn2 and Qb1°Qb2 each form a junction circuit, and the bases of Qal and Qbl are connected to a bias power supply VBI.

QalのエミッタはQn2のベースM続され、 Qbl
のエミッタはQb2のベースに接続され+ Qa2+Q
b2のエミッタ即ち接合回路の出力端は差動アンプを成
すトランジスタQて、Qxのベースにそれぞれ接続され
ている。またQyのコレクタはQblのエミッタに接続
され、QxのコレクタはQalのエミッタに接続されて
いる。
The emitter of Qal is connected to the base of Qn2, Qbl
The emitter of is connected to the base of Qb2 +Qa2+Q
The emitter of b2, that is, the output end of the junction circuit, is connected to the base of transistor Q, which constitutes a differential amplifier, and Qx. Further, the collector of Qy is connected to the emitter of Qbl, and the collector of Qx is connected to the emitter of Qal.

端子Pa2はトランジスタQa2のエミッタに接続され
た電流供給端子であり、端子Px、Pyはそれぞれトラ
ンジスタQa1.Qb]のコレクタに接続された出力端
子である。またトランジスタQx、Qyの共通エミッタ
は電流源Isoを介して基準電位点(アース)に接続さ
れ、トランジスタQb2のエミッタは電流源l5b2に
接続されている。そしてトランジスタQa2.Qbz 
のコレクタは電圧源VCCK接続されている。
Terminal Pa2 is a current supply terminal connected to the emitter of transistor Qa2, and terminals Px and Py are respectively connected to transistors Qa1. Qb] is an output terminal connected to the collector of Qb]. Further, the common emitters of the transistors Qx and Qy are connected to a reference potential point (earth) via a current source Iso, and the emitter of the transistor Qb2 is connected to a current source l5b2. and transistor Qa2. Qbz
The collector of is connected to the voltage source VCCK.

次に第1図(A)の回路の動作について第1図(B)の
特性図を参照して説明する。(A)図よりIa1=Ix
、 Ib]=Iy、 Iaz=Ipa2. Ib2=I
sM・・・・(7) となる。ここでIpa2が 工Pa2=ISb2          −・−・(8
)のときを考えると。
Next, the operation of the circuit shown in FIG. 1(A) will be explained with reference to the characteristic diagram shown in FIG. 1(B). (A) From the diagram, Ia1=Ix
, Ib]=Iy, Iaz=Ipa2. Ib2=I
sM...(7) becomes. Here, Ipa2 is engineering Pa2=ISb2 −・−・(8
).

Ial@Ia2eIY=IX−Ib2− Ibx   
 −・(9)が成立し、(8)式が成立したときのみ(
入)図の回路は動作領域となる。
Ial@Ia2eIY=IX-Ib2- Ibx
−・Only when (9) holds and equation (8) holds (
(Input) The circuit shown in the figure is the operating area.

そしてI p a 2=)I s b 2のときに(9
)式が成立するためには I a 1 =I X=OあるいはIb]=Iy=O−
・・(10)のときとなる。
And when I p a 2 =) I s b 2, (9
) For the formula to hold, I a 1 = I X = O or Ib] = Iy = O-
...(10) occurs.

このような特性は図式化すると(B)図の如く表わされ
る。(B)図の縦軸は端子Px、Pyでの電流IPX、
 IPYを示し、横軸は端子Pa2での電流値Ipa2
を示している。Ipx=Ia]=l。
Such characteristics can be expressed graphically as shown in Figure (B). (B) The vertical axis of the figure is the current IPX at terminals Px and Py,
IPY is shown, and the horizontal axis is the current value Ipa2 at terminal Pa2.
It shows. Ipx=Ia]=l.

Ipy=Ibx=Iy であるからIpa2=Isbz
のときIpx、 Ipyは互に等シイ値(工EJo/2
)ヲ呈スル。
Since Ipy=Ibx=Iy, Ipa2=Isbz
When Ipx and Ipy are equal to each other (EJo/2
) Presentation.

Ipaz=I日b2の条件を外れると(10)式より差
動アンプのトランジスタQx、QYは一瞬にしていずれ
か一方が導通、他方がカットオフの状態になる。したが
ってIpaz=IsMを境にしてIPX、 IPYの状
態が切り替わることを意味する。
When the condition of Ipaz=Idayb2 is removed, one of the transistors Qx and QY of the differential amplifier instantly becomes conductive and the other becomes cutoff, according to equation (10). Therefore, this means that the states of IPX and IPY switch at Ipaz=IsM.

これは次の動作による。This is due to the following operation.

例えばトランジスタQyの′1流Iyが増加しようとす
るとトランジスタQb1の電流Ib1がt付加し、  
Qbxのエミッタ4位が下る。(反対にトランジスタQ
xの電流Ixは減少しよ5とする)。Qblのエミッタ
電位が下るとエミッタフォロアのトランジスタQb2を
介してトランジス\りQxのベース電位が下り、Qxの
電流Ixが減少し、Qyの電流Iyがさらに増加しよう
とする。Ixの減少はトランジスタQalの電流Ia】
を減少し、Qalのエミッタ電位を上げ、ひいてはQa
zのエミッタ電位を上げてQYのベース電位を上げ、I
yの増加、Ixの減少を促進する。
For example, when the '1 current Iy of the transistor Qy tries to increase, the current Ib1 of the transistor Qb1 increases by t,
Qbx emitter 4th place goes down. (On the contrary, transistor Q
The current Ix of x decreases to 5). When the emitter potential of Qbl decreases, the base potential of the transistor Qx decreases via the emitter follower transistor Qb2, the current Ix of Qx decreases, and the current Iy of Qy tries to further increase. The decrease in Ix is the current Ia of transistor Qal]
decreases and increases the emitter potential of Qal, which in turn increases Qa
Raise the emitter potential of z, raise the base potential of QY, and
Promotes an increase in y and a decrease in Ix.

このようなIyの増加、Ixの減少は理論的に一瞬に行
われるが、実際には(B)図に示すように急激な傾斜を
ともなった特性となる。
Theoretically, such an increase in Iy and a decrease in Ix occur instantaneously, but in reality, the characteristics have a steep slope as shown in the diagram (B).

したbζって切り替わる付近(Ipaz=Isb2近辺
)は高利得の回路となり、微少信号の増幅や正弦波の矩
形波への変換、あるいは信号判別回路等圧用いてきわめ
て有利である。
The area where bζ is switched (near Ipaz=Isb2) becomes a high gain circuit, which is extremely advantageous for amplifying a minute signal, converting a sine wave into a rectangular wave, or using an equal pressure signal discrimination circuit.

第2図は本発明の他の実施例であり、差動入力の回路で
ある。第2図(A)は具体回路、(B)は特性図を示し
ている。
FIG. 2 shows another embodiment of the present invention, which is a differential input circuit. FIG. 2(A) shows a specific circuit, and FIG. 2(B) shows a characteristic diagram.

第2図にあっては第1図のQxに相当するトランジスタ
をQXI、QK2の並列トランジスタと1、、QXIの
コレクタをQaコのエミッタに、  Q10のコレクタ
をQ+)]のエミッタに、またQyのコレクタをQbz
のコレクタに接続している。さらにQa]のコレクタと
Qbxのコレクタを接続して出力4Pxとし、  Qb
zのコレクタを出力iPYとしている。そしてQ22.
Qbl のエミッタをそれぞれ電流供給端Pa2.Pb
1に接続している。
In Figure 2, the transistor corresponding to Qx in Figure 1 is connected to QXI, the parallel transistor QK2 and 1, the collector of QXI is connected to the emitter of Qa, the collector of Q10 is connected to the emitter of Q+), and the collector of Q10 is connected to the emitter of Q Qbz the collector of
is connected to the collector of Furthermore, connect the collector of Qa] and the collector of Qbx to make the output 4Px, and then
The collector of z is set as the output iPY. And Q22.
The emitters of Qbl are respectively connected to current supply terminals Pa2. Pb
Connected to 1.

またQazのエミッタを電流源l5azを介して接地し
ている。
Further, the emitter of Qaz is grounded via a current source l5az.

8g2図(A)より。From Figure 8g2 (A).

さらに Iaユ・Ia2−IY=IX−Ib2−IPI    
  −−(12)(11)、 (12)式より IPX=2IX]=2(IPa2−IPbl−)−IS
a2)−−(13)Ipy=Iso−Ipx     
     −・−(14)となる。
Furthermore, Ia Yu・Ia2−IY=IX−Ib2−IPI
--(12)(11), From formula (12), IPX=2IX]=2(IPa2-IPbl-)-IS
a2) --(13) Ipy=Iso-Ipx
−・−(14).

今、  l5O=4IBa2とすれば(13)、 (1
4)式の%  4゜性は第2図(B)のようになり、 
 IpazとlPb1の差入力に比例した出力を線形に
取出すことができる。
Now, if l5O=4IBa2, (13), (1
4) The %4 degree property of the formula is as shown in Figure 2 (B),
An output proportional to the differential input between Ipaz and lPb1 can be linearly extracted.

尚2本発明は図示の回路に限定されず1種々の変形例が
考えられる。例えばQaz、 Qbzはトランジスタの
ベース・エミッタ接合特性と同等のダイオード接合に置
き換えることができ、また接合回路は2段の直列接続(
Qal、 Qaz)。
2. The present invention is not limited to the illustrated circuit, and various modifications may be made. For example, Qaz and Qbz can be replaced with diode junctions that have the same base-emitter junction characteristics as a transistor, and the junction circuit can be replaced with a two-stage series connection (
Qal, Qaz).

(Qbx、 Qbz) Kよらず、それ以外の段数をも
って構成することもできる。
(Qbx, Qbz) It is also possible to configure the number of stages other than K.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明の回路は、線形特性が得られ、
かつ高利得でスイッチング回路が作れ、微少信号の増幅
や波形整形等、その応用は広い。
As described above, the circuit of the present invention can obtain linear characteristics,
It also allows the creation of high-gain switching circuits, and has a wide range of applications, including amplification of minute signals and waveform shaping.

しかも半導体集積化に好適で、温度、素子変動に安定で
、1流モードのため低電圧化に有利である。また微少通
流動作が可能で消費電力を少なくできる等の効果−b−
ある。
Moreover, it is suitable for semiconductor integration, is stable against temperature and element fluctuations, and is advantageous in reducing voltage because it is in a single current mode. In addition, it is possible to perform minute current operation and reduce power consumption, etc. -b-
be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はそれぞれ本発明の電流変換回路の各実
施例を示す回路図と特性図、第3図は従来の電流変換回
路を示す回路図である。 Qx、 QR・・・・ 差動アンプを成すトランジスタ
。 Pa2. Ph]  ・・入力鷹流供給瑞子。 Px、Py・・出力端子。 代理人 弁理士  則 近 憲 佑 同     宇  治   弘 (A+ +5n (II) 第1図
FIGS. 1 and 2 are circuit diagrams and characteristic diagrams showing respective embodiments of the current conversion circuit of the present invention, and FIG. 3 is a circuit diagram showing a conventional current conversion circuit. Qx, QR... Transistors forming a differential amplifier. Pa2. Ph] ・・Input hawk flow supply Mizuko. Px, Py... Output terminal. Agent Patent Attorney Noriyuki Chika Yudo Hiroshi Uji (A+ +5n (II) Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)エミッタを共通に基準電流端子に接続した第1、
第2のトランジスタを含んで成る差動アンプと、 それぞれトランジスタのベース・エミッタ接合もしくは
このベース・エミッタ接合特性と同等のダイオード接合
によるm個(m≧1)の半導体接合を有し、m>1の場
合はそれらを直列に接続したものであって、少なくとも
各初段はトランジスタのベース・エミッタ接合で成り、
その初段のトランジスタのベースをバイアス電源に接続
し、各終段の出力端をそれぞれ前記第1、第2のトラン
ジスタのベースに接続した第1、第2の接合回路と、 前記第1のトランジスタのコレクタを前記第2の接合回
路のうちの1つの半導体接合の出力端に接続するととも
に、前記第2のトランジスタのコレクタを前記第1の接
合回路のうちの1つの半導体接合の出力端に接続する線
路を含んで成る接続手段と、 前記第1、第2の接合回路の任意の半導体接合の出力端
に接続した入力電流供給手段と、前記第1、第2のトラ
ンジスタのコレクタにつながる線路から出力を取出す手
段とを具備して成る電流変換回路。
(1) The first one whose emitter is commonly connected to the reference current terminal,
A differential amplifier including a second transistor, and m semiconductor junctions (m≧1) each formed by a base-emitter junction of a transistor or a diode junction having the same base-emitter junction characteristics, m>1. In the case of , they are connected in series, and at least each first stage consists of the base-emitter junction of a transistor
first and second junction circuits in which the base of the first stage transistor is connected to a bias power supply, and the output end of each final stage is connected to the bases of the first and second transistors, respectively; A collector is connected to an output terminal of a semiconductor junction of one of the second junction circuits, and a collector of the second transistor is connected to an output terminal of a semiconductor junction of one of the first junction circuits. connection means comprising a line; input current supply means connected to the output ends of arbitrary semiconductor junctions of the first and second junction circuits; and an output from the line connected to the collectors of the first and second transistors. A current conversion circuit comprising means for extracting the current.
(2)前記差動アンプは、第1、第2のトランジスタの
ほかに、エミッタをこれらトランジスタのエミッタに共
通に接続し、ベースを第2のトランジスタのベースに共
通に接続した第3のトランジスタを有し、かつ前記接続
手段には第3のトランジスタのコレクタを前記第2の接
合回路のうちの1つの半導体接合の出力端に接続する線
路を有して成ることを特徴とする特許請求の範囲第1項
に記載の電流変換回路。
(2) In addition to the first and second transistors, the differential amplifier includes a third transistor whose emitters are commonly connected to the emitters of these transistors and whose bases are commonly connected to the base of the second transistor. and the connecting means includes a line connecting the collector of the third transistor to the output end of one of the semiconductor junctions of the second junction circuit. The current conversion circuit according to item 1.
JP60289153A 1985-12-24 1985-12-24 Current conversion circuit Pending JPS62149205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60289153A JPS62149205A (en) 1985-12-24 1985-12-24 Current conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60289153A JPS62149205A (en) 1985-12-24 1985-12-24 Current conversion circuit

Publications (1)

Publication Number Publication Date
JPS62149205A true JPS62149205A (en) 1987-07-03

Family

ID=17739447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60289153A Pending JPS62149205A (en) 1985-12-24 1985-12-24 Current conversion circuit

Country Status (1)

Country Link
JP (1) JPS62149205A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176814A (en) * 1981-04-03 1982-10-30 Ibm Current mode differential multistage amplifier
JPS5957508A (en) * 1982-09-27 1984-04-03 Sony Corp Variable current amplifier circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176814A (en) * 1981-04-03 1982-10-30 Ibm Current mode differential multistage amplifier
JPS5957508A (en) * 1982-09-27 1984-04-03 Sony Corp Variable current amplifier circuit

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