JPS62147725A - Charged beam exposure apparatus - Google Patents

Abstract

PURPOSE:To improve the throughput of a charged beam exposure apparatus by providing a main deflection controller, and a sub deflection controller for independently controlling a plurality of sub deflectors corresponding to main deflectors. CONSTITUTION:A first charged beam exposure apparatus splits a plurality of deflectors corresponding to charged beams into main and sub deflectors 108, 107, and provides main deflector controllers 120 for commonly controlling two or more main deflectors, and sub deflector controllers 119 for independently controlling the corresponding sub deflectors. A second charged beam exposure apparatus associates two or more charged beam sources and deflectors in one mirror body 200, provides a plurality of mirror bodies, splits the deflectors into main and sub reflectors, and provides main deflector controllers for common ly controlling two or more main deflectors in the same mirror body and sub deflector controllers for independently controlling the corresponding sub deflectors. Thus, the throughput of the apparatus is improved.

Description

[Detailed Description of the Invention] "Field of Industrial Application" The present invention is directed to a multi-beam system using an electron beam or an ion beam, which is used to form fine patterns required in the manufacture of conductor integrated circuits, etc. Related to charged beam exposure equipment.

[Conventional technology]

As an example of a secondary charged beam exposure device using multi-beams, see Journal of Observer and Technology 19 (1981), p.

953~957 (D, 005mlth and K,
J-Harte: “Electron beam
array lithography'Journal
of Vaccum 5science and Te
chnolog7.19 (1981) p953-95
7) is shown in Figure 10. 100
0 f'i electron gun, 1001 blanker, 1002 po forming aperture, 1003 kj coarse deflection C (coarse def
lector), 1001; t matrix lens, 1
005 is a fine deflector
), 1oosi ueno 1, 1007 is on stage. - Chita, 1ooa is the control computer, 1009
Imabutton memory, 1010id blanker control circuit,
1011 is a coarse deflection control circuit, 1012 is a registration correction circuit, and 1013 is a fine deflection control circuit.

The electron guns 1000 are arranged in a 3x3 arrangement with an interval of 30 mm, but only three are shown in the figure. One mirror body 2000 corresponds to one electron gun. j;υ
Well, the 1-piece mirror body is one electron gun 1000, one blanker 1001, and one forming aperture! +1002.0.625
A matrix lens 1004 consisting of lenses 7Jh arranged in a 16×16 array with rm spacing? X, Y in the same array as L
It consists of a fine deflector 1005 consisting of a deflector.

The drawing data is read out from the common memory for each beam (Tanchi Tough C Meta/Memory 1009) and sent in parallel to the mirror body 3-'3. The deflection is controlled by the coarse deflection control circuit 1011 and the fine deflection control circuit 1013 based on the common batten data in the body, and occurs when all 3×3 batons of the same size and shape are oriented.In other words, 3×3 same chips are drawn at the same time. This will continue to be the case.

[Problems to be Solved by the Invention] By the way, since the spacing between fd and 3x3 beams is set to 30 mm in the following device as described above, the step size is, in fact, 30 mm.
3 such as mm, 15mm, 10mm, 7.5mm
It is limited to an integer fraction of 0 mm. Other sizes,
For example, in the case of chips of 8 m x 111 squares, the chips must be arranged at intervals of 10 mm.

Assuming that a 980 mm square area can be written on a wafer, the number of chips will be 64. On the other hand, if the chips can be arranged at 8 mm intervals without waste, then one chip can be obtained, so 36 chips are wasted and only one chip is produced.In SI manufacturing, it is important to reduce the cost per chip. It is desirable to be able to arbitrarily set the interval between the tips and the chips, which has a meaningful meaning.As a friend, it is possible to change the interval tl between the mirrors mechanically, but it is also possible to change the distance tl between the mirrors mechanically, but Due to structural constraints, it is difficult to remove the gold film from the movable mechanism of the mirror9, and it also increases installation costs.In this way, conventional devices have large restrictions on chip size, leading to problems with It became.

Also, to improve throughput, is it effective to increase the number of beams corresponding to a wafer?In order to do so, the spacing between the mirrors must be reduced, so there are structural limitations. . Therefore, it is difficult to greatly increase the number of beams in the conventional structure described above, and it is not expected to dramatically improve the sluggish If.

[Means for solving problems]

In the first charged beam exposure apparatus of the present invention, each of the plurality of deflectors corresponding to each charged beam is divided into a main deflector and a sub deflector, and two or more main deflectors are commonly controlled. A main deflector control circuit and a sub-deflector control circuit for controlling the corresponding sub-deflectors independently of each other are provided.

The second charged beam exposure device f of the present invention has two or more charged beam sources and deflectors all incorporated into one mirror body, and
A plurality of L-shaped mirror bodies are provided, each deflector is divided into a main deflector and a sub deflector, and a main deflector control circuit that commonly controls two or more main deflectors in the same mirror body, and a corresponding sub deflector are provided. It is equipped with a sub-deflector control circuit that independently controls the deflector.

[Operation] In the 1st o device, each beam is located in a different area on each Nara 1 so that the 4'' spacing of the plurality of beams corresponding to luni/・does not match the chip spacing. Even in the case of summer, the IIT + deflector moves this independently and draws the desired bump in each area.
Simultaneous drawing is possible.

In addition to this, in the second device, lfi is added to lurchin/1.
By adapting your body, you can deal with a large number of sea urchins.

〔Example〕

Is Fig. 1 an embodiment of the present invention? This is a configuration diagram of the electron beam exposure apparatus shown in FIG. 100 is an electron gun, 101U irradiation lens,
102ij blanker, 103U first g-type aperture, 104 second forming aperture, 105 forming deflector, 106 forming lens, 107 sub-deflector, 108 main deflector, 109i
The objective lens, 110 is a mark detector, and 4
The entire system corresponds to one mirror body 200. In the figure, only two skins are shown, and the mirror bodies are arranged in a 2x2 pattern. Four beams are generated for each bell body, resulting in a total of 16 beams.

111 is a wafer, 112 is a stage, 113 is a control calculator, and 114/11 is a button memory. 115 is a data restoration/shot decomposition circuit; 116 is a drawing control circuit; 11
7 is a blanker control circuit, 118 is a forming deflection control circuit, 1
19 is a sub-deflection control circuit, and one system is provided for each of the electron guns to the book.

120 is a main deflection control circuit and is commonly used.

121 is a laser length measuring device, 122i is a mark detection control circuit,
123 is a stage control circuit.

The configuration and operation of the electron beam exposure apparatus shown in FIG. 1 will be described in detail below.

First, FIG. 2 shows the correspondence between the beam arrangement within the mirror body and the wafer. 201 indicates a beam.

Four beams 201 correspond to each mirror body 200, and they are arranged in a row at equal intervals. One wafer 111 is irradiated with each of the four beams. Wafer 1
11 are arranged in a 2×2 arrangement on a stage 112 and can be moved in common. The arrangement and spacing of the mirror bodies 200 are set to be the same as the query.

FIG. 3 shows the positional relationship of the beams within the wafer. 30
0Ia chip, 301 is a wafer mark.

Four beams 201 are lined up in a row at an interval of L=20 mm. As shown in the figure, the vertical spacing C of the chips generally does not match L. The number of beams N and the distance @L are
Assuming that the maximum length in the vertical direction that can be arranged on one wafer is on, it is set to be N×L2m. this is,
The technique explained in ROTO is used to reduce unnecessary movements in drawing.

FIG. 4 shows an example of the lens structure of the irradiation lens 101, the shaping lens 106, and the objective lens 109 shown in FIG. 1 in order to obtain the beam in this easy-to-use 4×1 array. 400 is a lens electrode, 401 is a lens aperture, 402 is an object surface, 40
3 is an image plane, and 404 is a lens power supply. This lens is
It uses a 4x1 array of matrix lenses. This matrix lens U is composed of an Einzel lens as shown in the figure, and a common voltage is connected to the lens power supply 40 to the intermediate electrode.
Back 9 is applied to 4. By using this type of electrostatic matrix lens, the structure becomes simple, and it is also easy to reduce the distance between the lenses and the distance between the lens apertures. Furthermore, it is relatively easy to increase the precision of this lens spacing, and the precision of the beam spacing can be improved.

Next, the mirror body 200 with the beam arrangement explained above is
I will explain how to draw a baton using . First, FIG. 5 shows the movement of the beam during drawing. C
is the vertical spacing of ticks, S is the belt width, and L is the beam spacing. Here, the belt i is a belt-shaped area surrounded by the length T between both ends of the chip arrangement and the width S shown in the figure. The belt width S is set within a region that can be deflected by the main deflection.

The t stage 112 shown in FIG.
3, drawing is performed for each belt instead of continuous movement. Main deflector 1 within the width of beam zo1us
08, while deflecting with the sub-deflector 107, complete drawing is performed using the drawing procedure described later.

First, move the beam 201 to the starting point indicated as ST,
Take a margin t of run-up pressure 1 = M J to make the stage constant speed. At this point, the entire movement of the stage begins, and when the stage reaches a constant speed and reaches the position to be drawn, drawing begins. Arrow A indicates the direction of beam movement. The position at which the pattern / is to be drawn is determined from the stage position measurement data by the laser length measuring device 121. When the drawing for 1 minute is completed, the stage is stopped and the stage is stepped vertically by S.

Once again, with a margin of 9 for the run-up distance J, draw on the next belt' while moving the entire stage continuously. Repeat this operation until the drawing of all belts is completed.

The order of movement of the stages, etc. is controlled by a control calculator.

In this example, if N XL = Cm as described above, drawing of all chips is completed after all steps of the stage are completed by five belts. The end point is indicated as 't ED.

Further, the numbers shown with BL on the right side indicate the entire belt number. In other words, the beam in the upper left corner has 1 belt number 1.2,
3, 4.1 j ridge, the next row of beams is 2.3, 4, 1
．． Draw in the order of step 2. If NXL is used, drawing will be performed using only one beam or N-1 beams for several belts, resulting in dead time. However, in terms of NXL2m, the dead time will be as small as the drawing time of several belts at most ν, and this effect is small and can be ignored in terms of the total drawing time. Here, the chip interval C will be the same width S on the compression side as the minimum unit, but since a continuous movement drawing method is used, what is the overall drawing speed? As expected, i deflection width Srs.

It can be made as small as several 100 μm. The step interval is increased by the maximum S than the vertical thickness of the steps, and the number of steps in the vertical direction is multiplied by S (rfj increases by the size of the step array, but this value is L7 Therefore, it does not substantially affect the number of chips that can fit on one wafer and is not a practical problem.'!
Although the chip spacing is limited on a belt-by-belt basis, it is possible to remove the fli11 limit by providing a beam aligner if necessary. However, if the beam spacing is not an integral multiple of the belt width, a deviation will occur, so the beam aligner is used to adjust the beam spacing so that the main deflection center of each beam is at the center of the belt width. The adjustment amount may be at most S/2. In this way, the chip spacing can be set completely arbitrarily.

FIG. 6 is an explanatory diagram of the procedure for drawing the entire inside of the belt. 6
00 is a sub-deflection area, 601 is a sub-deflection center, 602 is a shaped beam, 60311'i subchip''''C: Roll.

Here, since a rectangular shaped beam is used as the beam 201, in order to clearly indicate this, the shaped beam 601 is
And so. In the figure, two belts 2 are shown. Divide the area into areas that can be scanned by the sub-deflection of the belt metal, and then scan the next area.
It's called Sotu. For example, the belt width is 'f-200 μm, and the sub-step is 50 μm square. The width of the sub-chip should be set small, taking into account the distortion correction of the sub-deflection and the installation error of the phenol. First, in common to each beam, the main deflector 108 in FIG. 1 is operated by the main deflection control circuit 120 to move the sub-deflection area 601 to the sub-step at the upper left corner of the belt. Next, 1
In the ifll deflection area 600, the beam deflector 107 (Cm deflector 107,
The shaping deflector 10 and the Beblan force 102 are respectively FAff
Deflection control circuit 119, forming deflection control circuit 11B, blanker control circuit 117? Use-C operation, forming beam 6
02 is obtained and irradiated to the desired position. The sub-deflector 107 is
The stage position of the laser length measuring device 121 is operated with full reference to the t data so that the shaped beam can be irradiated accurately at the position 6. These operations (controlled by the drawing control circuit 116 under the control of the A1 control computer 118 Here, as shown in Fig. 1, a variable shaping beam element system consisting of a first shaping aperture 102, a second shaping aperture 103, a shaping deflector 105, and a shaping lens 106 is used. The size of the beam that can be shot can be changed. Therefore, the drawing time can be significantly reduced compared to using a spot beam or a fixed shaped beam all around the area. Sub-deflection area 600
The vector scan scans the beam only where one tap is placed within the beam, and deflection is performed efficiently.

Here, since we draw all different battens with the valley beam, -f
The drawing time for each sub-nap differs by fK%.

Therefore, after waiting until the writing of the subchip with the largest number of strokes is completed, the compression side is simultaneously operated in the same order as shown by arrow B in the figure, and each beam is applied to the next subchip. The sub-concave area 600 corresponding to the main deflection is simultaneously operated 114 times, and the same drawing operation is repeated.During this time, the stage is continuously moving as shown by arrow A.The sub-concave area 600 due to the main deflection The movement order does not have to be as shown in the figure. However, when there is no button to draw on the subchip corresponding to each beam, the substeps can be skilagged in common with the main deflection to save dead time. You can also do that.

Figure W, 7 shows the correspondence between the slam data and the slams inside the belt. 700 is a slam. Here, an example of four belts is shown, and only steps are shown. The batan data is the first
In the figure, smooth control meter ga! 113f, input the slam memo 1J1141c. The button data can be stored in any address layout, even if it is not for each belt, as long as the order is determined in advance.
14 may be stored. In the figure, the proportionality of the allocation of the step-worth of baton data to the baton memory for each belt is shown. Normally, the fixed pattern data is stored in the baton memo 1, and the data for repeated batons is compressed and input in the form of 7. Restore to compatible data. Each baton is usually rectangular, but there is an upper limit to the size of the shaped beam that can be exposed in one writing operation.

Therefore, it is necessary to break down the slams that exceed this upper limit into several shots. Data restoration/shot decomposition circuit 1
It also has the function of 15 cigarettes. The data restoration/shot decomposition circuit 115 is controlled by the drawing control circuit 116 in synchronization with the drawing operation.

As shown in FIG. 1, data restoration/shot decomposition circuit 1
15 has four systems, each of which sends out all independent signals corresponding to each of the four beams in one mirror, and each system is common to the corresponding four beams in the four mirrors. For this reason, as described above, an independent batten data chain can be generated within the mirror body. For example, in a certain beam, the pattern data of belt 1 is the area of the button memory 114]! 9, 'Also, in other beams, the baton data of belt 4 is stored in baton memory 1.
Each of the 14 areas 4 and 9 is read out in parallel, and converted into baton data for each shot by the respective data restoration/shot decomposition circuits 115, and the baton 700 is drawn. Before the stage moves to the area corresponding to the step and enters the nap area of the rig, the address where the entire pattern data is exposed is returned to the start address of the slam data for each belt. Then, all the next chips are drawn while sequentially reading out the button data starting from the button data at this first address. Repeat this operation for one row of chips. Once the step size is determined, the number of the belt corresponding to each beam can be calculated, so calculate this number in advance using the total control computer 113, and refer to this number before starting to draw one belt. Read out the baton data.

Selection of the read address of the button data does not need to be performed by the controller q2iso 113, but may be performed using a dedicated address control circuit.

Here, in order to draw while continuously moving on the stage, it is desirable that the direction of the belt and the direction of movement of the stage be as flat as possible. In addition, regarding the valley beam that is common to mirror fins, it is desirable to make the position of the subchip where writing starts to coincide with the position of the IVx beam as much as possible. When loading the stage VC, the third
The wafer mark 301 shown in the figure is detected and the X and Y positions and rotation amount of the wafer are all measured to check the alignment of the wafer. Beam deviations due to alignment errors are corrected as shown in FIG. Figure (b),
(c) shows the same Fx+(*1 ICRG ml knee 1, fail anti-I W VC shown f). , 30Qb, the corresponding sub-chips 603a, 6(J3b) are shifted relative to the beams as shown in FIG.

Therefore, the sub-deflection area 600 corresponding to the sub-step is corrected, and the sub-deflection is corrected by shifting the position as shown in figure L9, and the sub-deflection area is all positioned at position t of the sub-steps 603a and 603b by correcting the position and drawing the sub-chip. . here,
Although the main deflection unit 1 is made common, if it is made independent between each mirror body and common within the mirror body, the above-mentioned correction can also be performed by the main deflection.

Next, a mark detection method for completely correcting beam deviation due to tip distortion is shown in FIGS. 9(a) and 9(b). FIG. 9(a) shows a mark 900 on each chip 300.
This is a diagram that fully explains how to detect marks when they are arranged at the four corners of
FIG. 9(b) U, spacing of beam 201 and mark 9
This is a diagram illustrating a mark detection method when the vertical intervals of 00 are made equal. 1. In FIG. 9(a), the beam 20
1. While stepping the stage one by one, all marks 900 of chips in one horizontal row are detected.

At this time, the other beams are blanked by the blanker 102 so that the wafer is not irradiated with the beams. Mark detection is performed by detecting all the reflected electrons from the mark using the mark detector 110 shown in FIG. Mark detector 1
10 is controlled by a mark detection control section 122. In the control calculation 113, the nap distortion is determined from the obtained mark position 1α data and corrected by the sub-deflector 10γ when drawing. 300 chips in one horizontal row
Each time the detection of the mark 900 is completed, the stage is stepped and moved in the direction shown in the figure so that the Y-direction position of the beam almost matches the Y-direction position of the mark required for the nap of the respective column. This operation sound is repeated until all marks are detected. As long as the interval between the beams is smoothed and measured, each mark can be detected using any beam, but here, in order to reduce the amount of stage movement, the mark is detected using the beam closest to the mark 900. is desirable. Next, in FIG. 9(b), the distance between the mark 900 and the beam 201 is made to match, so that each beam can detect the mark at the same time. Since the spacing between the marks 900 and the spacing between the chips 3000 do not match, the distortion of the chips is obtained by extrapolating from the mark position data.

In this case, since the chip distortion is determined based on data detected by marks using different beams, the spacing between each beam is of course measured in advance, and the chip distortion is corrected.

〔Effect of the invention〕

The charged beam exposure of the present invention is calibrated for each beam based on independent baton data? Since it has a function to perform simultaneous control, it has the effect of being able to arrange chips of any size without waste, unlike conventional devices that generate common bumps for all beams. Furthermore, by arranging a plurality of sharp metal beams to generate a plurality of metal beams, a mantissa number of wafers can be written at the same time, and the through-grating process can be greatly improved. This is possible because since the wafer is moved on a common stage, the stage movement time, mark detection time, etc. can be shared for the 15-beam, and the dead time can be greatly reduced as a whole. In addition, by increasing the number of t5 wafers, the number of beams increases and writing time is also reduced, so throughput is greatly improved. Also,
By dividing the deflector into the main deflector and h+tl deflector, the main deflector is commonly controlled while the sub deflector is controlled independently, simplifying deflection control, reducing the control circuit scale and reducing the device configuration. All can be done easily. Second, there is a fourth effect of reducing device costs.

As described above, according to the charged beam exposure apparatus of the present invention, the equipment cost' (English 0': J
It is possible to realize high throughput and high throughput.

By using this device, it becomes possible to significantly reduce the manufacturing cost of LSI.

[Brief explanation of drawings]

Figures 1 to 9 are diagrams showing the implementation of the present invention, Figure 1 is a configuration diagram of a charged beam exposure device, and Figure 2 is a diagram showing the relationship between the beam arrangement and the arrangement of the unit. , FIG. 3 is a diagram showing the positional relationship of the beams within the wafer, FIG. 4 is a perspective view showing the lens structure, and FIG. Figure 6 is a diagram showing drawn hands l1liI inside the belt, Figure 7 is a ninth diagram explaining the correspondence between the baton data and the batons inside the belt,
FIG. 8 is a diagram for explaining the subchip position correction method,
The W2O diagram is a diagram for explaining the mark detection method, and Figure 10 shows a conventional example (it is a 4-component diagram. 100...t; secondary gun; 107... sub-deflector;
108... Main deflector, 111*... Wafer, 11
2...Stage, 113...Control calculation m:s
114... Exposure/bang memory, 115... Reference data Enomoto/shot decomposition circuit, 116... Drawing control circuit, 119... Sub-deflection control circuit, 120...
・・Main deflection control circuit, 200 ・・Mirror body, 201
····beam

Claims (2)

[Claims] (1) In a charged beam exposure apparatus equipped with a plurality of charged beam sources and a beam deflector built into a mirror together with each charged beam source, each beam deflector is divided into a main deflector and a sub deflector, and A main deflection control circuit having at least a function of commonly controlling two or more main deflectors, and a sub deflection control circuit having at least a function of independently controlling two or more sub deflectors corresponding to the main deflector. A charged beam exposure device featuring: (2) In a charged beam exposure apparatus equipped with a plurality of charged beam sources and a beam deflector incorporated in a mirror body together with each charged beam source, a plurality of mirror bodies each having two or more charged beam sources and deflectors are provided, and Each deflector is divided into a main deflector and a sub-deflector, and a main deflection control circuit has at least a function of commonly controlling two or more main deflectors in the same mirror body, and a plurality of sub-deflectors corresponding to the main deflector. A charged beam exposure apparatus comprising: a sub-deflection control circuit having at least a function of independently controlling a deflector.