JPS62144088A - Time measuring apparatus - Google Patents

Abstract

PURPOSE:To enable the measurement of a time range at a high speed and in real time with a pair of fraction time measuring circuit, by converting a fraction time into a voltage without resetting a time-voltage converter to perform a computation after an A/D conversion thereof. CONSTITUTION:When a start fraction time pulse is applied, a time-voltage converter 1 converts the period and time of a pulse width of the pulse to voltage and when upon the end of the pulse, a voltage value v1 to v2. The value of v1-v2 becomes a voltage proportional to the start fraction time. During this period, the converter 1 is operated without resetting it thereby enabling high- speed operation. Thereafter, a step fraction time pulse comes, a time-voltage conversion is done with the voltage v3 (v2=v3) previously held as starting point to obtain a voltage v3. This v3-v4 value is becomes a voltage proportional to a stop fraction time. These v1-v4 values are converted to a digital value with an A/D converter 5 and applied to processor 6o through a latch circuit 7. The processor 60 are given v1-v4 and a voltage of a pulse width equal to a clock cycle to compute time.

Description

[Detailed description of the invention] B. [Object of the invention J [Industrial application field] The present invention relates to a time measuring device.

More details)! The present invention relates to a time measurement device that can accurately measure even so-called fractional time that is less than the period of the reference clock signal.

(Prior Art) Universal counters are widely used as devices for measuring the frequency, period, etc. of a signal.

Furthermore, not only such a counter but also a device such as an LS tester that measures the time from the point in time to the point in time in which the signal to be measured is formed is used.

Generally, the following principle is adopted to measure time with high precision. A clock signal with a period T0 is passed through a gate that is open in the measured time width Tχ, and the number N of clocks passing through is counted. And, NTo is the time width. Although this method improves resolution as the clock frequency increases, there is actually a limit to the speed of the circuit elements. That is, this means cannot measure with a resolution higher than the clock cycle.

In the above method, strictly speaking, Tx-NT.

This is because Tχ is not divisible by TO and there are small fractional times. This is shown in Figure 4. In Figure 4, ,
ΔT! is the fractional time from the rising edge of Tχ to the clock Co generated immediately after that, and ΔT2 is Tχ
The clock Cu generated immediately after the falling edge of
It is a fraction of the time up to. Then, open the period gate between the clock signal Go and CTL (see (d) in Figure 4).
and count the number of clocks passing. Let N be the clock error during that period [(e) in Figure 4]
The time width Tχ is expressed by equation (1).

T-x=NTo+ΔT+-ΔT 2 (1
) Therefore, it can be seen from equation (1) that by measuring 6 fractional times and ΔT2, it is possible to measure the time width Tχ with a resolution greater than the clock cycle To.

As a known means capable of measuring this fractional time, there is the time expandicon method shown in FIG. This method uses an integrator to expand the fractional time using the charge or voltage stored in the capacitor as an intermediary, and measures it with a clock. FIG. 5 is a diagram showing a case where voltage is used as an intermediary. This uses two integrators, one of which charges capacitor CI with current 11 while under Δ and then holds this output voltage. The other integrator then starts operating and charges capacitor C2 with current I2. If we take ΔTE like the fifth factor, ■・C”
(2) ΔTE- becomes T·ΔT, and the enlargement ratio is given by I+cz/ZC1.

(Problem to be Solved by the Invention) However, in the measurement of fractional time, the above means introduces a reference clock and corrects it in order to remove the influence of the bias current and offset voltage of the integrator. It is necessary to perform calculations. Furthermore, in order to separately measure the fractional time at the start and stop of time width measurement, a two-phase fractional time measuring circuit is required, which increases the price of the device. In addition, it takes a long time in principle to expand the fractional time and measure it, and it also takes a considerable amount of time in total to perform correction calculations for each fractional time and use these results to calculate four periods. become.

Therefore, since it takes too much time to measure fractional hours, there is a problem that high-speed repeated measurements or real-time measurements cannot be performed.

An object of the present invention is to provide a time measuring device that can perform high-speed repetitive measurements, real-time measurements, and high-resolution measurements.

``Structure of the Invention J (Means for Solving the Problems) In order to solve the above problems, the present invention converts the start fractional time pulse and the stop fractional time pulse into voltage values, and converts the start fractional time pulses into voltage values. In a device that calculates a fractional time by adding calculations to a signal based on , and measures the measured time,
.

A time-voltage converter that introduces a pulse signal and outputs a signal whose voltage changes according to the pulse width of this signal; an AD converter that converts the output of this time-voltage converter into a digital signal; It is equipped with a fractional time measuring circuit consisting of a latch circuit that stores the output of the converter, a timing signal generator that controls the operation timing of the AD converter, and a fractional time pulse signal is generated by one time-voltage converter. When converting to a voltage value, this time-voltage converter is configured to continuously convert into a voltage value during the period between a pair of start fractional time pulses and stop fractional time pulses without resetting in the middle. It is.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an example of the configuration of a fractional time measuring circuit, which is a main part of the present invention. Further, FIG. 2 shows a block diagram of a time measuring device according to the present invention, and FIG. 3 is a time chart.

First, the entire time measuring device according to the present invention will be explained using FIG. In the figure, 10 is an input amplifier,
A signal having a time width to be measured introduced from the input terminal p1 is waveform-shaped into a rectangular wave as shown in FIG. 3(1). Reference numeral 20 denotes a control circuit, which inputs a signal from the input amplifier 10 having a time width Tχ to be measured and a clock signal sO, and generates a fraction time pulse signal S1 having a pulse width corresponding to a so-called fraction time, and a gating clock signal. S2 can be output. The pulse width of the fractional time pulse shown in FIG. 3 is wider by one clock pulse than that of the fractional time pulse explained in FIG. 4(C). Although this is to prevent the influence of non-linearity, etc., FIG. 3 and FIG. 4 are mathematically the same. The reason for this is that if the calculation of (ΔT1-ΔT2) is performed, one clock is canceled. A counter 30 measures the number of times the gating clock signal S2 introduced from the control circuit 20 crosses this level. 40 is a clock generator with a period of 1. A clock signal SO is generated as a time reference. Reference numeral 50 denotes a fractional time measuring circuit, which has a function of introducing a fractional time pulse signal S1 and a clock signal SO whose pulse width is known, for example, and outputting a signal that becomes the basis for calculating the fractional time. The configuration of this fractional time measuring circuit 50 is illustrated in detail in FIG. Reference numeral 60 denotes a block, which introduces signals from the counter 30 and the fractional time measuring circuit 50 and performs an itch to numb the time.

In FIG. 1, 1 is a time-voltage converter, which outputs a signal whose voltage changes corresponding to the pulse width of the introduced signal. Specifically, for example, it is composed of something like an integrator (not shown), and charges or discharges an integrating capacitor (not shown) with a constant current during the period of the applied pulse width signal. It can output a voltage signal proportional to width (time).

3 is a buffer circuit that transmits the output voltage of the time-voltage converter 1 to the next stage.

5 is an AD converter that converts the output of the time-voltage converter 1 introduced via the buffer 3 into a digital signal. Since this AD conversion@5 requires high speed in the field related to the present invention, it is usually a flash type (fully parallel type > AD
A converter is used.

7 is AD! This is a latch circuit that latches the output signal of the converter 5 at high speed, and is made up of, for example, a flip-flop or a RAM. Usually, a total of four types of values (digital values) are stored: the voltage value at the start and the voltage value at the end of the integration of fractional time pulses that occur at the start and stop of measurement.

A timing signal generator 9 outputs a conversion clock for the AD converter 5 and a latch signal for the latch circuit 7.

The operation of the circuits of FIGS. 1 and 2 configured as described above will be explained.

A signal having a time width to be measured applied to the input terminal p1 is waveform-shaped by the input amplifier 10, becomes a signal like <+> in FIG. 3, and is introduced into the control circuit 20. In the control circuit 20, the rising edge and falling edge of the signal shown in FIG. Outputs a time pulse (pulse width ΔT2 >).

In addition, the control circuit 20 introduces the clock signal sO from the clock generator 40, and as explained in FIG. It has a gate circuit (not shown) that is open during the period of the clock signals C0 and CTL, and outputs the gating clock signal @S2 passing through this gate circuit to the counter 30.

This gating clock signal S2 is counted by the counter 30 (count number N), and then by the processor 60,
The NTo rendition shown in equation (1) is performed.

On the other hand, the fractional time measuring circuit 50 introduces the fractional time pulse S1 shown in FIG.

The time-voltage converter 1, as shown in FIG. 3<IV),
It is assumed that the voltage value is C1 before the start fractional time pulse is applied. When the start fractional time pulse is applied, for example, an integration operation is performed during the period of the pulse width (ΔT), and the voltage value at the end of the pulse becomes C2. Therefore, the value of υ1-v2-ΔV1 is a voltage proportional to the start fractional time.

In the present invention, even after converting the start fractional time pulse into a voltage and increasing the voltage υ2 to 19 as shown in FIG. 3, the time-voltage converter 1 continues to hold the voltage υ2 as it is. That is, in the present invention, the time-to-voltage converter is operated continuously during the period between a pair of start and stop fractional time pulses without resetting it. The reason is that high-speed operation is possible. Generally, it takes several hundred ns or more to reset the time-voltage converter 1, and if you try to measure a signal with a short measurement time width with one time-voltage converter, this reset time can be ignored. This is because it is not possible. On the other hand, the time required for one AD conversion is about 10 ns.

Then, when the next stop fractional time pulse comes, the held voltage U3 (normally, since the time-voltage converter 1 has drift etc., it goes to 02 and C3, but if it has an ideal function, C2= 1) Using 3) as a starting point, time-voltage conversion is performed again, and as a result, voltage V is obtained. As mentioned above, ZJ3-? The value of J, -Δv2 becomes a voltage proportional to the stop fraction time.

In contrast to the time-voltage converter 1 that operates as described above, the timing signal generator 9 is configured as shown in FIG. 3(V).
Apply the D conversion clock to the AD converter e5. Then, at this timing, the AD converter 5 converts the output of the time-voltage converter 1 introduced via the buffer 3 into a digital value. Therefore, υ1 to υ4 are each converted into digital values.

Further, the timing signal generator 9 generates a latch clock as shown in FIG. 3 (Vi), and at this timing A
The output of the D converter 5 is taken into the latch circuit 7. Each of the latch clocks C1 to C4 is generated, for example, at the following timing.

C1 operates in response to the rising edge of the start fractional time pulse, and C2 is for latching the output value of the time-voltage converter 1 at the end of the start fractional time pulse, for example, as shown in FIG. 3(V). AD conversion clock CI2 shown in
It is operating in response to this.

Similarly, C3 operates in response to the rising edge of the stop fractional time pulse, and C4 is for latching the value at the end of the stop fractional time pulse.
It operates in response to D conversion click cl 4.

(3) When a flash type AD converter 5 is used, (11) there is always a built-in latch circuit, so there is no need to provide an external latch circuit.

In general, a flash type ΔD converter operates to output a value latched one clock ago.

In FIG. 1, when the start fraction time pulse rises, a latch clock C+ is generated, and in response to this, the latch circuit 7 (or the latch circuit built in the AD converter 5) converts to Value converted by Tsuku C11 (C1)
and latch it.

Furthermore, when the AD conversion click c12 occurs after the start fractional time pulse ends, the latch clock C2 is generated in response to this. In this case, the latch circuit latches the value (C2) converted by the AD conversion click c12.

Thereafter, the digital values of C3 and υ4 are latched one after another in the latch circuit in the same manner. After latching these four values, these values are sequentially loaded into the processor 60.

Furthermore, a signal with a known pulse width, for example, a signal with a pulse width of a period equal to the period of the clock signal SO, is added to the time-voltage converter 1, and a voltage value ΔV corresponding to the clock period to is obtained.
3 (q) (not shown).

Using the above v1 to 1)a and Δv3, the processor 60
Now let's perform the first demonstration.

12 (I-2ts) ΔT + (3) Nico, I: Integral current 1B: Bias current C: Integral capacitor capacity Similarly, Δ■ 3-Up (1-Ja) to (S) 1 company, In addition to the above calculations, the processor 1 can calculate the time width Tx of the measurement target by further calculating the equation (1).

C. "Effects of the Present Invention" As described above, according to the present invention, the following effects can be obtained: (1) Conventional devices require expansion time. Even if the operating speed of the AD converter becomes faster in the future than it is now, this time is a theoretically necessary time and there is no room for improvement.

On the other hand, in the device according to the present invention, the fractional time is converted into voltage, which is directly AD converted, and then calculated by a microcomputer, etc., but the AD converter is currently of the flash type. There are very high-speed methods such as, for example, and for this reason, the present invention can operate at higher speeds than conventional means based on its operating principle. Therefore, the time width can be measured at high speed and in real time.

■ Conventionally, two sets of fractional time measuring circuits were required, but in the present invention, one time-voltage converter converts the generated fractional time pulse into voltage (a).
This can be achieved with a set of fractional time measuring circuits.

(2) As can be seen from equation (6), according to the present invention, the effects of the bias current iB, the integral current (2), and the integral capacitor C can be removed. Furthermore, by subtracting the value at the start from the value at the end (υ1-υ2), the influence of the offset voltage can also be removed. Furthermore, droop characteristics, which are fluctuations in hold characteristics, can also be removed. In addition,
If the interval between the start fractional time pulse and the stop m fractional time pulse is short, the fluctuation of the hold voltage can be ignored, so the value at the start of the stop fractional time pulse does not need to be latched, and the conversion time of the AD converter All you have to do is change the interval by a minute.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a configuration example of a fractional time measuring circuit which is the main part of the present invention, Fig. 2 is a block diagram of a time measuring device according to the present invention, Fig. 3 is a time chart, and Fig. 4 is a general FIG. 5 is a diagram for explaining the operation of the time expansion method. 1... Time-voltage converter, 5... AD converter, 7.
...Latch circuit, 9...Timing signal generator, 10
... Input amplifier, 20 ... Control circuit, 30 ... Counter, 40 ... Clock generator, 50 ... Fractional time measuring circuit, 6o ... Processor. Figure 1 De Figure 2 Figure 4 (D) Black 774g 3-Kate Figure 5 - ΔTE -

Claims (2)

[Claims] (1) In a device that converts the start fractional time pulse and the stop fractional time pulse into voltage values, calculates the fractional time by adding calculations to the signal based on this voltage value, and measures the measured time, the pulse signal is a time-voltage converter that outputs a signal whose voltage changes according to the pulse width of the signal; an AD converter that converts the output of the time-voltage converter into a digital signal; Equipped with a fractional time measurement circuit consisting of a latch circuit that stores the output, a timing signal generator that controls the operation timing of the AD converter, and a single time-voltage converter that converts fractional time pulses into voltage values. The time-to-voltage converter is operated to continuously convert into a voltage value during a period between a pair of start fractional time pulses and a stop fractional time pulse without being reset midway. A time measuring device. (2) The time-voltage converter obtains a voltage value corresponding to a known pulse width, and this value is used to correct the bias current of the voltage value corresponding to the fractional time. A time measuring device according to scope 1.