JPS62141867A - Solid-state image pickup element - Google Patents

Solid-state image pickup element

Info

Publication number
JPS62141867A
JPS62141867A JP60281971A JP28197185A JPS62141867A JP S62141867 A JPS62141867 A JP S62141867A JP 60281971 A JP60281971 A JP 60281971A JP 28197185 A JP28197185 A JP 28197185A JP S62141867 A JPS62141867 A JP S62141867A
Authority
JP
Japan
Prior art keywords
vertical
control
solid
state image
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60281971A
Other languages
Japanese (ja)
Inventor
Takashi Murayama
任 村山
Yoshimitsu Kudo
吉光 工藤
Ryuji Kondo
近藤 隆二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP60281971A priority Critical patent/JPS62141867A/en
Publication of JPS62141867A publication Critical patent/JPS62141867A/en
Pending legal-status Critical Current

Links

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To reduce remarkably the reset time by turning on vertical switches simultaneously attached to a photoelectric converting element of each picture element. CONSTITUTION:Vertical selection lines 6 connected to each gate of vertical MOS switches 5 arranged in the row direction are connected at the opposite side of vertical shift registers 2 to a source of a control FET 9 and drains of the control FETs 9 are connected to a common control drain 11. Further, the gates are connected to a common control line 10 and controlled. On the other hand, when the control line 10 goes to a high level, each control FET 9 is turned on to turn on the vertical MOS switch 5 attached to all picture elements at the same time. In applying horizontal scanning to the horizontal shift registers 1 in this state, all picture elements are scanned at once, the residual electric charge of each picture element is read simultaneously to reset photo diodes 8.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は固体撮像素子に関し、更に詳述子nば、リセッ
ト時間が大幅に短縮さnたMO3型固体撮像素子に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a solid-state image sensor, and more particularly to an MO3 solid-state image sensor whose reset time is significantly shortened.

(従来技術) MO3型固体撮像累子素子第2図に図示した如く、マト
リクス状に配置さnた光電変換素子8、これら光電変換
素子に付属した垂直MOSスイッチ5、垂直信号線7に
付属した水平MOSスイッチ4、垂直走査回路2および
水平走査回路1から成っている。
(Prior art) MO3 type solid-state image pickup element As shown in FIG. It consists of a horizontal MOS switch 4, a vertical scanning circuit 2, and a horizontal scanning circuit 1.

このような固体撮像素子に於て、各画素の光電変換素子
、例えば図示したようなフォトダイオードをリセットす
るには各画素ン一度読み出すことにより行わnる。
In such a solid-state image sensor, resetting the photoelectric conversion element of each pixel, for example, a photodiode as shown, is performed by reading each pixel once.

この固体撮像素子をビデオカメラ用として用いた場合、
ビデオカメラは一連のシーケンスが連続的に動作されて
おり、リセットも画像の読み出し動作に引き続いて順次
行わjLる。
When this solid-state image sensor is used for a video camera,
A video camera is continuously operated in a series of sequences, and resetting is also performed sequentially following an image readout operation.

従って、素子自体のリセットは、カメラの電源を入力し
た際の最初の1画面についてだけ行えばよい。
Therefore, it is only necessary to reset the element itself for the first screen when the camera is powered on.

(発明が解決しようとする問題点) しかしながら、このような固体撮像素子を電子スチル・
カメラ等に適用し、単発現象Y tlI+像しよ5とす
る場合、撮像の直前に於てその都度空読み出しを行って
リセットを行わなけnばならず、そのために、−画面読
み出し迄に長い時間を要した。このようにリセットのた
めに長い時間を要することは、第3図からも明らかなよ
うに、リセット時間、撮像時間および読み出し時間によ
り決まるシステム全体の所要時間を長くしてしまい、特
に、前記スチル・カメラで連写を行うような場合には充
分に対応できない事態を生じた。
(Problem to be solved by the invention) However, it is difficult to use such solid-state image sensors as electronic stills.
When applied to a camera, etc., when a single phenomenon Y tlI + image is taken, it is necessary to perform a blank readout and reset each time immediately before taking an image. Therefore, it takes a long time until the screen is read out. It cost. As is clear from FIG. 3, the long time it takes for the reset increases the time required for the entire system, which is determined by the reset time, imaging time, and readout time. This resulted in a situation that could not be adequately handled when continuous shooting was performed with a camera.

本発明の目的は、上記事情に鑑みなさ扛たものf、リセ
ット時間が大幅に短縮1きた固体撮像素子を提供するこ
とにある。
SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a solid-state image sensor in which the reset time can be significantly reduced.

(問題点を解決するための手段および作用)すなわち、
本発明の上記目的は、マ) IJクス状に配置さ扛た光
電変換素子、これら光電変換素子に付属した垂直スイッ
チ、垂直信号線に付属した水平スイッチ、垂直走査回路
および水平走査回路から成る固体撮像素子に於て、各行
の垂直選択線が前記垂直走査回路と反対側でコントロー
ル・FETのソースに接続さnでおり、このコントロー
ル・FETはドレイン側が各垂直選択線に共通のコント
ロール・ドレインに接続さn、かつゲートが共通のコン
トロール線に接続は几でいることを特徴とする固体撮像
素子により達成さnる。
(Means and actions for solving problems) That is,
The above-mentioned object of the present invention is to provide a solid-state device consisting of photoelectric conversion elements arranged in an IJ box shape, vertical switches attached to these photoelectric conversion elements, horizontal switches attached to vertical signal lines, a vertical scanning circuit, and a horizontal scanning circuit. In the image sensor, the vertical selection line of each row is connected to the source of a control FET on the side opposite to the vertical scanning circuit, and the drain side of this control FET is connected to the control drain common to each vertical selection line. This is achieved by a solid-state image sensing device characterized in that the gate is connected to a common control line and the gate is connected to a common control line.

この構成によnば、本来の信号電荷の涜み出しは、従来
と同じく垂直走査回路および水平走査回路からの各走査
パルスにより各スイッチング素子を順次切替えて行わn
る。一方、リセット時には全垂直スイッチが一度にオン
さτして、1水平走査だけ1素子内の全べての残留電荷
が読み出さnることにより短時間のリセットが行わnろ
According to this configuration, the original signal charge is removed by sequentially switching each switching element using each scanning pulse from the vertical scanning circuit and the horizontal scanning circuit, as in the conventional case.
Ru. On the other hand, at the time of reset, all the vertical switches are turned on at once and all residual charges in one element are read out for one horizontal scan, thereby performing a short reset.

(実施例) 以下、本発明の1実施例を図面によって説明する。(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は、本発明によるMO8型固体撮像素子の構造を
示している。この固体撮像素子は周知のものと略同−の
構成から成っており、従って、こ゛の同一部分について
は先の第3図と同じ符号を用いる。
FIG. 1 shows the structure of an MO8 type solid-state image sensor according to the present invention. This solid-state image sensing device has substantially the same structure as the well-known one, and therefore, the same reference numerals as in FIG. 3 are used for the same parts.

すなわち、マトリクス状に配置さnたフォトダイオード
8、これらフォトダイオード8に付属した垂直MOSス
イッチ5、垂直信号線7に付属した水平MOSスイッチ
4、前記垂直MOSスイッチ5および水平MOSスイッ
チ4を順次切替え動作する垂直シフトレジスタ2および
水平シフトレジスタ1から成っている。本発明の素子は
この従来素子に付加して更に各垂直選択線6の出力側、
すなわち前記垂直シフトレジスタ2と反対側にコン)ロ
ール・FET9Y設けている。更に詳しく述べると、行
方向に配置ざnた垂直MOSスイッチ5の各ゲートと接
続した垂直選択線6が垂直シフトレジスタ2と反対側〒
コン)O−ル・FET9のソースに接続ざnており、該
コントロール・FET9の各ドレインは共通のコントロ
ール・ドレイン11に接続ざnている。また、そnらの
ゲートは共通のコントロール線10に接続す几て制御ζ
nる。
That is, the photodiodes 8 arranged in a matrix, the vertical MOS switches 5 attached to these photodiodes 8, the horizontal MOS switch 4 attached to the vertical signal line 7, and the vertical MOS switch 5 and horizontal MOS switch 4 are switched in sequence. It consists of a vertical shift register 2 and a horizontal shift register 1 that operate. In addition to this conventional element, the element of the present invention further includes an output side of each vertical selection line 6;
That is, a control FET 9Y is provided on the opposite side from the vertical shift register 2. More specifically, the vertical selection line 6 connected to each gate of the vertical MOS switch 5 arranged in the row direction is located on the side opposite to the vertical shift register 2.
The control FET 9 is connected to the source of the control FET 9, and each drain of the control FET 9 is connected to a common control drain 11. In addition, those gates are connected to a common control line 10 to control ζ
nru.

このように構成garbだ本発明の固体撮像素子は、前
記コントロール線10の電圧レベルカ低しベル^L濠 
斤立」Lヱレロl’ ?へ1f1h赤1 イ久血モ箇信
号電荷が読み出さ几る。
The solid-state image sensing device of the present invention having the above-mentioned configuration garb lowers the voltage level of the control line 10.
斤台”Lererol’? 1f1h red 1 The signal charge is read out.

すなわち、前記コントロール線10が低レベルの場合、
垂直シフトレジスタ2からの垂直走査・ぞルスにより行
装置さまた垂直MOSスイッチ5の各行が順次選択さn
、一方、水平シフトレジスタ1からの水平走査、eルス
により水平MOSスイッチ4が順次切替えら几て垂直信
号線7が選択さnることにより、各画素に蓄えらnた信
号電荷は順次出力線から読み出さnろ。
That is, when the control line 10 is at a low level,
Each row of the row device or vertical MOS switch 5 is sequentially selected by vertical scanning from the vertical shift register 2.
, On the other hand, the horizontal scanning from the horizontal shift register 1 causes the horizontal MOS switches 4 to be sequentially switched and the vertical signal line 7 to be selected, so that the signal charges accumulated in each pixel are sequentially transferred to the output line. Read it from here.

一方、前記コントロール線10が高しベルニすると、各
コントロール・FET9はオンとなって全画素に付属し
た垂直MOSスイッチ5ゲー斎にオンにする。このよう
な状態〒水平シフトレジスタ1を1水平走査させると全
画素が1度に走査さ几ることになって、各画素の残留電
荷が一斉に読み出さnてフォトダイオード8がリセット
ざnる。
On the other hand, when the control line 10 goes high, each control FET 9 is turned on and the vertical MOS switches 5 attached to all pixels are turned on. In such a state, when the horizontal shift register 1 is scanned horizontally, all pixels are scanned at once, and the residual charges of each pixel are read out all at once, and the photodiode 8 is reset.

(発明の効果) 以上記載したとおり、本発明の固体撮像素子によnば、
各画素の光電変換素子に付属する垂直スイッチが一斉に
オン状態になるように設けたことにより、1水平走査だ
けで全画素の電荷を読み出すことができ、従ってリセッ
ト時間を短縮〒きる。しかもこのリセット時間は、シフ
トレジスタの駆動周波数に係わらず短縮でき、その短縮
の割合は少なくとも垂直方向の画素数分の1と等しく〒
きる。
(Effects of the Invention) As described above, the solid-state image sensor of the present invention has the following effects:
By providing the vertical switches attached to the photoelectric conversion elements of each pixel to be turned on all at once, the charges of all pixels can be read out with just one horizontal scan, thus reducing the reset time. Moreover, this reset time can be shortened regardless of the drive frequency of the shift register, and the reduction rate is at least equal to 1/the number of pixels in the vertical direction.
Wear.

また、本発明は従来素子の周辺部に若干の・ξターン乞
追加するだけで達成でき、この程度の追加では製造コス
トを大幅に上昇することもない。従って、本発明によn
ば、わずかなコストの上昇フ大幅にリセット時間の短縮
さr′L1こ固体撮像素子が得ら几る、
Furthermore, the present invention can be achieved by simply adding a few .xi. turns to the periphery of the conventional element, and this addition does not significantly increase manufacturing costs. Therefore, according to the present invention, n
For example, it is possible to obtain a solid-state image sensor with a significantly shortened reset time with a slight increase in cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明による固体撮像素子の実施例を示す回
路図、第2図は従来周知の固体撮像素子を例示した回路
図、第3図は画像読み出し迄のシステム時間乞説明する
図である。 1・・・水平走査回路(水平シフトレジスタ)、2・・
・垂直走査回路(垂直シフトレジスタ)、3・・・出力
線、4・・・水平MOSスイッチ、5・・・垂直MOS
スイッチ、6・・・垂直選択線、7・・・垂直信号線、
8・・・光tim索子(フォトダイオード)、9・・・
コントロール・FET、10・・・コントロール船、1
1・・・コントロール・ドレイン 代理人弁理士(8107)佐々木 清 隆i゛“ソζ\
(ほか2名)゛。 第 1 図 一−1 s  2 図 ゝ7 面 A°リセ・トー五偽のIJi、clbルたみ七(Bすr
、7B姿疹駄■9.写時間 C山1動tltbと(B今T憎
FIG. 1 is a circuit diagram illustrating an embodiment of a solid-state image sensor according to the present invention, FIG. 2 is a circuit diagram illustrating a conventionally known solid-state image sensor, and FIG. 3 is a diagram illustrating system time until image readout. be. 1...Horizontal scanning circuit (horizontal shift register), 2...
・Vertical scanning circuit (vertical shift register), 3... Output line, 4... Horizontal MOS switch, 5... Vertical MOS
switch, 6... vertical selection line, 7... vertical signal line,
8... Optical timing probe (photodiode), 9...
Control FET, 10... Control ship, 1
1...Control Drain Representative Patent Attorney (8107) Kiyoshi Sasaki
(2 others) ゛. 1st Figure 1-1 s 2 Figure 7 Surface A ° Lise To 5 false IJi, clb Rutami 7 (Bsr
, 7B appearance ■9. Photo time C mountain 1 motion tltb and (B now T hate

Claims (1)

【特許請求の範囲】[Claims] マトリスク状に配置された光電変換素子、これら光電変
換素子に付属した垂直スイッチ、垂直信号線に付属した
水平スイッチ、垂直走査回路および水平走査回路から成
る固体撮像素子に於て、各行の垂直選択線が前記垂直走
査回路と反対側でコントロール・FETのソースに接続
されており、このコントロール・FETはドレイン側が
各垂直選択線に共通のコントロール・ドレインに接続さ
れ、かつゲートが共通のコントロール線に接続されてい
ることを特徴とする固体撮像素子。
In a solid-state imaging device consisting of photoelectric conversion elements arranged in a matrix, vertical switches attached to these photoelectric conversion elements, horizontal switches attached to vertical signal lines, a vertical scanning circuit, and a horizontal scanning circuit, vertical selection lines in each row is connected to the source of a control FET on the side opposite to the vertical scanning circuit, and this control FET has a drain side connected to a control drain common to each vertical selection line, and a gate connected to the common control line. A solid-state image sensor characterized by:
JP60281971A 1985-12-17 1985-12-17 Solid-state image pickup element Pending JPS62141867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60281971A JPS62141867A (en) 1985-12-17 1985-12-17 Solid-state image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60281971A JPS62141867A (en) 1985-12-17 1985-12-17 Solid-state image pickup element

Publications (1)

Publication Number Publication Date
JPS62141867A true JPS62141867A (en) 1987-06-25

Family

ID=17646448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60281971A Pending JPS62141867A (en) 1985-12-17 1985-12-17 Solid-state image pickup element

Country Status (1)

Country Link
JP (1) JPS62141867A (en)

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