JPS62138933A - Interruption control system - Google Patents

Abstract

PURPOSE:To reduce the overhead for detecting an interruption request by scanning the state of an input/output control mechanism by a microprogram when an interruption request from a timer is detected, and initiating an input/output interruption to the program when the input/output interruption request is held. CONSTITUTION:The microprogram is interrupted with an interruption signal 11 from a scanning timer 10 as a start and the microprogram scans the internal registers and internal memory of the input/output control mechanism to check whether or not an interruption request is held; when the holding of the interruption request by either input/output control mechanism is detected, an input/ output interruption is caused to a control program. Namely, interruption request signals sent from the scanning timer 10 and a PIC 12 through signal lines 11 and 14 are gated by AND gates 20 and 21 with independent mask bits 31 and 32 in the interruption mask register 30 in a processor and then inputted to a microsequencer 22.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an interrupt control method for a processing device, and more specifically, the present invention relates to an interrupt control method for a processing device, and more specifically, a method for controlling an interrupt request from an input/output control mechanism without using an interrupt request signal to a processing module. This invention relates to an interrupt control method that makes it possible to transmit information to a program.

[Background of the invention]

In a computer system using a microcomputer, the number of input pins for interrupt signals from outside the microcomputer is limited, so the interrupt signals from each input/output control mechanism are ORed and the signal is sent to the microcomputer. It will be connected to the interrupt signal input pin of

For example, Intel's Microprocessor and Peripheral Handbook (Micr
.

processor and peripheral
Handbook) includes i A P X 286 and P
rogrammable interrupt-Co
n7 roller (hereinafter referred to as rP I CJ)
An application example using the 8259A is introduced, but interrupt requests from each input/output control mechanism are input to the PIC through eight signal lines, and one signal line is output from the PIC to the microcomputer. It is input as an interrupt signal.

Furthermore, as another application example, a method is introduced in which PICs are connected in cascade when there are interrupt requests from nine or more input/output control mechanisms.

However, in reality, there is a limit to the number of signal lines on the bus to which the input/output control mechanism is connected, and it is impossible to increase the number of signal lines for input/output interrupt requests unnecessarily.
Increasing the number of PICs used by cascading PICs increases the amount of hardware, so the number of input/output interrupt request signals that can be used is often limited to about eight.

Therefore, in computer systems that employ this type of interrupt control method, in order to increase the number of connected input/output control mechanisms, the control program handles each input/output without using signal lines to handle interrupt requests from the input/output control mechanisms. A method for detecting by periodically scanning and reading the status register of the control mechanism.% Formula% This method is applicable to input/output control mechanisms that can operate even with relatively slow interrupt responses, but the system To improve throughput, interrupt response as fast as possible is desirable. In order to obtain a fast interrupt response, it is necessary to shorten the above-mentioned scan interval.

The scan interval is usually determined by the interrupt interval from the timer, but if the interval is short, interrupts to the control program will occur frequently, resulting in a very large overhead.

Particularly in complex control programs that support multitasking, this is the entry point for interrupts.

There is a problem in that the overhead of exit processing is usually large, and even if the performance of processing equipment improves, it is difficult to construct a large-scale reproduction system. To solve the above-mentioned problems in conventional interrupt control methods and to reduce the overhead for detecting interrupt requests in a system connected to a human output control mechanism that detects input/output interrupt requests by periodic interrupt scans. The purpose of this invention is to provide an interrupt control method that makes it possible to

[Summary of the invention]

The above object of the present invention is to provide a microprogram-controlled processing device that includes a timer for generating an interrupt request signal to the microprogram at regular intervals, a means for masking the interrupt request signal from the timer, and a program. Means is provided for the microprogram of the processing device to recognize the address of a table prepared in memory and to store the address value, and when the microprogram detects an interrupt request from the timer, the microprogram uses the information in the table. The present invention is characterized in that it scans the status of an input/output control mechanism connected to a processing device to check whether an input/output interrupt request is pending, and if an input/output interrupt request is pending, generates an input/output interrupt in the program. This is achieved through an interrupt control scheme.

Hereinafter, the present invention will be explained in detail based on examples thereof.

[Embodiments of the invention]

FIG. 1 is a block diagram showing a main part of an interrupt control system according to an embodiment of the present invention. In the figure, 1 is a processing device;
2 is the main memory, 3 is the input/output bus, 4 is the input/output control mechanism, 1
o is a scan timer, and 12 is the PIC.

The scan timer 10 is connected to the processing device 1 via the input/output bus 3.
It is possible to write to the timer counter from the timer clock, and when the timer counter counts down at regular intervals and the timer counter value reaches '0'', an interrupt request signal is generated to the processing device 1 via the signal line 11. .

An input/output interrupt request signal 13 connected one-to-one with the one-person output control mechanism is input to the PICI 2 to perform priority control, and an interrupt request signal is sent to the processing device 1 via one person-output interrupt request line 14. It is configured to generate.

Interrupt request signals sent via signal lines 11.14 are processed by AND gates 20.2 by independent mask bits 31.32 in interrupt mask register 30 in processing bag [1].
1 and input to the microsequencer 22. In the microsequencer 22, a branch destination address of the microprogram is generated based on this signal, the address is supplied to the control memory 23, and the microprogram related to each interrupt request is read to the microprogram read register 24. The output of this register 24 is decoded by a decoder 25, and various controls within the processing device 1 are performed based on this.

The interrupt mask register 30 is read by a command issued by a control program stored in the main memory 2, and
Writing is possible and is controlled by a control program such that when the mask bit 31 is 111H, an input/output interrupt request related to the signal 1iA14 is permitted, and when it is IIOII, it is prohibited. The mask bit 32 is a bit for masking the interrupt request signal 11 from the timer 10 for input/output interrupt scan, and the control program allows the interrupt to be enabled when it is "B" and disables the interrupt when it is rr On. controlled by

In this case, the control program is the processing bag v! 11 via the I/O bus 3 from the I/O control mechanism 4 which expects to be read by periodic scanning of registers holding interrupt requests, such as status registers within the I/O control mechanism 4. The above mask bit 32 is used for control to permit or prohibit.

That is, instead of an interrupt occurring directly in the control program triggered by the interrupt request signal 11 from the scan timer 10, an interrupt occurs in the microprogram triggered by the interrupt request signal, and the microprogram is activated by the input/output control mechanism. scans the internal registers and internal memory of the controller to check whether an interrupt request is pending, and enters the control program when it detects that an interrupt request is pending in any of the input/output control mechanisms. This will cause an output interrupt to occur. In the control program, two levels of input/output interrupts related to the interrupt mask bits 31 and 32 are handled separately.

A method for performing an input/output interrupt scan using a microprogram triggered by an interrupt request from the scan timer 10 will be described below.

The input/output interrupt scan by the microprogram is performed based on a scan table set in the main memory 2 by the control program. An example of the contents of the scan table is shown in FIGS. 2(a) to 2(c), and a processing flow of the scan is shown in FIG. 3, respectively.

The control program creates the scan table according to the system configuration, and notifies the microprogram of its starting address using the "set scan table address" command. This instruction has an instruction format as shown in Figure 4, and consists of a ○P code section, a B section that specifies the pace register number, and a D section that specifies the displacement value. Depending on the value,
Specify the start address of the scan table.

When the microprogram detects the above instruction, the value of part B +
The value of the D part is calculated and the result is used as the scan table address 41 in the register file 40 in the processing device 1.
The value is stored in the primary address and held until the above instruction is issued.

After the control program sets the scan table address by issuing the "set scan table address J command," it can start the input/output interrupt scan by the microprogram by setting the mask bit 32 to 11111.

FIG. 2 (,) shows the structure of the scan table, which is composed of a 4-byte x 2 interrupt queue pointer and an 8-byte x n l0C-BLK. The interrupt queue pointer is a pointer for queuing interrupts detected by input/output interrupt scan, and two sets of queue pointers are prepared. FQPTRo, 1
is a pointer indicating the head of the queue, LQPTRo,
1 is a pointer indicating the end of the queue. FQPTRO
, LQPTRO, FQPTRI, and LQPTRI each form a pair.

10C-BLK is provided for each input/output control mechanism where an input/output interrupt scan is executed, and information such as the scan method and the pointer when connected to the queue is stored.
There are two types as shown in FIGS. 2(b) and 2(c).

The first 4 bits of each l0C-BLK are the corresponding l0C-B L
When an interrupt is detected in the scan for K, it is used to identify which of two queues it is connected to, and when it is (0)16, it is connected to the queues indicated by FQPTRO and LQPTRO.

(8) When it is 113, it is connected to the queues indicated by FQPTRI and LQPTRI.

QPTR of bits 59 to 48 of l0C-BLK (7) is a queue pointer and indicates the start address of the ■○C-BLK queued next to the own ■○C-BLK.

For each of FQPTRo, 1; LQPTRo, 1; QPTR, a pointer value is set as a displacement address from the scan table head zero address.

When the value of FQPTRo, 1 is II Ogg, it indicates that the queue is empty.

An example of pointing a queue pointer when connected to an interrupt queue is shown in FIG. Which of the two queues should I queue to?

This is determined systemically by dividing the input/output control mechanisms into two groups: input/output control mechanisms that require relatively fast interrupt responses and input/output control mechanisms that are slow but do not cause system problems. Priority control of interrupts becomes possible by giving priority to the control program and processing queues in which interrupts from input/output control mechanisms that require quick interrupt responses are queued.

There are two types of l0C-BLK as shown in FIGS. 2(b) and 2(c), which are identified by information in bits 47-32. The value of bits 47-36 is (F F F) 1
If it is less than or equal to s, it is of the type shown in FIG. 2(b), and the device number of the input/output control mechanism is stored in bits 47 to 36 of DVN. Therefore, in order to distinguish the device number of DVN=(FFF)1s from the type shown in FIG. 2(c),
Set to not be allocated within the system.

In the type shown in Figure 2(b), FUN in bits 35-32
The section stores a function command for the input/output control mechanism for reading a status register that can identify whether or not an interrupt is pending.

Based on the information in the DVN and FUN sections, the microprogram issues input/output instructions and reads the status register.

The read data is logically ANDed with the CH-IK data of bits 31-16, and it is checked whether the bit that identifies the presence/absence of an interrupt is 111gg. If the result of the AND is 0'', it is determined that the input/output control mechanism does not have an interrupt pending.Furthermore, if it is not rt Ort, it is determined that an interrupt is pending, and the corresponding IOC-B
A queue pointer is set in LK and queued by the method shown in FIG.

At this time, the value of the status register read is I 0C
-B Stored in the RDATA area of LK pins 1-15 to 0, and referenced by the control program as necessary after an input/output interrupt occurs.

In the type shown in FIG. 2(C), bits 47 to 32 are (FF
FO) 1e, and the method to determine whether there is an interrupt is
Read the contents of a specific main memory address and the contents are
This is for the input/output control mechanism depending on whether it is on or not. In this type of input/output control mechanism, a control memory in which the controlware is stored occupies a part of the address space on the main memory 2, and a method is adopted in which the processing device l can read and write from and write to it as part of the main memory 2. ing. In such an input/output control mechanism, the contents of a specific address within the address space are used as an interface area with the processing device 1, and an interrupt request is indicated by the fact that the contents of the interface area of a specific address are not II or OII. It is a method.

Therefore, in order to scan for input/output interrupt requests, it is necessary to periodically read the address and check the value. ■○C-BLK of the type shown in Figure 2 (c)
In this case, the M A DR of pins 1-31 to 0 stores a specific 71-res value that becomes the interface area. The microprogram reads the value of M A DR and
Reads the contents of the main memory at the address indicated by 11014
It is checked whether there is an interrupt request or not. When there is an interrupt, a queue pointer is set for the corresponding ■○C-BLK using the method shown in FIG. 5, and the queue is inked.

By the way, the value of bits 47 to 32 of l0C-BLK is (
FFFI) IG, the microprogram is
Skip scanning for QC-BLK. This is because when a failure occurs in the input/output control mechanism to be scanned, the system may switch off the input/output control mechanism, but in such cases, the scan table must be restarted. Bit 47 of l0C-BLK corresponding to such input/output control mechanism without further explanation.
By setting .about.32 to (FFFI)1s, it is possible to exclude it from the scan target.

■○The value of bits 47 to 36 of C-BLK is (F F F
)z s, the value of bits 35-32 is (0)1e,
(1) For throats other than 1e, so 0') IOC-BLK
is regarded as the final scan instruction block, and the scan ends. At the end of the scan, the microprogram reads FQPTRo in the scan table.

1 is checked, and if either is not II OH, an input/output interrupt is generated to the control program as an interrupt detection.

When an input/output interrupt occurs, the control program refers to FQPTRo, 1 in the scan table to identify which input/output control mechanism the interrupt is from, and starts an appropriate interrupt handling routine. Further, the control program sets the mask bit 32 in the processing device I to 0'' to prohibit scanning from the occurrence of the input/output interrupt until the end of the interrupt processing.

In addition, the control program interrupts pending interrupt l0C-BLK.
When the interrupt processing for is completed, the queue pointer is updated and the corresponding l0C-BLK is removed from the queue, and then the mask bit 32 in the processing device 1 is set to 1''. The mask bits 1 to 32 are set to ``1''. The method is to load P SW (
This is done by an instruction such as the Program St, atus Word) instruction. When the microprogram processes instructions issued by the control program, mask bit 3 is set.
Always check whether 2 has been changed to 1'' and 111
F in the scan table that is required when changing to 11
The value of QPTRo, 1 is checked, and if it is not 0'', an input/output interrupt is generated in the control program.

By this operation, the plurality of interrupt causes in the interrupt queue are transmitted to the control program and processed without being lost.

The process described above is shown in FIG. 3 as a broach yard.

〔Effect of the invention〕

As explained above, according to the present invention, even when using an input/output control mechanism that detects whether or not an interrupt is pending by performing an interrupt scan for the input/output control mechanism from a processing device, the By applying a timer interrupt to the control program, it becomes possible to perform interrupt scanning by a microprogram without performing interrupt scanning by the control program, and the overhead of the control program can be reduced.

In addition, the interface between the microprogram and the control block can be made flexible and independent of the system configuration by using a table.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 2(a) to 2(C) are diagrams showing the structure of the scan table, FIG. 3 is a flowchart of the scan operation by the microprogram, FIG. 4 is a diagram showing the command format for setting the scan table address, and FIG. FIG. 5 is a diagram showing the queue structure within the scan table. 1: processing unit, 2: main memory, 3: input/output bus. 4: Input/output control mechanism, 10: Scan timer, 12: P
IC12Q, 21: AND gate, 22: Micro sequencer, 30: Interrupt mask register, 31, 32: Interrupt mask bit, 40.50? register file. Figure 2 (a) Figure 3

Claims (1)

[Claims] (1) A timer for generating an interrupt request signal to the microprogram at regular intervals in a microprogram-controlled processing device, a means for masking the interrupt request signal from the timer, and a program prepared on the main memory. Means is provided for the microprogram of the processing device to recognize the address of the table and store the address value, and when the microprogram detects an interrupt request from the timer, the microprogram is connected to the processing device based on the information in the table. An interrupt control method characterized by scanning the status of an input/output control mechanism to check whether an input/output interrupt request is pending, and generating an input/output interrupt in a program if an input/output interrupt request is pending.