JPS62138328U - - Google Patents
Info
- Publication number
- JPS62138328U JPS62138328U JP2726086U JP2726086U JPS62138328U JP S62138328 U JPS62138328 U JP S62138328U JP 2726086 U JP2726086 U JP 2726086U JP 2726086 U JP2726086 U JP 2726086U JP S62138328 U JPS62138328 U JP S62138328U
- Authority
- JP
- Japan
- Prior art keywords
- dropout
- circuit
- abnormal noise
- modulation
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Description
第１図は本考案の一実施例のＣＵＥ記録再生回
路の構成図、第２図は従来のＣＵＥ記録再生回路
の構成図である。
図において、２はパルス幅変調回路、４は録音
ヘツド、５は磁気テープ、６は再生ヘツド、７は
再生信号増幅整形回路、１０はカウンタ回路、１
１は比較器、１２は前値保持回路、１４は乗算器
、１７は音声出力端子である。各図中の同一符号
は同一又は相当部分を示す。
FIG. 1 is a block diagram of a CUE recording and reproducing circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional CUE recording and reproducing circuit. In the figure, 2 is a pulse width modulation circuit, 4 is a recording head, 5 is a magnetic tape, 6 is a playback head, 7 is a playback signal amplification and shaping circuit, 10 is a counter circuit, 1
1 is a comparator, 12 is a previous value holding circuit, 14 is a multiplier, and 17 is an audio output terminal. The same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
する磁気録音機のパルス幅変調の変調率を一定の
範囲内に制限する変調回路と、再生波形の変調率
が前記の一定の範囲を超えるとき、これをテープ
のドロツプアウト又は異音として検出する比較器
と、ドロツプアウト、異音に対してはそれ以前の
再生波形を保持する前値保持回路と、前値保持値
に対してドロツプアウト又は異音の継続時間に応
じた値を掛ける乗算回路とを備えたＣＵＥ再生回
路。 A modulation circuit that limits the modulation rate of pulse width modulation of a magnetic recorder that records and reproduces CUE signals using a pulse width modulation method within a certain range, and when the modulation rate of the reproduced waveform exceeds the above certain range. A comparator that detects dropout or abnormal noise as tape dropout or abnormal noise, a previous value holding circuit that holds the previous playback waveform for dropout or abnormal noise, and a previous value holding circuit that maintains the previous value holding value and the duration of dropout or abnormal noise. A CUE reproduction circuit comprising a multiplication circuit that multiplies a value according to the value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2726086U JPS62138328U (en) | 1986-02-24 | 1986-02-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2726086U JPS62138328U (en) | 1986-02-24 | 1986-02-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62138328U true JPS62138328U (en) | 1987-09-01 |
Family
ID=30829118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2726086U Pending JPS62138328U (en) | 1986-02-24 | 1986-02-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62138328U (en) |
-
1986
- 1986-02-24 JP JP2726086U patent/JPS62138328U/ja active Pending
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