JPS62137979A - Smear correcting circuit - Google Patents

Abstract

PURPOSE:To perform smear correction with high precision by allowing an image pickup signal, which is outputted one field ahead of a smear component obtained in a vertical ineffective period, to pass a delay circuit to solve the lag. CONSTITUTION:The output from a solid-state image sensor 1 is supplied to an A/D converter 4 through a sampling and holding circuit 2, etc., and is converted to a digital signal. This signal is supplied to a field memory 5, and an image pickup signal So outputted in a vertical effective period Ta is written successively and is read and outputted successively after the period corresponding to one field. The digital signal is supplied to a line memory 8 through an adder 7, and a smear component Sm outputted in a vertical ineffective period Te is written. The image pickup signal So is supplied to a subtractor 9, and contents of the line memory 8 are read out and are supplied to the subtractor 9 through a gain control circuit 10. Thus, an image pickup signal S deg.' where the smear component Sm is eliminated is obtained from the subtractor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is suitable for application to a solid-state imaging device configured using a solid-state image sensor formed of, for example, COD (component coupling device). This invention relates to a smear correction circuit.

[Summary of the invention]

The present invention provides a smear correction circuit that removes a smear component by subtracting the thesmia component from an imaging signal from a solid-state image sensor. By passing the signal through a delay circuit and eliminating the time lag between the two, highly accurate smear correction is made possible.

[Conventional technology]

2. Description of the Related Art Conventionally, solid-state imaging devices have been proposed that are configured using nine solid-state image sensors formed of, for example, CCDs (charge-coupled devices). In this solid-state image sensor, it is important to remove smear components that are mixed into image signals during vertical transfer in order to improve image quality.

Conventionally, to remove this smear component, the smear component output during the vertical blank feed period was stored in a line memory, and the output of the line memory was subtracted for each line signal of the imaging signal from the solid-state image sensor. It has been proposed to do so, for example, as described in Japanese Patent Laid-Open No. 52-64219.

[Problem that the invention seeks to solve]

However, according to the conventional method described above, the imaging signal from the solid-state image sensor is one field ahead of the smear component output from the line memory. Therefore, there is no problem with a still screen, but when the smear portion moves due to nosonning, etc., the edge portion becomes over-corrected or under-corrected, making it impossible to perform highly accurate smear correction.

In view of this point, the present invention enables highly accurate smear correction.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides an imaging signal S output from the solid-state image sensor (1) during the vertical effective period.

A delay circuit (5) that delays the entire one field period, and a line memory (8) that stores the smear component Sm output by the solid-state image sensor (1) during the vertical blank feed period Te following the vertical effective period TIL. The smear component 5111 is removed from the image signal S0 by subtracting the smear component Sm, which is the output of the line memory (8), for each line signal of the image signal S0 output from the delay circuit (5). be.

[Effect]

In the above configuration, the image signal S0 is processed by the delay circuit (5).
Since it is delayed by a field period, the smear component Sm output from the imaging signal S0 trine memory (8) is of the same field, and the time difference between the two is eliminated.

〔Example〕

Below is Figure 1? An embodiment of the present invention will be described with reference to the following.

In the figure, (1) is a solid-state image sensor, for example, a well-known interline transfer type COD image sensor as shown in FIG. 2 is used.

In Figure 2, (c) is each light receiving unit arranged in a matrix pattern corresponding to each pixel in an odd field, and (b) is a light receiving part arranged in a matrix pattern corresponding to each pixel in an even field. (c) is each vertical transfer register section provided along the vertical row of the above-mentioned light receiving sections (H), and (c) is the vertical transfer register section (c) of the vertical transfer register section (c). There is a horizontal transfer renostar section provided on the output side, and (
C) and (C) are transfer dart sections provided between the light receiving sections (C) and (A) and the vertical transfer register section (C).

Based on the vertical synchronization signal, transfer r-g (a) and (c) of the solid-state image sensor (1) are opened at the beginning of odd and even fields, and each light receiving part Q
The signal loads of the odd and even fields obtained in 1) and (a) are transferred to the vertical transfer register section (2). Then, the signal charge transferred to the vertical transfer register section @ at the beginning of each field is transferred to the horizontal transfer register section (incorporated) for one horizontal line every horizontal period by the vertical E1m feed lock synchronized with the horizontal synchronization signal. The 111st transfer is carried out, and the Ilt'
It is read nth time. That is, the horizontal transfer register section (c) outputs the image signal.

It should be noted that Fig. 2 is a simplified diagram, and in reality, for example, 247 (ff11) light-receiving parts are arranged in the vertical direction.For example, 768 light-receiving parts are arranged in the horizontal direction. For example, 246 pieces are arranged in the horizontal direction, and 768 pieces are arranged in the horizontal direction.Therefore, in the solid-state image sensor (1), the NT
In the SC method (525 horizontal periods/frame), the 247 horizontal periods of odd fields are the vertical effective period Ta,
The 16 horizontal periods that follow this are the vertical air transport period T6,
Furthermore, the 246 horizontal periods of the even field are set as the vertical valid period T, and the subsequent 16 horizontal periods are set as the vertical blank feed period T0. Vertical validity period T.

, the imaging signal S0 is output, and the vertical blank feed period T
6, for example, the smear component Sm is output.

Further, a color filter (IA) as shown in FIG. 3 is disposed in front of the solid-state image sensor (1), and the output of the solid-state image sensor (1) is a dot-sequential signal of red, green, and blue.

Returning to FIG. 1, the signals from the solid-state image sensor (1) are supplied to the output sensor hold circuit (2), and the signals obtained from each light receiving section are sampled and held.
The signal is supplied to a converter (4) via a C amplifier (3) and converted into a digital signal. Then, the output of the solid-state image sensor (1) converted into a digital signal is supplied to a field memory (5), and an imaging signal S is outputted during the vertical effective period T3. are sequentially written and sequentially read out and output after one field period. That is, this field memory (5) functions as a delay circuit that delays the delay time of one field period. This field memory (5) is controlled by a control circuit (6).

Further, the output of the solid-state image sensor (1) converted into a digital signal by the A/D converter (4) is supplied to the line memory (8) via the adder (7), and the output is supplied to the line memory (8) during the vertical idle feed period T.

The smear component Srn output to is written. In this case, the line memory (8) has, for example, a shift register configuration, and its output is supplied to the adder (7), and the smear components Sm for, for example, 8 lines of vertical @ idle feed period T0 are sequentially added and accumulated. It is stored in the line memory (8). Like this? By multiplying by 3, the smear component Sm can be made good in s, ''N'6. For example, as described above, if 8 lines are added and accumulated, the smear component Sm will be 8 times as large, and the noise component will be multiplied by F. Note that the line memory (8) is controlled by a control circuit (6).

Further, the image signal S0 of one field before from the field memory (5) is supplied to the subtracter (9). In addition, in synchronization with each line signal of this image pickup signal S0, the stored content (smear component Sm) of the line memory (8) is repeatedly read out and reduced to, for example, 1/8 by the r-in control circuit←1. After that, it is supplied to a subtracter (9). therefore,
The subtracter (9) outputs the image signal S from which the smear component Sm has been removed. ′ is obtained.

Also, an image signal S obtained from a subtracter (9). ' is supplied to the launch circuit α°C. Imaging signal S. As mentioned above, l is a red, green, and blue point sequential signal, and in the latch circuit α, it is sequentially latched at each color signal position based on the control of the control circuit (6), and the red signal is ,
Primary color signals R%G and B for green and back are output. These primary color signals R, G, and B are transmitted through φ converters (1 (G), (12G),
(12B), the signal is converted into an analog signal and then supplied to the matrix circuit (1υ) via the white balance amplifier αJ and gamma correction circuit α. signal R-Y,
The blue difference signal B-Y is supplied to a color encoder αQ,
From this color encoder 0Q to the terminal α force, for example, NT
An SC-based composite color video signal Sv is output.

In the above configuration, when the imaging signal S0 and the smear component Sm of the N-th field and the N+1-th field are shown in FIG. signal S0
is for the Nth field, as shown in FIG. Furthermore, the smear component Sm supplied from the line memory (8) to the subtracter (9) via the r-in control circuit (11) is of the Nth field as shown in FIG. 9), an imaging signal S.' from which the smear component has been completely removed is obtained as shown in the same figure.In the past, the smear component Sm of the Nth field is obtained from the imaging signal S0 of the N+1th field. Since the image signal is subtracted, the image signal after the subtraction becomes as shown in E of the same figure, and the edge portion is over-corrected or under-corrected.

According to this example, the image signal S0 is delayed by one field period in the field memory (5), so the image signal S0 and the smear component Sm output from the line memory (8) are from the same field. As a result, the time difference between the two is eliminated. Therefore, even when there is movement,
Highly accurate smear correction can be performed.

Although the above-mentioned embodiment is an example in which the solid-state image sensor is applied to an interline transfer type solid-state image sensor, it can be similarly applied to a frame transfer type solid-state image sensor. Furthermore, although the above-mentioned embodiment is an example in which the solid-state image sensor (1) is formed using COD, the present invention is applicable to a case in which it is used on another solid-state image sensor formed using MOS or the like. The same can be applied to

Furthermore, in the above embodiment, the output of the line memory (8) is supplied to the full adder (7) to accumulate and add, for example, 8 lines worth of smear components Sm. It is also possible to stop the horizontal transfer register unit 0, perform accumulation and addition, and then write to the line memory (8).

In addition, in the above embodiment, ~Φ
Although the converters (12R), (12G), and (12B) are arranged, digital processing may be performed up to the color encoder αQ, and a φ converter may be arranged on the output side of the color encoder α0.

Further, the field memory (5) of the above embodiment can be used not only as a delay circuit but also for multiple purposes such as performing defect compensation two-dimensionally.

〔Effect of the invention〕

According to the present invention described above, the imaging signal is delayed by one field period in the delay circuit, and the imaging signal and the smear component output from the line memory are from the same field, so that the time difference between the two is eliminated. Therefore, highly accurate smear correction can be performed even when there is movement.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of an example of a solid-state image sensor, Fig. 3 is a configuration of a color filter, and Fig. 4 is an explanation of the example shown in Fig. 1. FIG. (1) is a solid-state image sensor, and (5) is a field memo! j, (6) is the control circuit, (7) is the adder, (
8) is a line memory, (9) is a subtracter, and 01 is a gain control circuit. Agent Mamukai Ito
Hidemori Matsuzumi Procedural Amendment Written January 20, 1986 Michibe Uga, Commissioner of the Patent Office 1, Display of $ 1985 Patent Application No. 27976.5 3, Relationship with the case of the person making the amendment Patent application Address: 6-7-35, Kitashina-yo, Kitahin-yo-ku, Tokyo 6 Number of inventions increased by the amendment 8 Contents of the amendment (1) In the specification, page 9, line 1, page 11, lines 7 and 9
Correct the lines rA/DJ to rD/AJ. (2) In the drawings, Figure 1 will be corrected as shown in the attached sheet. that's all

Claims (1)

[Claims] a delay circuit that delays an imaging signal output from the solid-state image sensor during a vertical effective period by one field period; and a line that stores a smear component that is output from the solid-state image sensor during a vertical blank feed period following the vertical effective period. 1. A smear correction circuit, comprising a memory, for removing a smear component from the image pickup signal by subtracting the output of the line memory for each line signal of the image pickup signal output from the delay circuit.