JPS62134899A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent access to a semiconductor storage device having a redundancy memory cell from being delayed by controlling gates and a switching element with the outputs of a redundancy decoder and a decoder and allowing or inhibiting the output of a clock. CONSTITUTION:When an address corresponding to a defective memory cell is inputted, selection and nonselection outputs of the redundancy decoder 1 and decoder 4 are H and L respectively. Consequently, switching transistors (TR) 3 and 5 turn on and off respectively and a clock phiA is outputted from the TR 3 to a redundancy bit line or word line and outputted to neither a bit line nor a word line. At the same time, when an AND gate 6 is opened and a clock phi2 goes up to H according to a clock phi1, a gate 7 is closed with the inverted clock phi2 and the clock phi1 is not supplied to the TR5. When the decoders 1 and 4 are selected and unselected, the clock phi2 goes down to L regardless of the clock phi1, the gate 7 is opened and the clock phiA is outputted through the TR 5 immediately, thereby preventing access from being delayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to the configuration of a decoder section of a semiconductor memory device having redundant memory cells.

[Prior Art] FIG. 5 is a circuit diagram of a decoder section of a conventional semiconductor memory device having redundant memory cells. First, the configuration of this decoder section will be explained. In the figure, A+, A+,
A2, A2, -Ao, and An are input address signals. On the input side of the redundant decoder 1, there are program elements "+", bI +a2 +b2 corresponding to each address signal.
, "'a1+, b4 are provided. These programming elements are programmed, for example, by blowing them out with a laser. That is, if there is a defective memory cell among a plurality of memory cells (not shown), In case,
Address signal A1, A+ -A2, A2,'=An
, An to input an address signal corresponding to a defective memory cell among the program elements a, dregs 4, program elements a2 or b2, and . . . program element a. Lend. By blowing out the defective memory cell, it is possible to replace the defective memory cell with a normal memory cell (not shown). The output side of the redundant decoder 1 is connected to one side input of an AND gate 6, and a MOS l-transistor 3 for selecting a redundant bit line or driving a redundant word line.
connected to the gate.

Redundant decoder 1 outputs an output signal Φs1, and this signal controls on/off of MOS transistor 3.

A clock signal Φ is applied to the other input of the AND gate 6. This clock signal Φ is a signal that rises whenever an address signal is input to the redundant decoder 1 and the output of this decoder is determined. The drain of the MOS t-transistor 3 is connected to the drain of a MOS transistor 5 for normal bit line selection or normal word line driving. A clock signal Φ6 for bit line or word line selection is applied to the drain of MOS transistor 3.

This clock signal Φ8 rises after the output of the regular decoder 4 is determined. The source of the MOS transistor 3 is connected to a bit line selection or word line driving signal line of the redundant memory cell. Φt2 is a clock signal for redundant bit line selection or redundant word line driving. AN
The output side of the D gate 6 is connected to the input side of the regular decoder 4. AND gate 6 generates a clock signal Φ2 that makes the output of regular decoder 4 non-selected when redundant decoder 1 is in the selected state, that is, inhibits regular bit line selection or regular word line driving. A1. A2
．． . . A+ . . . A is an address signal input to the regular decoder 4, and for example, A1 indicates A or skin.

The output side of the regular decoder 4 is a MOS t-transistor 5.
connected to the gate. The regular decoder 4 outputs an output signal Φi, and this signal controls the on/off of the MOS transistor 5. The source of the MOS transistor 5 is connected to a signal line for bit line selection or word line driving of a regular memory cell. Φ12 is a clock signal for normal bit line selection or normal word line driving.

6 is a waveform diagram of each signal when the output of redundant decoder 1 is in a non-selected state in the circuit of FIG. 5, and FIG. 7 is a waveform diagram of each signal when the output of redundant decoder 1 is in a selected state in the circuit of FIG. FIG. 4 is a waveform diagram of each signal at the time of FIG.

Next, the operation of this decoder section will be explained with reference to FIGS. 6 and 7. Now, program element al of redundant decoder 1 +b1'+a2 +b2 +"'a
. , b9 is not programmed, or the program element a4. b1. a2.1)2,”'an,I
nn ff170 If the input address signal is different from this programmed value, the output of the redundant decoder 1 becomes a non-selected state, and as shown in FIG. ．． is it L
Since the clock signal Φ2 is the output of the AND gate 6 which inputs the output signal Φs1 and the clock signal Φ, the clock signal Φ.

It becomes "L" level regardless of the state of. therefore,
The output of the regular decoder 4 is that all input address signals are “
When it is at L'' level, it is in the selected state, and the output signal Φi is at H'' level. Therefore, MOS transistor 3
The gate of MOS transistor 5 is at "L" level, and the gate of MOS transistor 5 is at "H" level, and when clock signal Φ8 is raised, clock signal Φ12 becomes "H" level, but clock signal Φ,2 is at "H" level. It remains at L'' level, a regular bit line is selected or a regular word line is driven, and a redundant bit line is selected or a redundant word line is not driven.On the other hand, when the output of the redundant decoder 1 is in the selected state , as shown in Fig. 7, the output signal Φ5. is a "tabil bell", so when the clock signal Φ rises, the clock signal Φ2 also rises, and the output of the regular decoder 4 is in the non-selected state, that is, the output, regardless of its input address signal. The signal Φi becomes "L" level. Therefore, the gate of MO8t-transistor 3 becomes "H" level,
The gate of MOS transistor 5 is at °゛L''L'' level,
If the clock signal Φ is raised here, the clock signal Φ
92 rises, but the clock signal ΦM2 remains at the "L" level, the redundant bit line is selected or the redundant word line is driven, and the normal bit line of the defective memory cell is not selected or the normal word line is not driven.

[Problems to be Solved by the Invention] Since the conventional semiconductor memory device having redundant memory cells is configured as described above, the clock signal Φ2 is determined after the output of the redundant decoder 1 is determined, and then the output of the regular decoder is determined. 4 is determined, it is necessary to take more time to raise the clock signal Φ after the address signal is determined than in a semiconductor memory device that does not have redundant memory cells. There was a problem with the delay.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device having redundant memory cells that does not cause delays in access time.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has a first switching element that outputs a first clock signal for selecting a bit line of a redundant memory cell or The first clock signal is output to the word line driving signal line, and when the output of the redundant decoder is in a non-selected state, the first clock signal is controlled not to be output to the bit line selection or word line driving signal line of the redundant memory cell. When the output of the regular decoder is in the selected state, the second switching element outputs the first clock signal to the bit line selection or word line driving signal line of the regular memory cell, and when the output of the regular decoder is in the non-selected state. When the output of the redundant decoder is in the selected state, the first clock signal is controlled not to be output to the bit line selection or word line driving signal line of the correct memory cell. The output of the first clock signal to the second switching element is prohibited by the output of the second switching element.

[Operation] In the present invention, when the output of the redundant decoder is in the selected state, the bit line of the redundant memory cell is selected or the word line is driven. At this time, the inhibiting means causes the redundant decoder to output the second clock signal of the first clock signal.
Since the output to the switching element is prohibited, the normal bit line of the defective memory cell is not selected or the normal word line is not driven.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a circuit diagram of a decoder section of a semiconductor memory device having redundant memory cells, which is an embodiment of the present invention. The structure of this decoder section differs from the structure of the decoder section shown in FIG. 1 in the following points. That is, the gate 7 is newly provided, the output side of the AND gate 6 is connected to one inverting input side of the gate 7, and the clock signal Φ for bit line or word line selection is connected to the normal bit line selection or the normal one. It is not applied to the drain of word line driving MOS transistor 5, but is applied to the other input side of gate 7. Also,
The output side of gate 7 is connected to the drain of MOS transistor 5. The gate 7 outputs a clock signal ΦB for normal bit line selection or normal word line driving from the clock signal Φ2 and the clock signal Φ, which inhibit normal bit line selection or normal word line driving.

FIG. 2 is a waveform diagram of each signal when the output of redundant decoder 1 is in a non-selected state in the circuit shown in FIG. 1, and FIG. 3 is a waveform diagram of each signal when the output of redundant decoder 1 is in a selected state in the circuit shown in FIG. FIG. 3 is a waveform diagram of each signal.

Next, we will explain the operation of this decoder section in Figures 2 and 3.
This will be explained with reference to the figures. Now, program element aI +bl +a2 *b2 +... of redundant decoder 1
If aII ebn is not programmed, program elements al, bI *a2 eb2 *”'
an Jn is programmed, when the input address signal is different from this programmed value, the redundant decoder 1 becomes a non-selected state, and as shown in FIG. 2, the output signal Φ9. is “L” level, and the clock signal Φ2 is the output signal Φ,1 and the clock signal Φ
Since it is the output of the AND gate 6 which takes inputs as inputs, it remains at "L" level even if the clock signal Φ rises, and this signal is input to the gate 7, so when the clock signal Φ rises, the gate 7 The clock signal ΦB from ΦB also rises. At this time, if all the input address signals to the regular decoder 4 are at the "Yes" level, the output of this regular decoder 4 becomes the selected state, its output signal Φ11 goes to the "H" level, and the clock signal ΦB becomes the "H" level. When it rises, the output signal Φi also rises, and the normal bit line connected to the source of the MOS transistor 5 is selected or the normal word line is driven. Furthermore, if the address signal input to the redundant decoder 1 matches the programmed value, the output signal Φ$ of the redundant decoder 1 will be “H”.
When the clock signal Φ, rises, the clock signal Φ,2 rises, and the MOS transistor 3
A redundant bit line connected to the drain of the redundant bit line is selected or a redundant word line is driven. On the other hand, when the clock signal Φ rises, the clock signal Φ2 also rises,
After that, even if the clock signal Φ8 rises, the clock signal Φa remains at "L" level, and even if the output of the normal decoder 4 becomes the selected state, the clock signal Φh remains at the "L" level, and the MOS The normal bit line of the defective memory cell connected to the source of transistor 5 is not selected or the normal word line is not driven.

In the above embodiment, the programming of the redundant decoder 1 is performed by cutting out the program element with a laser. However, the program element may be electrically cut out, or a non-volatile A semiconductor memory element may also be used.

Further, in the above embodiment, a negative logic NAND gate is used as the decoder type, but the decoder type may be other types.

Further, in the above embodiment, the case where the AND gate 6 and the gate 7 are used to generate the clock signal ΦB for normal bit line selection or normal word line driving is shown.
As shown in FIG. 4, the output signal of the gate 8 which receives the inverted signal of the output signal of the redundant decoder 1 and the clock signal Φ8 for bit line or word line driving is used to select the normal bit line or drive the normal word line. It may also be used as a clock signal for

[Effects of the Invention] As described above, according to the present invention, when the output of the redundant decoder is in the selected state, the first switching element causes the first clock signal to be used for selecting the bit line of the redundant memory cell or for driving the word line. the first clock signal is output to the signal line, and when the output of the redundant decoder is in a non-selected state, the first clock signal is controlled not to be output to the bit line selection or word line driving signal line of the redundant memory cell; Therefore, when the output of the regular decoder is in the selected state, the first
The first clock signal is output to the bit line selection or word line driving signal line of the regular memory cell, and when the output of the regular decoder is in a non-selected state, the first clock signal is output to the bit line selection of the regular memory cell. Alternatively, the output of the first clock signal to the second switching element is prohibited by the output of the redundant decoder when the output of the redundant decoder is in the selected state by the inhibiting means. As a result, it is possible to obtain a semiconductor memory device having redundant memory cells that does not cause delay in access time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a decoder section of a semiconductor memory device having redundant memory cells, which is an embodiment of the present invention. FIG. 2 is a waveform diagram of each signal when the output of the redundant decoder is in a non-selected state in the circuit of FIG. 1, and FIG.
FIG. 6 is a waveform diagram of each signal when the output of the redundant decoder is in a selected state in the circuit shown in the figure. FIG. 4 is a circuit diagram of a decoder section of a semiconductor memory device having redundant memory cells, which is another embodiment of the present invention. FIG. 5 is a circuit diagram of a decoder section of a conventional semiconductor memory device having redundant memory cells. 6 is a waveform diagram of each signal when the output of the redundant decoder is in a non-selected state in the circuit of FIG. 5, and FIG.
FIG. 6 is a waveform diagram of each signal when the output of the redundant decoder is in a selected state in the circuit shown in the figure. In the figure, 1 is a redundant decoder, 4 is a regular decoder,
3 and 5 are MOS transistors, 6 is an AND gate, and 7.
8 is the gate, a, ~a Il, b, ~b. are program elements, A, ~A,, A, ~A n. A, ~A, are address signals. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A plurality of normal memory cells and at least one redundant memory cell are provided, and when there is a defective memory cell among the plurality of normal memory cells, access to the defective memory cell is prohibited. A semiconductor memory device that replaces the defective memory cell with the redundant memory cell, which includes a regular decoder that decodes the input address signal, and a normal decoder that decodes the input address signal, and a normal decoder that decodes the defective memory cell among the address signals on the input side. a redundant decoder for a redundant memory cell having a programming element for inputting an address signal corresponding to a memory cell and decoding the address signal inputted via the programming element; and a selection state of an output of the redundant decoder. or a first clock signal generating means for generating a first clock signal after the non-selected state is determined; and performing an opening/closing operation in response to the output of the redundant decoder;
When the output of the redundant decoder is in the selected state, the first
The first clock signal is outputted to the bit line selection or word line driving signal line of the redundant memory cell, and when the output of the redundant decoder is in a non-selected state, the first clock signal is outputted to the bit line selection or word line driving signal line of the redundant memory cell. a first switching element configured to control the signal line so as not to be output to a word line driving signal line; 1 clock signal is output to the bit line selection or word line driving signal line of the regular memory cell, and when the output of the regular decoder is in a non-selected state, the first clock signal is output to the bit line selection or word line driving signal line of the regular memory cell. between the redundant decoder and the first clock signal generation means, and the second switching element, the second switching element controls not to output to the bit line selection or word line driving signal line; Interposed,
and prohibiting means for inhibiting output of the first clock signal to the second switching element by the output of the redundant decoder when the output of the redundant decoder is in a selected state. (2) Further, a second clock signal generating means generates a second clock signal having a large driving capability after determining the selected state or non-selected state of the output of the redundant decoder and before generating the first clock signal. and an AND circuit interposed between the redundant decoder and the second clock signal generating means, and the inhibiting means, and generating a logical product of the redundant decoder output signal and the second clock signal. 2. The semiconductor memory device according to claim 1, wherein said inhibiting means is driven by said AND circuit output signal.