JPS62134883A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To use memory space efficiently by setting the total number of bits of different kinds of memories which differ in capacity to 2n and varying the address space that a memory cell occupies on a programmable basis when using the different kinds of memories on the same substrate. CONSTITUTION:Two hundreds fifty six bytes of an 8K byte memory 14 of a semiconductor memory device are assigned to a shadow RAM 14a and 7936 bytes are assigned to a normal RAM 14b. In this case, a backup is assigned only from the start address and the flexibility of constitution is deficient. For example, when a stack area backup is mode, there is a backup preferably in the intermediate area of the memory. For the purpose, scramblers 150-1513 for address scrambling are provided. Those circuits are used and an external address input Ai is inverted freely or not inverted into an input Ai based on a program value in a storage element.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which different types of memory cells are mounted on the same chip, and is particularly used in peripheral devices of microcombiners. It is something.

[Technical background of the invention and its problems]

Conventionally, as this type of semiconductor memory device, for example, a combination of a shadow RAM (or a tile RAM) and a RAM is known. Shadow RAM or Nouvra Tile RAM (Nonvo-1atil)
e RAM) has 70 rips in one cell! (R
AM section) and KEPROM (Electrically
Erasa-ble Programrnable
Normal operation is performed in the RAM section, and when it is necessary to store data, such as in the case of an abnormal power supply, the data is saved in the EEPROM.

Shadow RAM and Neugeratile RAM each have the characteristics of RAM's high-speed operation and unlimited number of data rewrites, and the non-volatility of EgPROM, making them ideal as the ultimate form of semiconductor storage devices. close. However, since the cell size is very large, it is difficult to expect an increase in the degree of integration compared to general RAMs and EEPROMs, and high integration is delayed. For example, at present, the storage capacity of static RAM is 64) (8/<
In contrast, in shadow RAM, it is about an IK pit (128 bytes).

By the way, Shadow RAM's application cage data include Ininya Rise Routine and Nooru Meter Backup!
, stack, etc., but the capacity does not necessarily need to be large. For example, an 8-bit microprocessor Z (6
If a 64-bit static RAM (121 to 128) is connected to a 4-byte memory space, the result will be as shown in Figure 6(a), but if an IK-bit shadow RAM 13 is connected to this, the result will be as follows: The result will be as shown in FIG. 6(b) or FIG. 6(c). However, in the case of figure (b), the number of devices is eight, same as in figure (a), but 7 bytes of memory space are wasted. On the other hand, in the configuration shown in FIG. 3(e), although the memory space can be effectively utilized, the number of ICs increases, which increases the cost of the entire system and deteriorates portability.

Of course, it is possible to allocate a part of the RAM space to RAM K, but this requires adding an external logic circuit to invalidate a part of the RAM space, which complicates the system configuration. .

The above-mentioned problem will not change even if the memory capacity increases, as long as the cell size ratio between RAM and shadow RAM does not change! It does not depend on the bit number of the processor 11. This is the fate of nine systems that combine different types of memory with different capacities.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a semiconductor memory device that enables efficient use of memory space when using different types of memories with different capacities, and that can reduce cost and physical amount.

[Summary of the invention]

That is, in this invention, in order to achieve the above object, when two or more types of memories with different cell sizes are arranged on the same substrate, the total number of bits (excluding memory for redundant circuits) is The sum is 2'' (n: integer), and the address space occupied by a predetermined type of memory cell can be changed programmably.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor memory device that combines a RAM and a shadow RAM. Of the 8 bytes of memory 14, 256 bytes are allocated to shadow RAM 14a, and the other 7936 bytes are normal RAM.
14 b. By combining two types of devices on the same chip with such a capacity ratio, it is possible to eliminate wasted areas of memory space as shown in FIGS. 6(b) and 6(c). However, as it stands, backups are allocated only from the first address, which lacks flexibility in terms of system configuration. That is, in the case of the initialization routine of a microcomputer, it is desirable to have a backup from ``@oooo'', but for example, if you want to back up the stack area, it is better to have it in the intermediate area of the memory.

In order to meet such a request, a ninth address scrambling block 215o-15,s is provided. These scramblers 158-154. For example, an exclusive or dart is used, and as shown in FIG. Then, the actual internal address input At' may be used. By using such a circuit, it is possible to freely invert or non-invert the external address input λ1 and use it as the internal address input Ai9 based on the programmed value of the storage element (for example, FEFROM, etc.).

Next, the above-mentioned address scrambling will be explained in detail with reference to FIG. Now, there are 4 blocks of memory cell area 18. ~184 exists 9, first block 18.
is stored in the shadow RAM in the second to fourth blocks 182.
~184 is allocated to RAM, then (x
, xo)=(00), the first block 181 becomes a shadow RAM, which is suitable for use as a backup for initialization routines and the like. On the other hand, (xlxo
)=(01) and (xlxo)=(10), when viewed from the outside, the sha P-■ area 18 is the second
Alternatively, it is equivalent to existing in the third area 18□, 183, and is optimal for holding data such as a noclameter.

Moreover, in the case of (xlxo)=(11), the shadow R
This is equivalent to the AM area 181 existing in the rear part 184, and is suitable for backing up the stack, etc. You can eliminate the area.

Furthermore, by performing address scrambling, it is possible to allocate a certain type of memory to an optimal position suitable for the system.

FIGS. 4(a), 4(b) are for explaining another embodiment of the present invention, and show the LSB and MS of the address.
B can be changed using a program element. (a) In the figure, 191 to 19. MO8) transistors, these MOS) transistors 19, ~19. are controlled to be conductive by read outputs from predetermined memory cells 20, respectively, and which address to select is programmed according to the information stored in the memory element 20. Therefore, the scrambler 21. ~213 each has an address signal person. ~A person or a person.

~A211 is selectively supplied based on the information stored in the memory cell 20. And the scrambler 211-2
Internal address input person from 13. 9, A, 9゜h29
get.

FIG. 5 is intended to explain address scrambling with three address inputs shown in FIG. ~
In step 213, address inversion is not performed. As shown in the figure, 8f lock memory cell areas 22 to 228
Yes, 1st. The second area 221.222 is shadow
It is allocated to RAM. The above shadow RAM areas 221, 22□, MOS) Lanzosta 191-19
．． This is equivalent to existing in the third or fifth memory cell area 22, 225 depending on the on/off state of the cell.

With such a configuration, the flexibility of the above embodiment can be further increased, and the address of one area can be assigned to various areas.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a semiconductor memory device that enables efficient use of memory space when using different types of memories with different capacities, and that can reduce cost and physical amount.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining a semiconductor memory device according to one embodiment of the present invention, and FIGS. 4 and 5 are diagrams for explaining other embodiments of the invention, respectively. FIG. 6 is a diagram for explaining a conventional semiconductor memory device. Applicant's agent Patent attorney Takehiko Suzue
ku8ll A-ν' A-jl -. Ku x HaOha1 82 - A+''□A2' Figure 4 (a) Figure 4 (b) Ao = Ao” Ao = A1” Ao =
A2"A1・At At・Ao' Au・A1
"'A2 = A2 A2 = A2'" A2
= A. Figure 5 Figure 6 (a) Figure 6 (C)

Claims (3)

[Claims] (1) In a semiconductor memory device in which two or more types of memory cells with different structures are arranged on the same chip, the total number of bits of each memory cell is set to an integer power of 2, and the number of bits corresponding to each address signal is 1. A semiconductor memory device comprising scrambling means for inverting or non-inverting an input address based on stored information in an allocated memory means and supplying the inverted input address to the inside. (2) The memory cell having a different structure is a shadow RAM.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a RAM. (3) The semiconductor memory device according to claim 1, further comprising input address switching means for arbitrarily switching the order of the input address from LSB to MSB.