JPS62134731A - Fault diagnostic system for information processor - Google Patents

Abstract

PURPOSE:To execute a diagnosis of a processor in which a processor resources allocation rule of an instruction exists, by executing a test routine by determining an execution sequence of plural test routines so that a range of processor resources verified by some test routine contains a verification range of the test routine which is executed in the previous time. CONSTITUTION:An instruction is sent to an instruction decoding circuit (DEC0) 3-0 through paths 10, 11 from a main storage device 1. The first instruction of the DEC0 3-0 is initialization processing, therefore, the DEC0 3-0 instructs resources in a processor to be verified S1, and reset in a scalar 4. Subsequently, in case a processing of a call S1 is decoded by the DEC0 3-0, the DEC0 3-0 starts an instruction decoding circuit (DEC1) 3-1 and a data transferring circuit (REQ2) 2-2 of a vector processor (= a processor to be verified) S1. An initial address for reading out the main storage device 1 is transferred to the REQ2 2-2 inseparably from the start of this data transferring circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a processing device in which a plurality of instructions are logically equivalent.
This relates to a fault diagnosis method for an information processing device that employs a method executed by an H source.

[Background of the invention f; 0 Conventionally, in information processing devices, 1, for example, JP-A-56-
As described in Japanese Patent No. 50448, processing device resources are diagnosed using microprogram codes. In addition, for processing unit resources that are operated directly by instructions, not by microprogram instructions, a diagnostic method is used that compares the result of the instruction's operation with an expected value.7 The common point among these diagnostic techniques is that This is based on the premise that a one-to-one correspondence exists between an instruction and the processing device resources activated by the instruction. The fact that the logic circuit operated by an instruction and a microprogram that reduces it to a basic operation is uniquely determined by the logic circuit of the processing device under the condition that the processing of the processing device is performed serially. It is equivalent to saying that there is no redundancy in one situation. Therefore, it is natural that a processing device employing the conventional Neumann architecture has a one-to-one correspondence between a script-like operation and an operating logic circuit.

In recent years, there has been a strong demand for faster calculations of science and technology 81 calculations.

In order to meet this demand for higher speeds, devices have been developed that have a plurality of logically equivalent α sources within a processing circle. Examples include supercomputers and vector processing devices developed to process multidimensional matrices at high speed.Such processing devices are equipped with multiple logically equivalent resources and can execute multiple instructions in parallel. High performance is achieved by operating the Therefore, when only one instruction is processed, the programmer 1 can determine which resource the instruction is allocated to.
There is no means of detection from the first side, and diagnosis is difficult with conventional techniques.

[Purpose of the invention]

An object of the present invention is to provide an information processing system that executes instructions using multiple resources.
To develop a fault diagnosis method suitable for a JA device configured in such a way that one allocation logic can be easily expected when assigning multiple logically equivalent instructions to multiple processing device resources. It is in.

[Summary of the invention]

The present invention configures the diagnostic proger 11 with a plurality of test routines. Let x'T:: represent the set of processor resources that are verified by a test routine.

When the set of processing bag [d resources to be inspected in the test routine executed next to a certain test routine is X', the execution order of the plurality of test routines is determined so that X is included in X'. Executing the test routines in this order is hereinafter referred to as the small start method.

A set of logically equivalent J41 resources (
a+). Here, the subscript j is an index that distinguishes individual processing device resources. The fact that they are logically equivalent and cannot be indexed can be thought of as a concept. In other words, the fact that an index cannot be attached can be interpreted more broadly than the logically equivalent concept.

Suppose that ao is verified in a certain test routine. Due to the small start method, in the subsequent eggplant 1~routine, processing bag V1. Resources are verified. When instructions indicating multiple logically equivalent processing operations are allocated to multiple processing device resources and the allocation means is in the expected vine shape, the y element of the set (an+y) of the verified resources written in , can be determined by certain regulations. This ability to determine is another expression of the ability to predict. Therefore, it is possible to create a convention such that y becomes aj (j ~ 0), and according to this convention, it is also possible to create multiple instruction sequences such that y becomes a, 1. . This indicates that the order of the test routines should be created in a subsequent test routine so that the set of resources to be verified is (anlaj). We need to reconsider the conditions under which an index can be added here. Since ((,j~0)) is a natural number that is distinguished from O according to a certain convention, 1. It is possible to set j=1. Therefore, the following (an+
Write fl j ) = (an r a + ). By repeating the order of such test routines.

(a) It becomes possible to verify all the elements of the set, that is, the processing device resources.

The following points can be applied to a processing device equipped with multiple processing device resources by creating a test routine by combining multiple instructions, and by combining these test routines using the small start method to construct a diagnostic system. This shows that diagnosis is possible even when the current processing device resource cannot be uniquely identified by the instruction.

[Embodiments of the invention]

Assume that there is a processing yII device including a plurality of arithmetic units, a plurality of registers, a plurality of data transfer circuits, their control circuits, and a plurality of comparison circuits.

Regarding the command operations of this processing device, the processing device is classified as follows.

(1) Processing percentage that can be determined instantly by the logic circuit in the processing bag hV that operates according to instructions li'7゜(2)
A processing device capable of specifying a plurality of logic circuits in a processor 1111 to produce l1tJ+ by an instruction, and one logic 111 circuit by a plurality of instructions.

(3) A processing bag 5q that can identify the range of a plurality of logic circuits that operate according to an instruction.

A processing device belonging to (1) is, for example, a device vl having one adder, and is a processing device in which the smallness of one rig of the adder can be determined by an addition instruction. Processing devices that belong to this category include general-purpose computers.

A processing device belonging to (2) is, for example, a device F1-7 having a plurality of adders, and by operating these adders in parallel, the performance of the processing device can be improved. In such a processing device, since there are a plurality of logically equivalent processing resources, there is no one-to-one correspondence between the logic circuits that produce one instruction and the other.

■N+il・ cannot be done with commands. But the control circuit.

, by designing it so that instructions can be executed in a W-column manner, and by designing it so that the usage order of common sources used is uniquely determined by the parallel instruction origination state, that is, the busy state of resources. By suitably combining Mli'7 resources to create one, a specific processing Mli'7 resource can be saved. It can be performed.

The logic that dynamically allocates the processing unit resources to the execution of instructions in the control circuit of the processing unit according to the parallel execution status j/l of the instructions is essential logic for improving the performance of the processing unit, and is essential for one diagnostic system. 1) It is not a logic established solely for the purpose of building up popularity. For example, in order to easily construct a diagnostic system, processing '! The state holding means that manages the state of the A-purchased resource may be directly modified by a command. By adding such a logic circuit, it is possible to establish a pairwise correspondence between instructions and logic circuits. However, instructions for modifying such a state holding means must be incorporated into a processing device that is not related to the performance of the processing location, which results in an increase in hardware cost.

However, there are cases where a computer with multiple processing unit resources has a different architecture for diagnosis. For example, Hiraki, ITJ Nishi, and Sekiguchi, ``Maintenance Architecture of +rnr Data Driven Computer for Scientific and Technical Computing SLGM A-1'', Information Processing Society of Japan 31st Annual Conference Proceedings 6D-3. This SIGMA-1 has an approximately 20% increase in logic due to the addition of a maintenance architecture. Therefore, the present invention does not aim at constructing a diagnostic system that would result in such an increase in hardware costs.

A processing device belonging to (3) is a device that has multiple processing device resources, but the order in which the '9t and g are used is not unique, and a specific processing device resource cannot be verified depending on the combination of instructions. It is. A feature of such a processing device is that instruction execution control is not performed by decoding the instruction, but by controlling the operand data of the instruction when it is ready for operation.

Therefore, it is not possible to specify when an instruction is to be executed, and it is also impossible to verify a specific resource by combining multiple instructions. An example of a machine that explores such data flow control is T(E P -1 (Miura, Information Processing,
Volume 26, P, 659-P, 667).

In the fault diagnosis formula of the present invention, (1) and (2) of 1]
It is possible to verify the case of

In the present invention, a method is adopted for small star 1 in which the verification range of the processing device is sequentially expanded. However, when a chain of test routines using this small start method is called a pass, this path is reduced to a single path due to the instruction system of the processing device. Sometimes it doesn't happen. As shown in Figure 4, when attempting to perform a more extensive test following the test routine O),
(2) or (2) may be tested using multiple passes. Such a case is hereinafter referred to as a multi-pass test.

Multi-pass testing has the potential to pinpoint multiple faulty parts within a processing device. In this multi-pass test, the test proceeds along one path and moves to another path when the test is completed for that path or when a fault is issued. Therefore, it is necessary to construct a diagnostic system with a configuration that allows this processing. There is a close relationship between the construction of this diagnostic system and the instruction decoding of the processing unit. This will be discussed below.

In addition to these classifications, there are processing bags in which there is a one-to-one correspondence between an instruction and the logic circuit that performs its processing, and there are those in which there is no one-to-one correspondence.

The instruction m reading processing section of the processing device is 111. It can also be classified by number or plurality. An example is C of general-purpose 41 arithmetic machine.
The PU has one instruction decoder, but vector computers generally have 11 instruction decoders! There are 2 parts. That is, there is a scalar instruction decoding section, a scalar instruction solution, and an h'1 section. In these two types of processing equipment, the diagnostic system Progera t
It is necessary to consider the structure of 1.If the processing device has only one instruction decoding section, even such a computer can have a plurality of processing and drawing resources for each instruction. At this time, when there is an instruction that takes a long time to execute, such as a vector instruction, the instruction solver 2 part is configured so that the subsequent instruction can be executed without waiting for the completion of the previous instruction, and by combining the instructions... The processing device can be designed so that processing bag Vt resources can be specified at will. At this time, after the processing of 1 test 1 to routine is completed, a specific processing device resource can be verified and registered by executing an instruction to compare the test result with an expected value. Processing device I' with one instruction decoding section! Even if the processing time is t, it is possible to verify the specific resource in the processing bag h'a by repeating tests and comparisons repeatedly, performing a small start method, and performing a multi-pass test. In the multi-path test, if a faulty part of the bus is detected, a branch instruction is issued after comparison processing to branch to the start address of a test routine belonging to a different path.

When the processing device has two instruction decoding units, the test is performed by the first instruction decoding unit and the comparison process is performed by the second instruction M reading unit, so that the test and the comparison process are controlled to overlap, Parallel processing can speed up diagnosis. When a failure is detected in the multi-pass test, after the comparison process is completed, the test routine execution is canceled and branched to the beginning of the test routine of a different pass. The test routine is normally executed by resetting the state of the instruction decoding circuit. This state reset command is provided as a standard command set for processing AA products in order to prevent the processing device from running out of control. (Otherwise, the architecture of a processing device with two instruction decoding sections is inadequate.) As shown in the diagram, the diagnostic method of the present invention performs the diagnostic operation 1 when the routines 1 to 1 are operated. There is no need to prepare a special logic circuit for this purpose. Hereinafter, the diagnostic operation of the present invention will be explained with reference to the drawings, taking as an example a processing device having two instruction decoding units in the processing device.

FIG. 2 shows an embodiment of an information processing device capable of operating the fault diagnosis method of the present invention, where N indicates a vector processing device. In FIG. 2, 1 is the main memory, 2
3 is a data transfer circuit, 3 is an instruction decoding circuit, 4 is a scalar arithmetic unit (including a working register), 5 is an instruction activation circuit, 6
is an intermediate storage holding unit (vector register), and 7 is a plurality of vector arithmetic units. S is surrounded by the dotted line in Figure 2. The part corresponds to the scalar cenosa, and the 81st part corresponds to the vector processor.

FIG. 1 shows a schematic diagram of the diagnostic program of the present invention when the processing unit H has two instruction decoding sections. FIG. 1 shows the scalar processor S in FIG. 2 with time as the axis. , shows the instruction sequence of the vector processor S1.

The part indicated as initialization in the Sn column is the diagnostic system 11.
This is the part that performs initial settings to run the . The next call is ((JALL) S +.

This is an instruction to start the vector processor S1 from the scalar processor So. The next check (C: HECK) is an instruction to check whether the instruction processing of the vector processor S1 is completed. In this case, it is assumed that the check instruction is not completed until the processing of the vector processor is completed.

Parts 1 to 1 of the S1 column are instructions for testing processing equipment resources in the vector processor Sl.

The subscript number indicates the order of the test. The instruction sequence between test i and test I" i + 1 is coded using the Small Star 86 formula. That is, for example, test 1 is a test that uses one arithmetic unit, and test 1-2 is a test that uses two arithmetic units. It is a test.

The conveyor section of the Sn column is an instruction sequence for comparing the test result with the expected value. The numbers of some subscripts of the conveyor and eggplant 1 correspond. The judge section is a section that determines whether or not to execute the next test routine depending on whether the result of the conveyor i and the result of the test i is +F or L. That is, if the conveyor result is 11 yen, nothing is done and the next Death 1-routine is executed. If the conveyor result 1 does not match the expected value, interrupt the processing of the backup processor that is already processing the 1st test routine, perform the vector processor repeater 1~, and test a different pass. Performs processing to branch to a routine.

Note that the processing shown in the So column, with the exception of call S1, check, and vector processor processing interruption, includes load instructions, comparison instructions, and comparison instructions prepared in conventional general-purpose computers.
This can be done by combining branch instructions. Therefore, since these instructions can be executed by a combination of techniques that have already been made public, in FIG. 111. It has become a reality.

Next, the behavior of each logic circuit when the diagnostic program shown in FIG. 1 is executed will be explained using FIG. 2.

In FIG. 2, the command is a data transfer circuit (REQO) 2
-0 is used to send from the main memory 1 to the instruction decoding circuit (DECo) 30 via the path 10°1F. The D
Since the first instruction of ECO3-o is an initialization process, DECn30 instructs to reset the resources in the processor to be verified S1 and the scalar arithmetic unit 4 via path 1.2.13.

Next, when the process called call S1 is decoded by DECn3-o, DECn30 transfers data to the instruction decoding circuit (DECI) 3-1 of vector processor (=processor to be verified) S+ via path 12゜14. Circuit (R
EQ7) The initial address for accessing the main memory device 1 is transmitted to the REQ 22-2 inseparably from the activation of the data transfer circuit for activating the REQ 2-2. Send address to main memory 1 from address.

The instruction for verifying the vector processor S1 (instruction in the test i block in FIG. 1) is read out via the path 15 and sent to the DEC:+31 through the path 16. A circuit is required to manage multiple data transfers between the storage device 1 and the city storage device 1. This management circuit determines the priority of data transfer when the same main memory -H address occurs between multiple data transfer circuits, but the logic of this management circuit itself is already well known. . Furthermore, since it has no bearing on the diagnostic method of the present invention, the main memory management circuit is omitted from FIG. The following description will be made on the assumption that the main storage device 1 is provided with the management circuit and that a plurality of data transfers are possible.

1) EC: +3 1 sends instruction decoding information to the instruction decoding circuit 5 via path 17 after decoding the instruction of the test routine. The instruction starting circuit 5 manages the states of a plurality of data transfer circuits 21 and operations 8:+7 via a path [8°19]. Path 18 marked with a thick line (-) in Figure 2
, 19, 20.26 is the east line. If the resource requested by the instruction to be verified is free 5, the instruction is processed by the instruction activation circuit 5 according to the resource-side supplementary rules'! Assigned to A device source. This allocation or resource activation is done via path 20. If the resource requested by the instruction to be verified is busy, the instruction originator 4111 circuit 5
Instructs REQ22-2 to suppress successive primary verification instructions.

When the resource activated by the verification instruction is the data transfer circuit REQ3+n, the resource issues a data read or write request to the main storage device 1. In other words, if data continues to flow from the main storage device 1, the path 22.2
Data is written to the vector register 6 through the vector register 3.

In addition, when writing data to main storage device 1, path 2
The vector register 6 is read out via the path 25, and the data is stored in the i5 storage device 1 via the path 25. If the resource activated by the instruction is the arithmetic unit 7, the data serving as the arithmetic operand is read from the back register 6, and the result is written to the vector register 6 via the path 26.

As described in -1- above, the processor S to be verified executes an instruction, and the result is written to the main storage device 1.

Next, when the check instruction is decoded by DECn3-0,
The DECo 3 Q passes through a path 27 to the instruction source 39 of the processor S+ to be verified + the state I of the processor in the circuit 5.
Read the register indicating N to find out whether the processor has completed processing.

When branching to a test routine belonging to a yellow bus due to a 5-expectation mismatch from the scalar processor S n side, and forcibly suspending the verified processor S, the instruction that performs this suspension processing is r:l. When detected at ECn3-0, the DFC++30 interrupts instruction decoding of the processor under test via bus 12!5-, and then
The registers that hold the state of the processing device resources in the instruction activation circuit 5 are sent to the resense 1 through the instruction activation circuit 5.

FIG. 3 is a detailed diagram of the instruction activation circuit 5. In FIG. 73, the input/output paths of the instruction activation circuit are the same as those in FIG. 2.

The command is stored in the register 50 via the bus 17 and set in the register 51 at the primary timing. register 5
0.51 constitutes an instruction stack. In FIG. 3, the instruction stack is shown in two stages to simplify the drawing. For an instruction set in register 51, the resources to be used are determined by circuit 52 which determines what processing device resources are required to execute the instruction. The circuit 52 can be configured by referring to a storage means (for example, ROM) using an instruction opcode as an address and decoding it with a decoder means (DEC). For simplicity of explanation, assume that two processing unit resources are allocated to execute the instruction on register 51. This assigned information is transferred via buses 80, 81 to switching circuits 53.5.
/I is input.

The registers 55 each hold the status of the processing '3A resources. The processing device manages two states: whether the processing device is busy or not. That is, when the reporting source is busy, the value of the corresponding register 55 is L, 1.1+, and when it is not busy, the value is Lg_OTl. The states of registers 55 are selected by switching circuits 53 and 54, respectively, and the results are sent to registers 56 and 57, respectively. These registers 56
．． The value 57 indicates whether processing unit resources that can execute the instruction in register 51 are busy.

The values in the registers 56 and 57 are ANDed by an AND circuit 58 and sent onto the bus 21. When the signal on this bus 21'' becomes 1'', reading of instructions from the main memory is inhibited.
- to be done. At the same time, the signal on the bus 83 is inverted by the inverter 59, and the register 6° is set (7, which becomes the Pi number).
Therefore, when the output of the AAND circuit 58 is N i II, the instruction in the register 51-hi remains in the register 51 without being sent to the register 60 at the next timing. In this case, the status of the register 55 is checked again at the next timing.

When the values of registers 56 and 57 are not 111-II at the same time, the output of both registers is a selection circuit 61 that determines the processing device i# resource to execute the instruction of register 51-1-.
is input. In the case of two-person operation, the selection circuit 61 is the third
As shown in the figure, it can be constructed using an inverter and an OR circuit. Bus 84, 851- no I, 1 Gin is It O11゜II O
In the case of n, the output of the 1 selection circuit 61 is 1''.Similarly, in the case of 11 Q II, II J-II, the output of the 1 selection circuit 61 is ``['', and the six signals are '.

0" is "0". This determines which processing device resource is executed by the instruction. The output signal of the selection circuit 61 is input to the encoder 62 through the bus 86. This encoder It is not necessary when the input of the selection circuit 61 is 2, but when the input is 3 or more, the output of the selection circuit 61 becomes multiple, so it is necessary to perform appropriate conversion with the encoder.The output of the encoder 62 is connected to the bus. 87-H signal (when this is 1", the process to execute the command % SY
(indicates that one or more resources exist) and A N D I
A logical AND is performed at +'1 path 63 and inputted to a decoder 64. Decoder 64 sends a signal onto bus 88 that sets one of the registers 55 that holds the state of the resource used by the instruction on register 51.

On the other hand, when it is determined that the instruction is to be executed by the processing device, and as a result, the instruction is transferred to the register 60, the instruction is executed by referring to the storage means (order information generation circuit) 65 using the operation code of this instruction as an address. Generate order information for. The output of the order information generation circuit 65 is in the register 66.
Once the instruction is received, the switching circuit 67 sends it to the instruction execution resource via the bus 20 (multiple buses).

The switching control information of the switching circuit 67 can be used by latching the output of the encoder 62 in the register 69.

The output of register 55 is always logically summed by OR circuit 68, and the result is sent to bus 27J-. bus 27
A signal of 1 indicates that all processing unit resources in the vector processor portion of the processing unit are not busy, and this can be used to determine the completion of scalar processor processing.

When the processing designated by the command is completed in each of the processing units 9f and 9f, the respective resources in FIG. In the figure, this completion information is manually input to the register 55 as a reset instruction.

As explained above, it is possible to manage a plurality of resources of a processing device and consciously operate the plurality of processing device resources from the processor 11 side by combining a plurality of commands.

〔Effect of the invention〕

According to the present invention, there are cases where there are multiple resources in the processing device R and it is not possible to specify which resource is allocated with a single instruction, which was impossible to diagnose using microcode diagnosis etc. since tiQ. Then, the instruction processing shift 1i! /It is possible to diagnose a processing device in which a resource allocation rule exists. Also,
In implementing the fault diagnosis method of the present invention, there is no need to add a new logic circuit to the normal instruction execution logic of the processing device.

It has remarkable economic efficiency.

[Brief explanation of drawings]

FIG. 1 is a structural diagram of an example of a diagnostic program used in the present invention, FIG. 2 is a schematic block diagram of an information processing device to be diagnosed,
FIG. 3 is a detailed diagram of the instruction generation 191 circuit in FIG. 2, and FIG. 4 is a conceptual diagram of the eggplant 1-order of the diagnostic program. 1... Main memory device, 4... Scalar arithmetic unit. 5... Instruction activation circuit, 6... Intermediate memory holding section. 7. Arithmetic unit. J % (- Fig. 1 So 51 ! 1 Fig. 2 Fig. 4 Fig. 3

Claims (1)

[Claims] (1) In an information processing device that is equipped with a plurality of logically equivalent processing device resources and employs a method in which instructions are executed by the plurality of logically equivalent processing device resources, multiple diagnostic programs are installed. The test routine is executed by determining the execution order of the plurality of test routines so that the range of processing device resources verified by a certain test routine includes the verification range of the previously executed test routine. A fault diagnosing method for an information processing device, characterized in that a fault in the processing device resource is diagnosed.