JPS6213033U - - Google Patents
Info
- Publication number
- JPS6213033U JPS6213033U JP10425285U JP10425285U JPS6213033U JP S6213033 U JPS6213033 U JP S6213033U JP 10425285 U JP10425285 U JP 10425285U JP 10425285 U JP10425285 U JP 10425285U JP S6213033 U JPS6213033 U JP S6213033U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reversible
- input
- preset counter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002441 reversible effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 3
Description
第１図はこの考案によるデジタルスイツチの一
例を示す側面図、第２図はこのデジタルスイツチ
の一例を示す回路図、第３図はこのデジタルスイ
ツチ回路における入力禁止回路の一例を示すブロ
ツク図、第４図はこのデジタルスイツチの使用の
一例を示す正面図、第５図はこの考案によるデジ
タルスイツチの他の例を示す回路図である。
２ａ……前面板、４，１４……表示器、５，６
，２，３……押釦、７，８，２４……メカスイツ
チ、１５……可逆プリセツトカウンタ、１６……
表示駆動回路、１７……入出力回路、１８……パ
ルス発生回路、１９……入出力制御回路、２０…
…ラツチ回路、２１……リセツト回路、２２……
切換回路、３５……演算処理回路、１０１……入
力禁止回路。
FIG. 1 is a side view showing an example of a digital switch according to this invention, FIG. 2 is a circuit diagram showing an example of this digital switch, FIG. 3 is a block diagram showing an example of an input inhibit circuit in this digital switch circuit, and FIG. FIG. 4 is a front view showing an example of the use of this digital switch, and FIG. 5 is a circuit diagram showing another example of the digital switch according to this invention. 2a... Front plate, 4, 14... Display unit, 5, 6
, 2, 3...Push button, 7, 8, 24...Mechanical switch, 15...Reversible preset counter, 16...
Display drive circuit, 17... Input/output circuit, 18... Pulse generation circuit, 19... Input/output control circuit, 20...
...Latch circuit, 21...Reset circuit, 22...
Switching circuit, 35... Arithmetic processing circuit, 101... Input prohibition circuit.
Claims (1)
演算処理回路等からの信号線を入出力および高抵
抗の各状態に切り換える入出力回路と、演算処理
回路等からのデータ信号を可逆プリセツトカウン
タに入力させるための制御信号を上記入出力回路
に印加する入出力制御回路と、演算処理回路等か
らの全データ信号を保持するラツチ回路と、可逆
プリセツトカウンタのデータ出力および動作状態
を表示する表示器と、この表示器を駆動する表示
駆動回路と、この表示駆動回路に印加されるラツ
チ回路からのデータ信号と可逆プリセツトカウン
タからの数値信号とを切り換える切換回路と、前
面板側に設定された操作スイツチにより上記可逆
プリセツトカウンタを歩進させるパルス発生回路
とを具備し、演算処理回路等から全データ信号を
上記ラツチ回路に保持させ、上記切換回路により
切り換えて表示器に表示させるとともに、演算処
理回路等からの全データ信号のうち数値信号は可
逆プリセツトカウンタを介して表示させるように
構成したことを特徴とするデジタルスイツチ。 (2) 外部の演算処理回路等からの入力禁止信号
が印加されたとき、前面板側に設定された操作ス
イツチから可逆プリセツトカウンタへの入力を禁
止する入力禁止回路を具備してなる実用新案登録
請求の範囲第１項記載のデジタルスイツチ。[Claims for Utility Model Registration] (1) A reversible preset counter capable of addition and subtraction;
An input/output circuit that switches the signal line from the arithmetic processing circuit, etc. to each state of input/output and high resistance, and a control signal for inputting the data signal from the arithmetic processing circuit, etc. to the reversible preset counter to the input/output circuit. An input/output control circuit that applies voltage, a latch circuit that holds all data signals from the arithmetic processing circuit, etc., a display that displays the data output and operating status of the reversible preset counter, and a display drive circuit that drives this display. The reversible preset counter is incremented by a switching circuit that switches between the data signal from the latch circuit and the numerical signal from the reversible preset counter applied to the display drive circuit, and an operation switch set on the front panel. The latch circuit holds all data signals from the arithmetic processing circuit, etc., and the switching circuit switches the data signals to be displayed on the display. A digital switch characterized in that a signal is configured to be displayed via a reversible preset counter. (2) A utility model equipped with an input prohibition circuit that prohibits input from an operation switch set on the front panel side to a reversible preset counter when an input prohibition signal is applied from an external arithmetic processing circuit, etc. A digital switch according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985104252U JP2588271Y2 (en) | 1985-07-08 | 1985-07-08 | Digital switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985104252U JP2588271Y2 (en) | 1985-07-08 | 1985-07-08 | Digital switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6213033U true JPS6213033U (en) | 1987-01-26 |
| JP2588271Y2 JP2588271Y2 (en) | 1999-01-06 |
Family
ID=30977571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985104252U Expired - Lifetime JP2588271Y2 (en) | 1985-07-08 | 1985-07-08 | Digital switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2588271Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698671A (en) * | 1979-12-20 | 1981-08-08 | Suisse Horlogerie | Interface unit for inputting data into small device such as watch or clock |
-
1985
- 1985-07-08 JP JP1985104252U patent/JP2588271Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698671A (en) * | 1979-12-20 | 1981-08-08 | Suisse Horlogerie | Interface unit for inputting data into small device such as watch or clock |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2588271Y2 (en) | 1999-01-06 |
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