JPS6212902B2 - - Google Patents

Info

Publication number
JPS6212902B2
JPS6212902B2 JP15375679A JP15375679A JPS6212902B2 JP S6212902 B2 JPS6212902 B2 JP S6212902B2 JP 15375679 A JP15375679 A JP 15375679A JP 15375679 A JP15375679 A JP 15375679A JP S6212902 B2 JPS6212902 B2 JP S6212902B2
Authority
JP
Japan
Prior art keywords
liquid crystal
switching element
circuit
electrode
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15375679A
Other languages
Japanese (ja)
Other versions
JPS5677892A (en
Inventor
Seigo Togashi
Fukuo Sekya
Shigeru Morokawa
Akira Tsuzuki
Kazuhiko Maeda
Hisato Hiraishi
Sadao Masubuchi
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP15375679A priority Critical patent/JPS5677892A/en
Publication of JPS5677892A publication Critical patent/JPS5677892A/en
Publication of JPS6212902B2 publication Critical patent/JPS6212902B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はスイツチング素子をセル基板上に設け
たスイツチング素子内蔵型液晶表示装置に関し、
詳しくは環境の変動に対しても安定した表示品質
を有する液晶表示装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching element built-in liquid crystal display device in which a switching element is provided on a cell substrate.
More specifically, the present invention relates to a liquid crystal display device that has stable display quality even under environmental changes.

液晶表示装置は低電力、低電圧という他の装置
にない特徴を有し、電卓、時計等の携帯機器を中
心に広く用いられている。しかし表示特性は電圧
に対し鋭い閾値特性を持たない為、高分割のマル
チプレクツス駆動には適さない。そこで高分割の
マルチプレツクス駆動を可能とする為にスイツチ
ング素子を各表示要素毎に配置する方式(スイツ
チング素子内蔵方式)が提案されていた(参照、
B.J.Lechner et al.Proc.IEEE vol 59、
Nov.1971、p.1566〜1579)。しかし従来のスイツ
チング素子内蔵方式では温度、光等の外的環境の
変動による表示品質の低下に対する対策がほとん
どなされておらず、携帯機器等厳しい使用状態で
も確実に動作しなくてはならない用途への実用化
は実現していない。本発明はかかる欠点を解消す
る技術に関し、極めて効率良く且つ確実に外的環
境の変動による影響を補償する手段を提供する。
Liquid crystal display devices have features that other devices do not have, such as low power and low voltage, and are widely used mainly in portable devices such as calculators and watches. However, since the display characteristics do not have sharp threshold characteristics with respect to voltage, they are not suitable for high-division multiplex driving. Therefore, in order to enable high-division multiplex driving, a method was proposed in which a switching element is arranged for each display element (switching element built-in method) (see
BJLechner et al.Proc.IEEE vol 59,
Nov.1971, p.1566-1579). However, with conventional switching element built-in systems, there are few measures taken to prevent deterioration of display quality due to changes in the external environment such as temperature and light, making it difficult to use for applications such as mobile devices that must operate reliably even under harsh usage conditions. It has not been put into practical use. The present invention relates to a technique for eliminating such drawbacks, and provides means for extremely efficiently and reliably compensating for the effects of changes in the external environment.

本発明の説明に先立ち、スイツチング素子内蔵
方式について述べる。第1図はその一例の説明図
で、Sijはスイツチング素子、Zijは電極で狭まれ
た液晶層よりなるインピーダンス素子、Cijは必
要に応じて適宜設けられ付加る付加容量である。
但し添字i,jは任意の自然数である。液晶層イ
ンピーダンス素子Zijは第2図の如く大よそ配線
抵抗R、液晶層容量C、液晶層抵抗Rよりなる。
スイツチング素子Sijのゲート電圧VG対ドレイン
電流ID特性が第7図での実線15の特性をとる
とすると適当なゲート電圧をYi電極に印加すれ
ばXj電極から液晶層インピーダンスZji及び付加
容量に注入するドレイン電流を任意に制御出来
る。例えばY1,Y2,Y3,………電極に第3図の
時分割された制御信号y1,y2,y3,………を印加
する。v2が印加されている期間を選択期間t,v1
が印加されている期間を非選択期間T−tと呼
ぶ。選択期間tではスイツチング素子は導通状態
となりドレイン電流が流れ、もし配線抵抗Rが十
分小さく液晶抵抗が十分大きければ、液晶容量及
び付加容量の電位(例えば第3図V11)はその時の
Xj電極の電位例えば第3図VONになるように時
定数τで充放電される。非選択期間ではスイツ
チング素子は非導通状態となり、前の選択期間で
定まつた電位が時定数τで保持される。以上の
如くスイツチング素子内蔵方式では選択期間での
充放電特性と、非選択期間での保持特性が重要
で、両特性が十分である時初めて高品質の高分割
マルチプレツクス駆動が可能となる。選択期間で
の充放電時間τはスイツチング素子のオン抵抗
ONと液晶容量C、付加容量Cijに依存しRON
(C+Cij)に比例し、非選択期間での保持時間τ
はスイツチング素子のオフ抵抗ROFFと前記C
+Cijの積に比例する。よつて安定な動作を得る
為には小さなRONと大きなROFFを実現し得るス
イツチング素子が必要である。
Prior to explaining the present invention, a switching element built-in system will be described. FIG. 1 is an explanatory diagram of one example, where Sij is a switching element, Zij is an impedance element made of a liquid crystal layer narrowed by electrodes, and Cij is an additional capacitance that is appropriately provided and added as necessary.
However, the subscripts i and j are arbitrary natural numbers. The liquid crystal layer impedance element Zij is approximately composed of a wiring resistance R, a liquid crystal layer capacitance C, and a liquid crystal layer resistance R as shown in FIG.
Assuming that the gate voltage V G vs. drain current I D characteristic of the switching element Sij takes the characteristic shown by the solid line 15 in Figure 7, if an appropriate gate voltage is applied to the Yi electrode, the liquid crystal layer impedance Zji and additional capacitance will be changed from the Xj electrode to the liquid crystal layer impedance Zji. The drain current to be injected can be controlled arbitrarily. For example, the time-divided control signals y 1 , y 2 , y 3 , . . . shown in FIG. 3 are applied to the electrodes Y 1 , Y 2 , Y 3 , . The period during which v 2 is applied is selected period t, v 1
The period during which is applied is called a non-selection period T-t. During the selection period t, the switching element becomes conductive and a drain current flows, and if the wiring resistance R is sufficiently small and the liquid crystal resistance is sufficiently large, the potential of the liquid crystal capacitance and the additional capacitance (for example, V 11 in Fig. 3) will be the same at that time.
It is charged and discharged with a time constant τ 1 so that the potential of the Xj electrode becomes, for example, V ON in FIG. During the non-selection period, the switching element is non-conductive, and the potential determined during the previous selection period is maintained with a time constant τ 2 . As described above, in the switching element built-in system, the charging/discharging characteristics during the selection period and the holding characteristics during the non-selection period are important, and high-quality, high-division multiplex driving is only possible when both characteristics are sufficient. The charging/discharging time τ1 during the selection period depends on the on-resistance R ON of the switching element, the liquid crystal capacitance C, and the additional capacitance Cij, and is R ON
It is proportional to (C + Cij), and the retention time τ in the non-selection period
2 is the off-resistance R OFF of the switching element and the above C
Proportional to the product of +Cij. Therefore, in order to obtain stable operation, a switching element that can realize small R ON and large R OFF is required.

スイツチング素子積層型液晶表示パネルの実際
的な構成の一例を第4,5,6図に示す。第4図
は斜視図である。基板1上には電極層4が、基板
2上にはスイツチング素子を含む層5が形成さ
れ、両基板の間に液晶層3が挾まれている。第5
図は部分断面図である。基板2上のスイツチング
素子はゲートである電極Yと絶縁層10、半導体
層11,12,13、ソース電極を兼ねる電極
X、ドレイン電極を兼ねる液晶用電極7よりな
る。8,9は保護膜を兼ねた表面処理層である。
第6図は、約1表示要素に対応する部分の基板2
を上から見た平面図である。Yはゲート電極、X
はソース電極、6は半導体層、7はドレイン電極
兼液晶用電極である。一点鎖線14による断面が
第5図に対応する。第5,6図には付加容量が設
けられてないが、必要に応じてドレイン電極とゲ
ート電極の間に形成すればよい。
An example of a practical configuration of a switching element stacked type liquid crystal display panel is shown in FIGS. 4, 5, and 6. FIG. 4 is a perspective view. An electrode layer 4 is formed on the substrate 1, a layer 5 including switching elements is formed on the substrate 2, and a liquid crystal layer 3 is sandwiched between the two substrates. Fifth
The figure is a partial sectional view. The switching element on the substrate 2 includes an electrode Y serving as a gate, an insulating layer 10, semiconductor layers 11, 12, and 13, an electrode X serving as a source electrode, and a liquid crystal electrode 7 serving as a drain electrode. 8 and 9 are surface treatment layers that also serve as protective films.
FIG. 6 shows a portion of the substrate 2 corresponding to about one display element.
FIG. Y is the gate electrode, X
is a source electrode, 6 is a semiconductor layer, and 7 is a drain electrode and a liquid crystal electrode. The cross section along the dashed line 14 corresponds to FIG. Although an additional capacitor is not provided in FIGS. 5 and 6, it may be formed between the drain electrode and the gate electrode if necessary.

第8図は全体のブロツクダイヤフラムである。
21が第4〜6図の様な構成をとる表示パネル
部、22は第3図y1,y2,y3,………等のゲート
信号を供給するゲート・ドライバでクロツク回路
25のクロツクに同期して駆動される低速掃引シ
フト・レジスタで構成され、23はソース信号を
供給するソース・ドライバで表示信号発生回路2
6よりシリアルに入力される表示信号がクロツク
回路25で同期をとつた高速掃引シフト・レジス
タ24の信号により順次記憶する一時記憶回路等
で構成される。表示信号発生回路26は必要に応
じて外部情報を27より受けて動作する。電源線
は省略してある。
FIG. 8 shows the entire block diaphragm.
Reference numeral 21 denotes a display panel section having a configuration as shown in FIGS. 4 to 6, and 22 a gate driver that supplies gate signals such as y 1 , y 2 , y 3 , etc. shown in FIG. 23 is a source driver that supplies a source signal to the display signal generation circuit 2.
It is composed of a temporary storage circuit, etc., in which display signals serially input from 6 are sequentially stored in accordance with a signal from a high-speed sweep shift register 24 synchronized by a clock circuit 25. The display signal generation circuit 26 operates by receiving external information from 27 as necessary. The power line is omitted.

以上説明した様なスイツチング素子内蔵型液晶
表示装置は原理的にはテレビ程度の情報も十分表
示する事が可能であり、しかも低電圧、低電力駆
動という長所も損なわれず、小型携待用表示とし
ては他の方式と比べても非常に優れた方式と言え
る。
The liquid crystal display device with a built-in switching element as described above is, in principle, capable of displaying as much information as on a TV, and without sacrificing its advantages of low voltage and low power drive, it can be used as a small portable display device. can be said to be a very superior method compared to other methods.

しかし原理的に優れているものの従来方式では
実用化には至つていない。その原因の一つが温度
や光等の外的要因による表示品質のばらつき、低
下である。特に温度、光等に非常に敏感な半導体
をスイツチング素子に用いた場合この効果は大き
い。例えば第5図の様な電界効果トランジスタ型
のスイツチング素子を用いる場合、通常特性第7
図実線15は温度上昇により一点鎖線17に、光
照射により破線16の特性に変化する。この様に
ドレイン電流IDが変化し実効的なオン抵抗RON
及びオフ抵抗ROFFが変化すると液晶層に印加さ
れる信号波形、例えば第3図V11の時定数τ
びτが変化し、実効的な液晶印加電圧が変動し
表示品質の低下を生ずる。この品質低下をあらか
じめ製造上補償するにはスイツチング素子特性の
動作マージンを大きくとらねばならず、製造法及
び歩留りの面でも負担が大きい。本発明は以上の
様な外的要因による特性劣化の影響を駆動法の工
夫により改善する事により、品質の向上及び製造
上の自由度を拡大し製造価格の低減をも可能とす
る技術を提供する。以下図面に基づき詳細に説明
する。
However, although the method is excellent in principle, the conventional method has not been put into practical use. One of the causes is variation and deterioration in display quality due to external factors such as temperature and light. This effect is particularly significant when a semiconductor that is extremely sensitive to temperature, light, etc. is used for the switching element. For example, when using a field effect transistor type switching element as shown in FIG.
The solid line 15 in the figure changes to the dashed line 17 due to temperature rise, and changes to the broken line 16 due to light irradiation. In this way, the drain current I D changes and the effective on-resistance R ON
When the off-resistance R OFF changes, the signal waveform applied to the liquid crystal layer, for example, the time constants τ 1 and τ 2 of V 11 in FIG. . In order to compensate for this quality deterioration in advance during manufacturing, a large operating margin must be provided for the switching element characteristics, which imposes a heavy burden on the manufacturing method and yield. The present invention provides technology that improves quality, expands the degree of freedom in manufacturing, and reduces manufacturing costs by improving the effects of characteristic deterioration caused by external factors such as those described above by devising a driving method. do. A detailed explanation will be given below based on the drawings.

第9図は本発明の実施例のブロツクダイヤグラ
ムである。28がスイツチング素子の特性変化を
検出する検出回路であり、可変クロツク回路29
に含まれる測定制御回路からの制御信号66によ
りスイツチング素子のコンダクタンスに応じた信
号61を可変クロツク回路29に供給する。可変
クロツク回路29はスイツチング素子のコンダク
タンスの変動を補償し得る基本クロツク信号fを
設定し、fを基準にしたクロツク信号35,3
6,38,37をそれぞれソース用高速掃引シフ
トレジスタ24、ゲート・ドライブ用低速掃引シ
フトレジスタ22、ソース・ドライバ23、表示
信号発生回路26に供給する。25は固定の基準
クロツク回路であり基準クロツク信号30,34
を表示信号発生回路26及び可変クロツク回路2
9に供給する。
FIG. 9 is a block diagram of an embodiment of the present invention. 28 is a detection circuit for detecting a change in the characteristics of the switching element, and a variable clock circuit 29
A signal 61 corresponding to the conductance of the switching element is supplied to the variable clock circuit 29 by a control signal 66 from a measurement control circuit included in the circuit. The variable clock circuit 29 sets a basic clock signal f capable of compensating for fluctuations in the conductance of the switching element, and outputs clock signals 35, 3 based on f.
6, 38, and 37 are supplied to the source high-speed sweep shift register 24, the gate drive low-speed sweep shift register 22, the source driver 23, and the display signal generation circuit 26, respectively. 25 is a fixed reference clock circuit which receives reference clock signals 30, 34.
Display signal generation circuit 26 and variable clock circuit 2
Supply to 9.

本発明ではこの様にスツチング特性の変動を基
本クロツク信号に基づく駆動用周波数を変える事
により補償する。即ち、選択期間の充放電時定数
τはスイツチング素子のオン抵抗RONに比例
し、非選択期間の保持時定数τはオフ抵抗ROF
に比例するから、RON,ROFFの変動分だけ選択
時間t及び非選択時間(T−t)を変えてやれ
ば、液晶層に印加される実効電圧の変動はゼロに
なる。
In the present invention, variations in the stitching characteristics are compensated for by changing the driving frequency based on the basic clock signal. That is, the charging/discharging time constant τ 1 during the selection period is proportional to the on-resistance R ON of the switching element, and the holding time constant τ 2 during the non-selection period is proportional to the off-resistance R OF
Since it is proportional to F , if the selection time t and non-selection time (Tt) are changed by the amount of variation in R ON and R OFF , the variation in the effective voltage applied to the liquid crystal layer becomes zero.

T,t共に変えてもよいが、RON,ROFFの変
動は第7図の例でもわかる通り同程度の事が多
く、ΔRON/RONΔROFF/ROFFαと近似し
てt→(1+α)tT→(1+α)Tと周波数変
更して補償しても効果は十分大きい。この時は適
当なゲート電圧を与えて変化率αを測定し基本ク
ロツク信号を1+α倍すればよい。
Both T and t may be changed , but as can be seen from the example in Figure 7, the fluctuations in R ON and R OFF are often of the same degree, and t→ Even if the frequency is changed from (1+α)tT to (1+α)T to compensate, the effect is sufficiently large. At this time, it is sufficient to apply an appropriate gate voltage, measure the rate of change α, and multiply the basic clock signal by 1+α.

第10図は本発明の具体的な一実施例である。
56,50,51の3ブロツクで第9図の検出回
路28に対応し、52,53,54,55のブロ
ツクが第9図の可変クロツク回路29に対応す
る。56はオシレータ制御回路であり53に含ま
れる測定制御回路からの制御信号66によりスイ
ツチング素子特性測定用オシレータ50の発振を
スイツチ85により電源線68をオン・オフして
動作、停止させ、更にスイツチ86により液晶パ
ルス上の特性検出用スイツチング素子80にゲー
ト電圧vを供給する。特性検出用オシレータ50
は増幅器82,83,84と付加容量81、浮遊
容量88及び抵抗素子として働くスイツチング素
子80からなり、スイツチング素子のコンダクタ
ンスの関数である周波数で発振する。発振出力6
1は検出信号制御ゲート51により発振周波数に
比例したパルス列となつてカウンタ部52に62
から入力される。カウンタ部52は発振周波数を
カウントしその信号63を処理回路53に入力す
る。処理回路53はカウント信号63からクロツ
ク発生回路54を制御すべき信号64を発生する
回路と、前述の測定制御回路を有する。本実施例
ではクロツク発生回路54はプリセツトカウンタ
89を中心に構成され、処理回路53はカウンタ
出力を演算処理してプリセツトカウンタ89に信
号64を供給する。演算処理はマイクロプロセツ
サを用いても、ランダムロジツクゲートを組み合
わせた演算回路を用いても、プログラマブル・ロ
ジツク・アレイによる論理回路を用いてもよい。
クロツク発生回路54により発生した基本可変ク
ロツク信号65は分周器55で適当に分周され各
回路に供給される。
FIG. 10 shows a specific embodiment of the present invention.
Three blocks 56, 50, and 51 correspond to the detection circuit 28 of FIG. 9, and blocks 52, 53, 54, and 55 correspond to the variable clock circuit 29 of FIG. Reference numeral 56 denotes an oscillator control circuit, which operates and stops the oscillation of the oscillator 50 for measuring switching element characteristics by turning on and off the power supply line 68 using a switch 85 in response to a control signal 66 from a measurement control circuit included in 53; A gate voltage v is supplied to the switching element 80 for detecting characteristics on the liquid crystal pulse. Characteristic detection oscillator 50
consists of amplifiers 82, 83, 84, an additional capacitance 81, a stray capacitance 88, and a switching element 80 acting as a resistance element, and oscillates at a frequency that is a function of the conductance of the switching element. Oscillation output 6
1 is converted into a pulse train proportional to the oscillation frequency by the detection signal control gate 51 and sent to the counter section 52 at 62.
Input from The counter section 52 counts the oscillation frequency and inputs the signal 63 to the processing circuit 53. The processing circuit 53 has a circuit for generating a signal 64 for controlling the clock generating circuit 54 from the count signal 63, and the aforementioned measurement control circuit. In this embodiment, the clock generation circuit 54 is constructed mainly of a preset counter 89, and the processing circuit 53 performs arithmetic processing on the counter output and supplies a signal 64 to the preset counter 89. Arithmetic processing may be performed using a microprocessor, an arithmetic circuit combining random logic gates, or a logic circuit using a programmable logic array.
A basic variable clock signal 65 generated by the clock generation circuit 54 is appropriately frequency-divided by a frequency divider 55 and supplied to each circuit.

以上の説明した様に、液晶パネル上のスイツチ
ング素子の特性を検出する検出回路を設け、該検
出回路の検出出力によりクロツク回路を制御して
液晶パネルに供給する信号の基準となる基本周期
Tや選択期間tを最適化する本発明は若干の回路
を添加するだけであるから製造上の負担は極めて
小さいにもかかわらず、液晶に印加される電圧を
実効的に常にほぼ一定に保つ事により表示品質を
一定に保ち、製造上のマージンが小さくてもすむ
所から製造価格をも低減出来る極めて有効な技術
である。
As explained above, a detection circuit is provided to detect the characteristics of the switching elements on the liquid crystal panel, and the detection output of the detection circuit controls the clock circuit to determine the fundamental period T and the reference signal supplied to the liquid crystal panel. The present invention, which optimizes the selection period t, only requires the addition of a few circuits, so the manufacturing burden is extremely small. It is an extremely effective technology that can maintain constant quality and reduce manufacturing costs since it requires only a small manufacturing margin.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はスイツチング素子内蔵方式の説明図、
第2図は液晶層インピーダンスの等価回路図、第
3図はスイツチング素子内蔵方式のゲート制御信
号及び液晶層に印加される信号波形図、第4図は
スイツチング素子内蔵型液晶表示パネルの斜視図
第5図は第4図の部分断面図、第6図は第4図の
部分平面図、第7図はスイツチング素子特性図、
第8図及び第9図は従来方式及び本発明の駆動回
路のブロツクダイヤグラム、第10図は本発明の
駆動回路の具体的回路図である。 21……スイツチング素子内蔵型液晶表示パネ
ル、28……検出回路、29……可変クロツク回
路。
Figure 1 is an explanatory diagram of the built-in switching element system.
Figure 2 is an equivalent circuit diagram of liquid crystal layer impedance, Figure 3 is a diagram of gate control signals and signal waveforms applied to the liquid crystal layer in a switching element built-in type, and Figure 4 is a perspective view of a liquid crystal display panel with a built-in switching element. 5 is a partial sectional view of FIG. 4, FIG. 6 is a partial plan view of FIG. 4, FIG. 7 is a switching element characteristic diagram,
8 and 9 are block diagrams of the conventional drive circuit and the present invention, and FIG. 10 is a specific circuit diagram of the present invention. 21... Liquid crystal display panel with built-in switching element, 28... Detection circuit, 29... Variable clock circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 スイツチング素子を設けた基板と、少くとも
1個の電極を有する基板との間に液晶層を挾持し
た液晶表示パネルと、前記電極を通じて液晶層に
駆動信号を印加する駆動回路部とを備えた液晶表
示装置に於いて、前記スイツチング素子の特性変
化を検出する検出手段を設けると共に、該検出し
た情報により駆動信号の基本周期を変化させる手
段を有することを特徴とする液晶表示装置。
1. A liquid crystal display panel having a liquid crystal layer sandwiched between a substrate provided with a switching element and a substrate having at least one electrode, and a drive circuit section that applies a drive signal to the liquid crystal layer through the electrode. A liquid crystal display device, characterized in that the liquid crystal display device is provided with a detection means for detecting a change in the characteristics of the switching element, and further includes means for changing the basic period of a drive signal based on the detected information.
JP15375679A 1979-11-28 1979-11-28 Liquid crystal display unit Granted JPS5677892A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15375679A JPS5677892A (en) 1979-11-28 1979-11-28 Liquid crystal display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15375679A JPS5677892A (en) 1979-11-28 1979-11-28 Liquid crystal display unit

Publications (2)

Publication Number Publication Date
JPS5677892A JPS5677892A (en) 1981-06-26
JPS6212902B2 true JPS6212902B2 (en) 1987-03-23

Family

ID=15569430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15375679A Granted JPS5677892A (en) 1979-11-28 1979-11-28 Liquid crystal display unit

Country Status (1)

Country Link
JP (1) JPS5677892A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186796A (en) * 1982-04-26 1983-10-31 社団法人日本電子工業振興協会 Liquid crystal display unit and driving thereof

Also Published As

Publication number Publication date
JPS5677892A (en) 1981-06-26

Similar Documents

Publication Publication Date Title
US4045791A (en) Apparatus for driving liquid crystal display device wherein the signal applied thereto is varied in accordance with the temperature of the device
US6806871B1 (en) Driver IC, electro-optical device and electronic equipment
US5798746A (en) Liquid crystal display device
US4430648A (en) Combination matrix array display and memory system
JP4099913B2 (en) Electro-optical device, clock signal adjustment method and circuit thereof, production method thereof, and electronic apparatus
US4094137A (en) Voltage conversion system for electronic timepiece
GB2120440A (en) Liquid crystal display and methods for driving liquid crystal displays
US4057325A (en) Display device
JPS6357000B2 (en)
JPS6083477A (en) Driving circuit of liquid crystal display device
JPS62218943A (en) Liquid crystal display device
US3903518A (en) Driving system for liquid crystal display device
JPS63304228A (en) Liquid crystal display device
JP2000356976A (en) Electrooptical device, electronic equipment and driving method for electrooptical panel
CN112860102A (en) Drive circuit, touch display device and electronic equipment
JPS6212902B2 (en)
JPS6212903B2 (en)
KR101002099B1 (en) Active matrix liquid crystal display devices with feedback control of drive signals
CN214474928U (en) Liquid crystal display device and electronic apparatus
US4205518A (en) Voltage conversion system for electronic timepiece
KR20070071200A (en) Simulation algorithm for calculating liquid crystal capacitance of pixel
JP2005258465A (en) Electrooptical device and electronic equipment
JP3329028B2 (en) Display device with coordinate detection device
US20020126081A1 (en) Liquid crystal display device and method for driving the same
KR930010837A (en) Drive circuit for display device with digital source driver that can generate multi-level driving voltage from one external power source