JPS62126728A - Pcm codec - Google Patents

Abstract

PURPOSE:To attain data switching in a low/high bit ease of semiconductor circuit integration without losing the economy by using a data input/output device circuit section in common with a part of the circuit of a voice PCM- CODEC. CONSTITUTION:A digital signal stored in a buffer register 9 of PCM input is supplied to a buffer register 6 of PCM output, the bit rate is converted from a PCM output terminal and outputted. The PCM-CODEC has three ways of operating states. In the 1st state, the PCM output and input terminals 7, 8 are connected respectively to transmission/reception PCM highways and only the voice PCM is handled. In the 2nd state, the terminal 7 is connected to a 64kb/s data line and the terminal 8 is connected to a high speed PCM highway. In the 3rd state, the terminal 7 is connected to the PCM highway and the terminal 8 is connected to the 64kb/s data line.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an audio PCM code decoder (hereinafter referred to as CODEC) equipped with a data input/output function, and in particular to an audio PCM code decoder (hereinafter referred to as a CODEC) that is capable of handling low-speed bit rate data other than audio. The present invention relates to a PCM-C0DEC that is suitable for semiconductor integrated circuits and that enables mutual conversion and input/output of high-speed bit rate data.

[Background of the invention]

In the digital exchange, the voice PCM-C0DEC and the data input/output device control circuit were installed separately. The voice PCM-C0DEC, which normally uses a PCM signal bit rate of 1.5 Mb/s or more, is installed to support the subscriber circuit connected to the telephone set, so for the purpose of economicalization, it has been integrated into a semiconductor integrated circuit. It has been. - Since low-speed data (e.g. 64Kb/S) input/output device control circuits are intended for only a few man-machine interfaces such as typewriters, CRs, and Ts, they are implemented using dedicated semiconductor integrated circuits. Although there were no technical problems with this, it was not economical to realize it, so it was constructed by combining separate components and small-scale integrated circuits on a printed circuit board. Unfortunately, as subscriber circuits have become smaller through the active introduction of LSIs, the proportion of data input/output device control circuits mounted within digital exchanges has increased.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, and to enable mutual conversion between low bit rate data and high bit rate data for man-machine interfaces, which is easy to integrate into a semiconductor integrated circuit, without impairing economic efficiency. PC
Our goal is to provide M-C0DEC.

[Summary of the invention]

In order to achieve the above object, the present invention is designed so that the data input/output device circuit section can be shared with a part of the circuit of the audio PCM-C0DEC. digital signal to PC
The configuration is such that the data is supplied to a buffer register with M outputs, and the bit rate is converted and output from the PCM output terminal.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of an audio PCM-C0DEC according to the present invention.

The transmitter includes an A-D converter 2 that converts the audio signal input from the terminal 1 into a digital signal, a transmitter filter 3 that transmits only the audio band, and a compressor that converts the digital signal into a compressed PCM signal recommended by the CCITT. 4 (However, the order of the A-D converter 2 and filter 3 may be reversed, and in that case, the compressor 4 may be omitted). 64K
A switch function unit 5 for switching between the Hz data PCM signal and the audio PCM signal or the 64KHz data PC
Timing the M signal? A! ! It consists of a PCM0M output buffer register for temporary storage.

The receiving section includes a PCM input buffer register 9 that takes in the received PCM signal from the input terminal 8, an expander 10 that converts the output PCM into a linear PCM signal when the output PCM is an audio compressed PCM signal, and an expander 10 that converts only the audio frequency band into a linear PCM signal. a receiving side filter 11 for converting into an audio analog signal, and a D-A for converting into an audio analog signal.
It is composed of a converter 12 ((the order of the DA converter 12 and filter 11 may be reversed depending on the transmitting side, in which case the expander 11 may be omitted).

The circuit 14 also includes the transmitting side PCM output buffer register 6 and the receiving side PCM buffer register, 8K.
Based on the H2 synchronization signal 15 and the clock 16 switching control signal 17, it generates timing control pulses for the output and input from the CODEC and switching control pulses between audio PCM and data PCM.

The control signal 17 that controls the input and output switching of the audio PCM and data PCM signals can be provided as an external terminal and controlled by connecting it to the ground or power supply potential, or by providing a microcomputer interface to control the switching of the audio PCM output signal. It is also possible to use software to control the gain of the audio analog output signal, switching of the companding law (μ law/A law), etc. using software, but these control methods are not covered in this book. Since it does not limit the scope of the invention, it will not be described in detail.

FIG. 2 shows the switch section 5. of FIG. An example of the PCM buffer registers 6 and 9 and the timing pulse supply circuit 14 is shown. The functions of the switch unit 5 in FIG. 1 can be simultaneously realized by using the transmitting side PCM buffer register 6 as a shift register with a preset.

The PCM-C0DEC according to the present invention has three operating states. That is, in the first state, the PCM output terminal 7
, PCM input terminal 8 is connected to a high-speed transmitting/receiving PCM highway (with a pit rate of 2.046 Mb/S), and only audio P(, 'M is handled. In other words, this C0DEC is PCM for audio
Used in the same way as CODEC.

In the second state, the transmitting PCM output terminal 7 is
s data #j [connected, and the receiving PCM input terminal 8 is connected to the high speed PCM highway.

In the third state, the cape, output terminal 7 is connected to the PCM wire and input terminal 8 is connected to the 64b/S data line.

In the control signal 17 shown in FIG. 2, A, B.

By selecting one of C.

For example, when A is selected, the first state is selected, when B is selected, the second state is selected, and when C is selected, the third state is selected.

FIG. 3 shows PCM input control clock pulses 19. PCM output control clock 20,
and a timing chart of the preset pulse 21, the synchronizing signal 15, the PCM output terminal 7, and the PCM signal at the PCM input terminal 8.

The operations in each of the first state, second state, and third state will be described below with reference to FIGS. 2 and 3.

In the first state (N in Figure 3), the PCM input terminal 8
The audio PCM signal is synchronized to the specified time and bit rate of the PCM highway, e.g.
The 8-pit pressure aPcM is taken into the C0DEC by the 6 Mb/s clock 19, and converted into an analog audio signal by the expander 10, filter 11, and DA converter 12, as described above. On the other hand, the analog audio signal on the transmitting side passes through the A/D converter 2, filter 3, and compressor 4, and is stored in the PCM buffer register 5 at the specified time Tt, and is converted into an 8-pit compressed PCM signal by the clock 20. PCM connected to output terminal 7
output onto the highway. At this time, preset pulse 2
1 is not supplied.

Next, in the second state (jiga diagram B), the received PCM data at the input terminal 8 is transferred to the buffer register 9 by the clock 19 synchronized with the specified time and bit rate of the PCM highway, as described above. After being fetched, from the parallel output 18 of the same buffer register 9,
The preset pulse 21 is input in parallel to the output buffer register 6, and the clock pulse 20, which in this case is supplied at 64 KHz, is output to the output terminal 7.

Next, in the third state (Fig. 3C), the data at the input terminal 8 is 64KH synchronized with 64K b/s data.
After being fetched into the shift register 9 by the Z clock 19, it is input in parallel from the parallel output 18 of the same buffer register 9 to the output buffer register 6 by the preset pulse 21 in the same way as described above, and in this case, the bit rate of the PCM highway is clock pulse 20 synchronized with
As a result, the signal is output to the output terminal 7 at the specified time T.

〔Effect of the invention〕

As explained above, according to the present invention, the audio PCM-
By sharing part of CODEC.

This eliminates the need for a 64 KHz data interface, which was conventionally provided as a separate type of input/output device, and is effective in making the switching system more compact and economical.

The present invention has been illustrated in the above embodiments. Audio PCM bit rate 2.046 Mb/s and bit rate 64 Kb/s
It is not limited to the data of S.

Transmission/reception conversion of audio PCM and data PCM at other bit rates can also be carried out by appropriately determining the clocks 19 and 20 synchronized with the bit rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the audio PCM-C0DEC according to the present invention, FIG. 2 is a detailed diagram of an embodiment of the switching circuit for 64KHz data shown in FIG. 1, and FIG. , is a timing chart diagram of each part in FIG. 2. 2... A-D converter, 3... Transmission side filter, 4...
... Compressor, 5... Switch function section, 6... Output buffer register, 9... Input buffer register, 10
...Extender, 11...Reception side filter, 12...
D-A converter. Agent: Patent Attorney Katsuo Ogawa,

Claims (1)

[Claims] A circuit unit that converts the audio analog signal into a PCM signal, a PCM output buffer register for sending the PCM signal of the circuit to the outside, a PCM input buffer register that takes in the input PCM signal from the outside, and a circuit unit that converts the input PCM signal to the audio analog signal. a circuit section for converting into a signal, a circuit section for supplying timing pulses to the PCM output buffer register and the PCM input buffer register, and the PCM
The PCM signal stored in the input buffer register is
P consisting of means for supplying the CM output buffer register.
A CM codec comprising means for changing the bit rate of the PCM input signal and taking it out from the PCM output buffer register.