JPS621264U - - Google Patents
Info
- Publication number
- JPS621264U JPS621264U JP9313085U JP9313085U JPS621264U JP S621264 U JPS621264 U JP S621264U JP 9313085 U JP9313085 U JP 9313085U JP 9313085 U JP9313085 U JP 9313085U JP S621264 U JPS621264 U JP S621264U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- electronic device
- connector
- switch
- memory board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9313085U JPS621264U (enExample) | 1985-06-20 | 1985-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9313085U JPS621264U (enExample) | 1985-06-20 | 1985-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS621264U true JPS621264U (enExample) | 1987-01-07 |
Family
ID=30650531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9313085U Pending JPS621264U (enExample) | 1985-06-20 | 1985-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS621264U (enExample) |
-
1985
- 1985-06-20 JP JP9313085U patent/JPS621264U/ja active Pending
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