JPS62122168A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reproducibility and controllability by a method wherein the metallic electrodes on a semiconductor device with Shottky contacts comprising AlInAs layer and metallic electrodes are composed of dual structure with lower layer made of platinum. CONSTITUTION:Electrodes comprising e.g. Au, Ge, Ni etc. are evaporated on an AlInAs layer 3 whereto N-type impurity is added and then a sound electrode 4 and a drain electrode 5 as ohmic contacts are formed by alloying process. Furthermore, a gate electrode lower layer 6 comprising platinum Pt is formed by electron beam heating evaporation to around 400Angstrom thick. Next a gate electrode upper layer 7 around 4,000Angstrom thick comprising Au or Al etc. is formed by resistance heating evaporation on the platinum layer 6. Resultantly the gate electrode is around 4,400Angstrom thick. In such a constitution, the lower electrode layer 6 made of platinum is free from effect of oxidative reaction stabilizing the level of Schottky barrier.

Description

[Detailed description of the invention] (7) Industrial application fields The present invention relates to a semiconductor device.

In particular, it relates to the structure of a Schottky electrode formed on an AβInAs semiconductor layer.

Here, the Schottky electrode means the gate electrode of an FET and the electrode of a Schottky diode.

(a) Prior Art Several FETs using two-dimensional electron gas as a carrier have already been proposed.

An A4 InAs/Ga InAs field effect transistor will be described.

A GaInAs layer is provided on the substrate, an undoped AjgInAS layer is provided on this layer, an Al InAs layer doped with an n-type impurity is provided, and a source electrode, a drain electrode, and a gate electrode are provided on this layer. .

The source electrode and drain electrode are in ohmic contact, and current flows through them. The gate electrode is a Schottky electrode with metal attached to a semiconductor layer.

Unlike ordinary FETs, such FETs have extremely high carrier mobility.

Electrons from the n-type A6 InAs layer enter the Ga InAs layer and form a channel therein. The Ga InAs layer is undoped, has no sites for impurity atoms, and is formed only from host crystal atoms. Therefore, GaIn
Even when electrons travel in the As layer, scattering due to impurities does not occur.

This type of F
ET has fast electron mobility. Since the impurities that have lost their carriers are positively charged and attract electrons from the GaInAs layer, electrons exist only at the narrow boundary between the Aj' InAs layer and the GaInAS layer.

Since the spread in the thickness direction is substantially O, this is treated as a two-dimensional electron gas (Two Dimension El
It is called ectronGas (2DEG).

For example, for A4InAs/GaInAs FETs, C.Y., CHEN et al. “Depl.
modeModulationDop
ed ANo, 48 In0.52 As C;a
O,47InO,53AsHeterojunction
n Field Effect Transistor
s″IEEE ELECTRON DEVICE
LETTER5, vol.

EDL-3, No. 6. June 1982
It is proposed on p152-155.

The layer structure is written from above: (a) A4InAs O, 15μ
m S i doped (b) AdlnA
s 0.008μm Non-doped (c)
GaInAs (active layer) 1.5μm
It is a non-doped (d) Inp substrate.

The notation will be explained here. Since lattice matching with the substrate InP must be achieved, the composition of the A4InAs layer and b layer is not arbitrary.

It has 48% Al and 52% In and is lattice matched with InP. However, adding a suffix each time is cumbersome, so the suffix is omitted.

The same applies to Ga InAs. The absence of a suffix does not mean that the composition is arbitrary. For simplicity, the suffix is simply omitted, and the composition is determined by matching with the substrate.

Modulation Doped is sometimes translated as selective doping. Doping the layer of (a) and (b)
, because the layer (C) is not doped, but originally, when creating a superlattice structure by stacking a larger number of evictional layers, Modula
He used the term t i on Dope. For such FETs with a small number of layers, the Modulation
n Use the word Dope.

This type of FET is sometimes called a MOD FET.

This is also to distinguish it from GaAs MES FETs and the like.

Several such selective tope transistors are also proposed in Japanese Patent Publication No. 59-53714. However, the composition is different from that of the present invention.

Japanese Journal of Appl
ied Physics, vol.

19 (1980), page L225, also proposes an FET using two-dimensional electron gas as a carrier.

Japanese Patent Publication No. 59-53714 discloses (i) AlGaAs/GaAs heterojunction (
if) g? GaAs/Ge heterojunction (CdTe/InSb heterojunction Qiii) We have proposed a MODFET structure for Ga5h/InAs heterojunction.

In any case, it has source and drain electrodes, and the intermediate gate electrode is a Schottky electrode.

The mixed crystal ratios (1) and (ii) are determined by the conditions of lattice matching with GaAs, Ge, etc., and are therefore different from the mixed crystal ratios of the present invention. Although they have similar notations, they are actually different.

These FETs and the FET of the present invention are the same in that two-dimensional electron gas is used as a carrier.

The operating principle will be explained.

Since the AlInAs layer is an n-type layer, there are donor atoms that can release electrons and be fully charged. Since the GalnAS layer is non-doped, there are essentially no electrons to serve as carriers.

The electron affinity of the A4InAs layer is smaller than that of the GaInAs layer. Further, the band gap of the A3InAs layer is wider than that of the GaInAs layer.

Therefore, electrons in the AlInAs layer move to the GaInAs layer. Since the lattice and donor atoms of the Ga1nAs layer are highly charged, electrons are transferred to the A3InAs layer by Coulomb force.
drawn towards the layers. Therefore, electrons are two-dimensionally distributed only at the boundaries of the GaInAs layers.

This is a two-dimensional electron gas. Since it moves in a region where donor atoms do not exist, there is little impurity scattering and high mobility can be obtained.

Source, gate, and drain electrodes are provided on the AlInAs layer. Apply voltage between the source and drain electrodes.

A voltage applied to the gate electrode generates a depletion layer within the two-dimensional electron layer. The size of the depletion layer changes depending on the gate voltage.

The resistance between the source and drain changes depending on the size of the depletion layer. In this way, the current flowing between the drain and source can be controlled by the gate voltage.

Trans conductance is the value obtained by dividing the change in drain current by the change in gate voltage.
It's called ancd. This is proportional to carrier concentration, carrier mobility, etc.

High carrier mobility is important.

GaInAs/AlInAs which is the object of the present invention
MOD FETs are distinguished by high electron mobility.

Mobility is a function of temperature, but at room temperature it is 10,000ci
/Vsec or higher electron mobility can be obtained.

InP is often used for the substrate. To form a thin epitaxial layer on a substrate, molecular beam epitaxial method (MBE method) or metal organic chemical vapor deposition method (MOC method) is used.
VD method) is used.

As described above, the FET which is the object of the present invention using a heterojunction of an A3InAs layer and GaInAs is expected to have excellent characteristics such as high mutual conductance and high speed operation.

However, there are drawbacks such as the reverse breakdown voltage of the gate electrode being too low, and no practical product has yet been produced.

Japanese Patent Application No. 58-159800 proposes the following FET. The configuration from the bottom is: (1) Substrate (it) InP layer (non-doped) (i!f)
AllnAs layer (n type) 011^ So, 2. ,
These are the gate and drain electrodes. This is also non-doped In
Electrons are taken from the n-type AgInAs layer in the P layer to form a two-dimensional electron gas layer.

Since the InP layer has almost no impurities, there is little impurity scattering. Regarding the electron transport characteristics in the InP layer, the maximum drift velocity is about 2.5 x 10'cm/see, and the electric field where negative resistance occurs due to the electron transition effect is about 11
KV/c7n, which is very good. Therefore, it is possible to realize a field effect transistor FET that operates stably even in a high electric field.

(1) Problems to be Solved by the Invention In the above FET, aluminum was used as the gate electrode. Aluminum is deposited on top of the Al I n As layer to form a Schottky junction.

The inventor has developed an AlInAs/GaInAs FET
Many prototypes were produced. The gate electrode is Al. A3InAs/G that has been published so far by people other than the present inventor
All gate electrodes of the a1nAs FET are made of Al.

As is well known, the barrier height of a Schottky electrode is extremely sensitive to the surface condition of the material.

According to the results of numerous experiments conducted by the present inventors, it has been found that the height of the Schottky barrier of Al is widely distributed over a range of 0.58V to 0.67V. In other words, 0.
There is a width of 09V.

As described above, since the height of the Schottky barrier varies, the threshold voltage vth of the FET is also distributed over a wide range. Since the threshold voltage varies, good reproducibility and controllability cannot be obtained.

The threshold voltage vth can be expressed by the following equation.

Here, φb: Schottky barrier height q: unit charge NO: donor density in AlInAs ε: A
Relative permittivity d of the llnAs layer: Thickness ΔEc of the AlInAs layer: Band edge discontinuity.

FETs include normally-off transistors and normally-on transistors. A normally-off type transistor is such that the drain current is 0 when the gate voltage is Ov.
ent) Also called type.

A normally-on transistor is a transistor whose drain current is not 0 when the gate voltage is OV. The gate is controlled by a negative voltage. Depletion (
It is also called Depletion type.

Both types have advantages and disadvantages. AlInAs/G
Any type of aInAs MOD FET can also be manufactured.

In an FET using a Schottky contact for the gate electrode, the normally-on type (depletion) allows more current to flow through the load. Therefore, it is possible to drive a large load. Furthermore, the operating speed of the circuit becomes faster.

However, normally-on type FETs require voltage shifting when connected in multiple stages, which poses a problem.

When normally-on FETs are connected in multiple stages, it is necessary to use the positive output voltage of the previous stage to drive the gate voltage of the next stage FET, which has an amplifying effect on a negative gate voltage.

Since the output voltage level of the previous stage and the gate voltage level of the next stage are different, the voltage must be shifted.

A Schottky diode is often used for this voltage shift. That is, the forward potential difference of the Schottky diode is utilized.

This is because the voltage can be shifted by a constant DC voltage.

Therefore, in order to configure a circuit by integrating a large number of normally-on type FETs on the same substrate, it is necessary to integrate a large number of Schottky diodes on the same substrate. In this way, in addition to the gate electrode, it can also be used as a diode electrode.
Requires Schottky electrode.

As mentioned above, the FE with the kl I nAs layer as the top layer
In order to construct an integrated circuit including T, it is necessary to fabricate a Schottky diode that makes Schottky contact with the AlInAs layer.

The potential difference generated across this Schottky diode is affected by the height of the Schottky barrier.

In order to improve the yield of integrated circuits, it is necessary to eliminate this Schottky barrier height distribution. This is because the voltage drop caused by the diode must be constant.

However, as mentioned above, in the conventional Schottky diode using Al, the barrier height is 0.
．． It has the disadvantage that it is distributed over a range of 58V to 0.67V.

If the barrier voltage of the Schottky diode varies, the forward voltage drop will also vary. Therefore, when using a Schottky diode for voltage shifting,
The gate bias voltage of the FET will be different. For this reason, the amplification factor and the average level of the output voltage vary among a large number of FETs.

A) Objective of the invention A, g
It is an object of the present invention to improve the reproducibility and controllability of a semiconductor device having a Schottky contact to InAs.

Here, the semiconductor device includes both FETs and diodes.

(4) Means for solving the problem In the present invention, in a semiconductor device having a Schottky contact consisting of an Al I nAs layer and a metal electrode, the metal electrode has a two-layer structure, and the lower layer is made of platinum. It is.

Further, depending on the required characteristics, the upper layer may be made of gold.

That is, the metal electrode is changed from Al to Pt/X. X is a suitable metal other than PT, although it may be desirable to use Au.

In the conventional structure, the reproducibility of the Schottky barrier height,
Regarding the controllability, the reason why good characteristics were not obtained was considered by the present inventor as follows.

Conventionally, A is used as a metal for Schottky contact.
[is easily oxidized.

In order to form a Schottky electrode, Al is evaporated, but
At this time, the interface between the n-type AgInAs layer and the Aβ electrode layer is likely to be contaminated with oxides or the like.

As is well known academically, Schottky contacts are extremely sensitive to the surface conditions of semiconductors. Even slight contamination can cause the height of the Schottky electrode to rise or fall significantly.

Although Al vapor deposition is performed in a high vacuum, it is thought that a small amount of oxygen and oxides remain in the vapor deposition apparatus. This noise oxygen and the like will react with the heated A4 and oxidize it.

Partial oxidation of Atl causes large variations in the Schottky barrier height of the prototype devices. The inventor of the present invention thought like this.

In this case, either Al should be prevented from being oxidized at all, or even if oxidation is unavoidable, the degree of oxidation should be made uniform.

However, Al is a metal that is extremely easily oxidized, and
It is very difficult to control the oxidation of l.

Even if the degree of vacuum in the vapor deposition apparatus is increased, oxidation cannot be completely prevented.

In the first place, it has not yet been confirmed whether Al is oxidized or not, and therefore there is currently no method for measuring the degree of oxidation of Al at a Schottky electrode. Therefore, how do we control the oxidation of Al? Besides that, how can we detect the degree of oxidation of An?
A problem arises.

AJI? can be easily deposited by resistance heating, making it extremely useful as an electrode material.

However, the inventor considered that an Al main electrode was not possible to solve the problem of variations in the Schottky barrier. Oxidation of Al cannot be prevented and is difficult to control.

Therefore, a metal with low reactivity such as oxidation and excellent conductivity is used as the Schottky electrode material instead of Al.

Platinum P is a metal with low reactivity to oxidation, etc.
There is t1 gold Au. These metals also have excellent conductivity.

However, gold may easily react with the Al InAs mixed crystal semiconductor due to heat treatment or the like. Therefore, the height of the Schottky barrier may vary for other reasons.

It must be a metal that does not react with either the Al I nAs semiconductor layer or O. Such materials include platinum Ptl. The inventor thought as follows.

However, making a Schottky electrode using only platinum (Pt) is problematic in another sense.

The metal electrode in the Schottky contact must have a thickness that is at least as thick as possible. To improve high frequency characteristics,
It is necessary to lower the wiring resistance of the electrode section. Therefore, a film thickness of at least about 1000 A is required.

Platinum has a high electrical conductivity and a high melting point (1769° C.), so it cannot be deposited by resistance heating.

In the case of A4, it can be deposited very easily by resistance heating.

Therefore, platinum vapor deposition is generally performed by electron beam heating. A platinum target is irradiated with an electron beam, and the kinetic energy of the electrons heats the platinum to a high temperature above its melting point. The platinum turns into vapor and flies out from the target.
An A6InAs layer is deposited on the top semiconductor wafer.

At this time, the platinum target is heated to a temperature above its melting point, resulting in a very high temperature. The radiant heat emitted from this target is powerful. The temperature of the semiconductor Ukoha sample increases as it receives strong radiant heat from the platinum target.

If you move the sample far enough away from the target, you can reduce the amount of radiant heat it receives, but if you do that, it will be difficult for platinum vapor to reach the sample, so you cannot move it too far away. If the deposition time is increased in order to make the platinum electrode thicker, the time for receiving radiant heat will be longer, and the temperature of the semiconductor substrate, which is the sample, will rise excessively.

When a platinum layer with a thickness of 1000λ is deposited, the temperature of the sample surface increases significantly, which deteriorates the characteristics of the device.

The platinum layer cannot be made too thick.

However, the thickness of the entire electrode is 1000 mm to lower the resistance.
About λ is required.

Therefore, the inventor thought that the electrode should have a two-layer structure. It is sufficient to make it two layers and use platinum (Pt) for the part that contacts the AlInAs layer.

A metal other than platinum that does not excessively raise the temperature of the sample surface during vapor deposition may be deposited on the platinum. Since this metal does not come into contact with Al I nAs, A
It may be a metal that reacts with the lInAs layer.

Furthermore, since this metal does not determine the height of the Schottky barrier, it may be a metal that is easily oxidized.

The upper metal layer of the two-layer electrode can be, for example, gold Au. Gold can be deposited by resistive heating, and the deposition does not significantly increase the temperature of the sample. Furthermore, since it has good conductivity, resistance can be lowered by increasing the thickness of the electrode. If the total thickness of the platinum layer and the metal is 1000X or more, the high frequency characteristics are good.

The upper metal layer of the two-layer electrode may be made of Al, for example. Although this may be oxidized, since it is attached on top of Pt, it does not affect the height of the Schottky barrier.

Further, the upper limit of the thickness of platinum (Pt) is determined depending on the deposition time at which the substrate is heated and begins to be damaged. this is,
It depends on the accelerating voltage of the electron beam and 7 lux, the distance between the target and the substrate, and the properties of the substrate. The upper limit of the thickness is approximately 1000λ.

The lower limit of the thickness is determined by the fact that the upper layer metal does not contact and react with the 7JInAs JW, and is about 50λ.

Therefore, the thickness of the PT layer below the electrode is between 50λ and 100λ.
It is desirable that it be about 0λ.

The present inventor provided a gate electrode with a two-layer structure consisting of platinum and gold on the A4 I nAs layer, and
/GaInAsMOD FET was sampled.

As a result, the barrier height of the Schottky contact between the gate electrode and the n-type Al I nAS mixed crystal semiconductor was set to 0.77V to 0.7V.
It became possible to control the voltage within the range of 0.01V of 78V.

Therefore, the controllability and reproducibility of the threshold voltage of the MOD FET can be significantly improved.

(B) Example I (FET) According to FIG.
An example applied to a MODFET will be described.

The semiconductor substrate 1 is a substrate made of InP or the like. This is a semi-insulating substrate.

A non-doped Ga InAs mixed crystal semiconductor layer 2 is formed on a semiconductor substrate 1 . This is an organometallic decomposition method (
OMVPE) or molecular beam epitaxial growth (MBE). The thickness is, for example, 05 μm.

Furthermore, an AlI nAs mixed crystal semiconductor layer 3 containing n-type impurities is also epitaxially grown thereon. The thickness is, for example, about 500λ (0.01 μm).

For example, it is an Ad InAs layer containing Si as an n-type impurity on the order of 4×10c1n''. This Si supplies electrons, which are carriers.

The threshold voltage of the FET changes depending on the concentration of the n-type impurity and the thickness of the AlI nAs layer. This is clearly expressed in equation (1). Even if the height of the Schottky barrier is determined, vth depends on the impurity concentration and the thickness of the Al I nAs layer.
can change.

Therefore, depending on the design value of the threshold voltage vth, the n-type impurity concentration and the thickness of the A4 InAs layer may be made different from the above values.

Furthermore, depending on the required characteristics, non-doped A4
An InAs spacer layer (not shown) is made of undoped GaI
It may be interposed between the nAs layer 2 and the n-type AnInAs layer 3.

Next, electrodes made of, for example, Au, Ge1Ni, etc. are deposited on the AA7I nAs layer doped with n-type impurities, and alloyed to form source electrode 4 and drain electrode 5, which are ohmic contacts.

The above configuration is publicly known.

Furthermore, a gate electrode lower layer 6 made of platinum Pt was formed on the n-type AlInAs layer 3 by electron beam heating evaporation or the like. The thickness was approximately 400°fi when closed.

On top of the platinum PT layer, Au is further deposited by resistance heating evaporation method.
Alternatively, the gate electrode upper layer 7 made of Al etc.
It was formed with a thickness of . The thickness of the gate electrode is approximately 4400^.

Since it is platinum (Pt), it is not affected by oxidation reactions and the height of the Schottky barrier is stable. Also, since platinum is thin, the deposition time is short. Therefore, there is no possibility that the sample will deteriorate due to temperature rise.

Rewriting this example from the bottom layer: I InP substrate (semi-insulating) Z GalnAs layer (non-doped)
0.5μm3 A4InAs layer (n type)
500 A4.5 AuGeNi (ohmic electrode, drain/source) 6 Pt (”
Yo'/) Key electrode lower layer) 40oX7 Au or Al
(Electrode upper layer) 4000 A.

) Example II (FET) The present invention is illustrated in FIG.
An example applied to a MODFET will be described.

Almost the same as the previous example, but with non-doped GaInAs
The difference is that a non-doped InP layer 2 is formed instead of the layer. Everything else is the same. Writing from the bottom layer: I InP substrate (semi-insulating) Z InP layer (non-doped) 0.
5μma AlInAs layer (n type) 50
0 A4.5 AuGeNi (Ohmic electrode, drain/source) 6 Pt (Schottky electrode lower layer) 400^7 Au or An (electrode upper layer) 4000 A.

n-type kl I nAs is, for example, Si 4X1017
>-3 or so was added. The same point as in the previous example is that these electrons form a two-dimensional electron gas in the InP layer.

3) Embodiment 1 (Diode) An embodiment in which the present invention is applied to a diode will be described with reference to FIG.

On the substrate 1, a GaInAs mixed crystal semiconductor layer 2 or I
An nP semiconductor layer 2 and an AlInAs mixed crystal semiconductor layer 3 are epitaxially grown.

An ohmic electrode made of Au1Ge1Ni is deposited on the AlInAs layer 3, and a cathode electrode 9 is formed by alloying.

Further, on the Ad InAs layer 3, platinum PT is deposited to a thickness of about 400 nm using an electron beam heating method or the like. This is the lower layer 10 of the anode electrode 12. Platinum PT is A4
A metal electrode lower layer is formed in Schottky contact with the InAs layer.

A metal electrode upper layer 11 made of gold or Al is formed on the platinum PT by a resistance heating vapor deposition method or the like.

This thickness is, for example, 4000×.

This Schottky diode is a diode fabricated on the same substrate as Examples I and II. Therefore, the structure of the layers is the same as in those examples.

In Examples ■ and ■, depletion (depletion)
When an n) type FET is manufactured, it is necessary to level shift the output voltage when connecting in multiple stages. For this reason, a Schottky diode is formed and used on the same substrate. In the present invention, since the voltage drop across the Schottky electrode (anode) is constant, the magnitude of the level shift is also constant.

Therefore, the bias level of the FET and the amplification factor become the same.

i) Effects Regarding the present invention, the height of the Schottky barrier was measured from the capacitance-voltage characteristics at I MH2, and it was found that it was controlled within the range of 0.77V to 0.78V within the plane of a 2-inch wafer. was confirmed. In other words, it falls within a narrow range of 0.01V, with little variation.0 According to the conventional A4 electrode, 0.58V to 0.67V
The range of variation was as wide as 0.09V.

According to the present invention, it is possible to significantly improve the reproducibility and controllability of the characteristics of a semiconductor device such as an FET or a Schottky diode in which a Schottky contact is provided on a kl I nAs layer.

[Brief explanation of drawings]

FIG. 1 shows an example of the present invention.
A longitudinal cross-sectional view of InAsMOD FET. FIG. 2 shows another embodiment of the present invention.
FIG. 1 is a vertical cross-sectional view of an I nPMOD FET. FIG. 3 is a longitudinal sectional view showing an example in which the present invention is applied to a Schottky diode whose surface layer is kl I nAs. 1... Semiconductor substrate 2...
...Ga InAs mixed crystal semiconductor layer 2 ...
......InP semiconductor layer 3...
... n-type Al I nAs mixed crystal semiconductor layer 4 ...
・・・・・・Source electrode 5・・・・・・・・・・・・
Drain electrode 6...Gate electrode lower layer 7...Gate electrode upper layer 8...
......Gate electrode 9...
...Cathode electrode 10...Metal electrode lower layer 11...Metal electrode upper layer 12
・・・・・・・・・・・・Anode electrode inventor Goro Sasaki Figure 1 Figure 3 Figure 2

Claims (7)

[Claims] (1) A semiconductor device having a Schottky contact made of an AlInAs mixed crystal semiconductor and a metal electrode, characterized in that the metal electrode has a two-layer structure, and the lower layer is made of platinum. (2) The semiconductor device according to claim (1), wherein the upper layer of the metal electrode having a two-layer structure is made of gold. (3) The thickness of the lower platinum layer of the metal electrode with a two-layer structure is 5
The semiconductor device according to claim (1) or (2), characterized in that the thickness is in the range of 0 Å to 1000 Å. (4) The semiconductor device is a Schottky diode comprising an electrode that makes ohmic contact and an electrode that makes Schottky contact.
The semiconductor device according to any one of paragraph (3). (5) A semiconductor device has an AlInAs mixed crystal semiconductor layer on a GaInAs mixed crystal semiconductor layer on a substrate, and the A
A field effect transistor having a gate electrode provided on an lInAs mixed crystal semiconductor layer, and a source electrode and a drain electrode provided on both sides of the gate electrode, wherein the gate electrode is a Schottky contact. The semiconductor device according to any one of paragraphs (1) to (3). (6) A semiconductor device is provided on a substrate and has an AlInAs mixed crystal semiconductor layer on an InP semiconductor layer, a gate electrode is provided on the mixed crystal semiconductor layer, and a source electrode and a drain electrode are provided on both sides of the gate electrode. It is a field effect transistor provided with
A semiconductor device according to any one of claims (1) to (3), characterized in that the gate electrode has a Schottky contact. (7) The semiconductor device according to claim (1), wherein the upper layer of the metal electrode having a two-layer structure is made of Al.