JPS62120973A - Two-side simultaneous lapping method for gaas wafer - Google Patents

Two-side simultaneous lapping method for gaas wafer

Info

Publication number
JPS62120973A
JPS62120973A JP60260669A JP26066985A JPS62120973A JP S62120973 A JPS62120973 A JP S62120973A JP 60260669 A JP60260669 A JP 60260669A JP 26066985 A JP26066985 A JP 26066985A JP S62120973 A JPS62120973 A JP S62120973A
Authority
JP
Japan
Prior art keywords
lapping
wafer
gaas
gaas wafer
abrasive grains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60260669A
Other languages
Japanese (ja)
Inventor
Hiroki Akiyama
弘樹 秋山
Toshiya Toyoshima
豊島 敏也
Akitetsu Takahashi
高橋 昭哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP60260669A priority Critical patent/JPS62120973A/en
Publication of JPS62120973A publication Critical patent/JPS62120973A/en
Pending legal-status Critical Current

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  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To provide easier manufacture of GaAs wafer with precision and less amount of warp by mixing a grinding liquid incl. abrasive grains for lapping with an etching liquid having effect to dissolve GaAs chemically between the upper and lower surface reference boards. CONSTITUTION:Each GaAs wafer is nipped by an upper and a lower surface reference board for lapping which operate at different revolving speeds, and both sides of the ware are lapped simultaneously. The processing distortion layer generated at the surface of the GaAs wafer in the course of said lapping operation is dissolved by the etching liquid contained in the grinding liquid while it serves grinding with abrasive grains contained therein, and then is removed to relieve stresses at the surface of wafer, which should contribute to reduction of a warp otherwise generated there. At this time, the ratio of the mechanical grinding speed by the abrasive grains for lapping to the chemical dissolution speed by etching liquid shall preferably the approximately ten to one.

Description

【発明の詳細な説明】 [発明の背景と目的] 本発明はGaAsウェハの両面を同時にラッピングする
方法に関するものである。
BACKGROUND AND OBJECTS OF THE INVENTION The present invention relates to a method for simultaneously lapping both sides of a GaAs wafer.

従来、ウェハの両面同時ラッピング方法は、ブレートに
ウェハを接着して行なう片面ラッピング方法に比べて、
ウェハの仕上り厚みの寸法精度が優れていることから、
例えば、3iウエハにおいては最も一般的に採用されて
いる方法である。
Traditionally, the method of lapping both sides of a wafer at the same time is faster than the single-side lapping method, which involves bonding the wafer to a plate.
Due to the excellent dimensional accuracy of the finished wafer thickness,
For example, this is the most commonly used method for 3i wafers.

しかしながらGaAsウェハにおいては、同様な方法で
両面同時ラッピングを行なうと、ウェハに大きなそりが
発生する。これはラッピング用砥粒による機械的な作用
で発生する加工歪が原因であり、材質的にGaAsの場
合は、結晶の異方性が強く、一般にデバイス等に使用さ
れる(100)面ウェハでは、直交する[ OT T 
1方向および[OT1]方向について、(100)面を
基準面としたとき、相互に反対方向に弯曲状態を示すい
わゆる鞍形のそりとなる。一般にウェハの両面同時ラッ
ピング方法では、ウェハが特に固定されていないため、
研磨作用の進行中に発生する下降歪に基づく上記のそり
現象は、研磨Mの増加に伴い増大する。例えば、直径5
0m、厚さ450μmのn型GaAsウェハ・では、両
面研磨41μmに仏 対して約0.1mの割合でそり吊fffl’l大する。
However, when a GaAs wafer is simultaneously lapped on both sides using a similar method, large warpage occurs in the wafer. This is caused by processing distortion caused by the mechanical action of the lapping abrasive grains.In the case of GaAs, the crystalline anisotropy is strong, and (100) wafers, which are generally used for devices, etc. , orthogonal [OT T
When the (100) plane is used as the reference plane for the 1 direction and the [OT1] direction, the curvature becomes a so-called saddle-shaped curvature that is curved in mutually opposite directions. In general, in the simultaneous double-sided wafer lapping method, the wafer is not particularly fixed, so
The above-mentioned warping phenomenon based on the downward strain occurring during the polishing action increases as the polishing M increases. For example, diameter 5
For an n-type GaAs wafer with a thickness of 0 m and a thickness of 450 μm, the warpage is increased by about 0.1 m for double-sided polishing of 41 μm.

そりの原因は、機械的に加えられた応力を起因とするも
のであり、砥粒の大きざ、加工圧力、ラッピング用上下
定盤の回転速度等の加工条件を調整しても、工業的に有
効なラッピング速度である0、5〜20μm/分を得る
ためには、上記のそり現象は回避できないものであった
The cause of warpage is mechanically applied stress, and even if processing conditions such as the size of the abrasive grains, processing pressure, and rotation speed of the upper and lower surface plates for lapping are adjusted, it will not work industrially. In order to obtain an effective lapping speed of 0.5 to 20 μm/min, the warping phenomenon described above cannot be avoided.

本発明は、上記の難点を解決し、そり聞が少なく寸法精
度の高いGaAsウェハを得ることができるGaAsウ
ェハの両面同時ラッピング方法を提供することを目的と
するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for simultaneously lapping both sides of a GaAs wafer, which solves the above-mentioned difficulties and can obtain a GaAs wafer with less warpage and high dimensional accuracy.

[発明の概要] 本発明は、GaAsウェハをそれぞれ回転速度の異なる
ラッピング用の上部定盤と下部定盤との間に挟持して行
なうGaAsウェハの両面同時ラッピング方法において
、前記上部定盤と下部定盤との間にGaAsを化学的に
溶解する作用を有するエツチング液にラッピング用砥粒
を混入した研磨液を介在させることを特徴とするもので
ある。
[Summary of the Invention] The present invention provides a method for simultaneously lapping both sides of a GaAs wafer in which the GaAs wafer is sandwiched between an upper surface plate and a lower surface plate for lapping, each having a different rotation speed. This is characterized in that a polishing liquid containing lapping abrasive grains mixed in an etching liquid having the effect of chemically dissolving GaAs is interposed between the polishing plate and the surface plate.

本発明は、ラッピング作業によりGaAsウェハ表面に
発生する加工歪層を、研磨作用が進行中に、研磨液中の
エツチング液により溶解除去することによりウェハ表面
の応力を解消し、そりを低減するものである。従って、
本発明は、使用するラッピング用砥粒の粒径1種類、お
よびエツチング液の種類等によって限定されるものでは
なく、ン また、ラッピI装置の構造、材質等により限定されるも
のでもない。
The present invention eliminates stress on the wafer surface and reduces warping by dissolving and removing a strained layer generated on the surface of a GaAs wafer during the lapping operation using an etching solution in the polishing solution while the polishing operation is in progress. It is. Therefore,
The present invention is not limited by the particle size of the lapping abrasive grains used or the type of etching solution used, nor is it limited by the structure, material, etc. of the lapping I device.

本発明を効果的に行うには、ラッピング作用のうち、ラ
ッピング用砥粒による機械的な研削速度と、エツチング
液による科学的な溶解速度との比をほぼ10:1にする
ことが望ましい。図にラッピング速度10μm/分のと
ぎのエツチング速度とそりの大きさの関係を示す。
In order to carry out the present invention effectively, it is desirable that the ratio of the mechanical grinding speed by the lapping abrasive grains to the scientific dissolution rate by the etching liquid be approximately 10:1 in the lapping action. The figure shows the relationship between the etching speed at a lapping speed of 10 μm/min and the warpage size.

[実施例] この実施例では、両面ラッピング装置として、直径63
0mのガラス製のラッピング用の上部定盤および下部定
盤を有し、ウェハを保持するキャリアを回転させる中心
歯車および太陽歯車で構成される3ウ工イ方式の装置を
用ε\た。GaAsウェハ材料としては、厚さ500μ
m、直径50#IのSiドープ、n型の(100)面ウ
ェハを用いた。1枚のキャリアに上記ウェハを6枚設置
し、ラッピング装置には5枚のキャリアを設置し、上部
定盤を静かに下降させ、上記ウェハを下部定盤との間に
挟持してウェハに1000/cm2の圧力を加えた。そ
して研磨液として、粒径5μmのアルミナ微粉、脱イオ
ン水、アンモニア水、過酸化水素水を重量化で2:10
:2:1の割合に混合したものを上部定盤と下部定盤と
の間に流し込み、下部定盤を15 rpn+ 、上部定
盤を5 romの回転速度で回転させた。そして、ウェ
ハの厚さが400μmになったところで定盤の回転を止
めラッピング作業を終了し、ウェハのそり儀を干渉縞法
により測定したところ6μm以下であった。
[Example] In this example, a double-sided wrapping device with a diameter of 63 mm is used.
A three-way system was used, which had an upper surface plate and a lower surface plate made of glass with a length of 0 m, and consisted of a center gear and a sun gear that rotated a carrier holding the wafer. GaAs wafer material has a thickness of 500μ
A Si-doped, n-type (100) wafer with a diameter of 50#I was used. Six of the above wafers are placed on one carrier, five carriers are placed on the lapping device, the upper surface plate is gently lowered, the above wafer is held between it and the lower surface plate, and the wafers are placed at 1000 wafers. A pressure of /cm2 was applied. As a polishing liquid, fine alumina powder with a particle size of 5 μm, deionized water, aqueous ammonia, and hydrogen peroxide were mixed in a ratio of 2:10 by weight.
The mixture at a ratio of :2:1 was poured between the upper surface plate and the lower surface plate, and the lower surface plate was rotated at a rotation speed of 15 rpn+ and the upper surface plate at a rotation speed of 5 ROM. Then, when the thickness of the wafer reached 400 μm, the rotation of the surface plate was stopped and the lapping operation was completed, and the warpage of the wafer was measured by the interference fringe method and was found to be 6 μm or less.

さらにこのウェハをアンモニア水、過酸化水素水、水の
容積比が2:1 :5のエツチング液で両面をそれぞれ
5μmずつ溶解させた後、再びそりmを測定したところ
4μm以下であった。
Further, after this wafer was dissolved by 5 μm on each side with an etching solution having a volume ratio of ammonia water, hydrogen peroxide solution, and water of 2:1:5, the warpage m was measured again and found to be 4 μm or less.

なお比較例として、上記実施例と同じ装置を用い、研磨
液としては粒径5μmのアルミナ微粉と脱イオン水を、
重fd比で1=5の割合に混合したもの用い、上記実施
例と同じ回転速度および加圧力で同様にラッピング作業
を行なったところ、ウェハのそりMは15μmと大きか
った。
As a comparative example, the same equipment as in the above example was used, and the polishing liquid was alumina fine powder with a particle size of 5 μm and deionized water.
When lapping was performed in the same manner as in the above example using a mixture having a weight/fd ratio of 1=5 and the same rotational speed and pressure as in the above example, the warp M of the wafer was as large as 15 μm.

[発明の効果] 以上説明したように、本発明によれば、そり吊が少なく
、寸法精度の高いGaAsウェハを容易に製造すること
ができるというすぐれた工業的効果を奏することができ
る。
[Effects of the Invention] As described above, according to the present invention, excellent industrial effects can be achieved in that GaAs wafers with less warpage and high dimensional accuracy can be easily manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例によるラッピング速度10μm/
分のときのエツチング速度とそりの大きさとの関係を示
した線図である。
The figure shows a wrapping speed of 10 μm/1 according to an embodiment of the present invention.
FIG. 3 is a diagram showing the relationship between the etching speed and the warpage size in minutes.

Claims (2)

【特許請求の範囲】[Claims] (1)GaAsウエハをそれぞれ回転速度の異なるラッ
ピング用の上部定盤と下部定盤との間に挟持して行なう
GaAsウエハの両面同時ラッピング方法において、前
記上部定盤と下部定盤との間にGaAsを化学的に溶解
する作用を有するエッチング液にラッピング用砥粒を混
入した研磨液を介在させることを特徴とするGaAsウ
エハの両面同時ラッピング方法。
(1) In a simultaneous lapping method for both sides of a GaAs wafer, in which the GaAs wafer is sandwiched between an upper surface plate and a lower surface plate for lapping, each having a different rotational speed, there is a gap between the upper surface plate and the lower surface plate. A method for simultaneously lapping both sides of a GaAs wafer, characterized by interposing a polishing liquid in which lapping abrasive grains are mixed into an etching liquid that has the effect of chemically dissolving GaAs.
(2)前記エッチング液はアンモニア水と過酸化水素水
とを含有している特許請求の範囲第1項記載のGaAs
ウエハの両面同時ラッピング方法。
(2) The GaAs according to claim 1, wherein the etching solution contains aqueous ammonia and aqueous hydrogen peroxide.
A method for simultaneously lapping both sides of a wafer.
JP60260669A 1985-11-20 1985-11-20 Two-side simultaneous lapping method for gaas wafer Pending JPS62120973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60260669A JPS62120973A (en) 1985-11-20 1985-11-20 Two-side simultaneous lapping method for gaas wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60260669A JPS62120973A (en) 1985-11-20 1985-11-20 Two-side simultaneous lapping method for gaas wafer

Publications (1)

Publication Number Publication Date
JPS62120973A true JPS62120973A (en) 1987-06-02

Family

ID=17351120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60260669A Pending JPS62120973A (en) 1985-11-20 1985-11-20 Two-side simultaneous lapping method for gaas wafer

Country Status (1)

Country Link
JP (1) JPS62120973A (en)

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