JPS6211812B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that a filter circuit includes a switch, a capacitor and an amplifier controlled by a predetermined clock phase, and is provided with an operational amplifier, the output terminal of the operational amplifier and an inverter. The present invention relates to an electric filter circuit using at least one pseudo-inductance, with a capacitor connected between the input terminals and a non-inverting input terminal connected to a fixed reference potential, for example earth potential.

The above-mentioned switch filter is described in the paper ``Switched Capacitor Filter Design Coding Bilinear Z Transform'' magazine ``IEEE Transactions on Circuits.
and Systems” Vol.Cas―25, No.12, 1978
December, 1979, pp. 1039-1044, and the article "Switched Capacitor Circuit Bilinearly Equivalent to Floating Inductor or FDNR" magazine "Electronics Letters" February 1, 1979.
Vol. 15, No. 387 and page 88, it is already known. In this case, we are dealing with a filter that processes not a temporally continuous analog signal as it would normally be, but a temporally separated signal in the form of a sample, the samples being synchronized to the clock frequency F. and correspondingly the expression T=1/
T through F is called the clock period. Circuits for generating such samples are well known and need not be described in detail here. However, the following is assumed below. That is, such a sampling circuit can be connected before or after the circuit shown in each case, so that on the one hand the sample taken from the analog signal is supplied to the input side of the filter circuit;
Moreover, the signal obtained on the output side can be converted back into a temporally continuous analog signal. The important industrial advantages of such filters are: That is, the coil is simulated by an active switch element and a capacitor and is therefore suitable for monolithic integration of many filter circuits. In this case, it is desirable to use primarily known operational amplifiers as amplifiers, on the one hand requiring as few switching elements as possible, and on the other hand also ensuring the stability of such circuits. In the known circuit, the inverting input terminal of the operational amplifier is likewise connected to the output terminal via a capacitor and is therefore subjected to some degree of negative feedback. However, it has been found that the operational amplifiers used are sometimes not coupled with negative feedback or require a high degree of common mode pushing. This is because during a given switching phase the non-inverting input terminal of the operational amplifier is not subjected to short-term negative feedback or is not constantly held at ground potential. Furthermore, it is clear that the implementation of the capacitors is carried out in the manner of MOS technology and that in these implementation methods the ground capacitances inevitably associated with floating MOS capacitors can cause considerable impairment of the filter function.

The object of the invention is to provide a circuit for simulating a coil which can be used as a floating and grounded coil in so-called switched capacitor filters and which can be realized actively, with as few disturbances caused by the switching process as possible. It turns out. A circuit for realizing a floating parallel resonance is also provided, the circuit technology of which requires approximately only as many switch elements as there are simulated inductances.

Based on the filter circuit described at the beginning, according to the present invention, this problem is solved as follows. That is, from the inverting input terminal of the operational amplifier to the first
A switch is connected to the circuit point, and a capacitor is connected from this circuit point to the reference potential.
and a switch is connected between a first circuit point and a second circuit point, a capacitor is connected from this second circuit point to a reference potential, and a switch is connected between a first circuit point and a second circuit point;
A switch is connected from the circuit point to the inverting input terminal of the operational amplifier, another switch is connected between the second circuit point and the output terminal, and the other switch is connected to the first input terminal. and a second circuit point, and the switches close simultaneously during one clock phase and the switches close sequentially during subsequent non-overlapping clock phases.

Embodiments of the present invention will be described below with reference to the drawings.

In the embodiment of FIG. 1, an operational amplifier 10 is shown, the non-inverting input terminal 12 of which is connected to a reference potential, in this case earth potential.
The output terminal of the operational amplifier is indicated by 13, the inverting input terminal is indicated by 11, and a capacitor 14 is connected between the output terminal 13 and the inverting input terminal 11, and the capacitance value of this capacitor is C/4.
In this embodiment, it is advantageous to have . Further switches S13, S14, S15, S1 are installed in the middle of the circuit.
6 and S23, of which switches S13 leads to circuit point 19, and switches S15 and S16 lead to circuit point 20. Circuit point 19 and circuit point 20 are connected via switch S14, and furthermore, circuit point 19 and earth potential 18
A capacitor 16 is connected between the circuit point 19 and the reference potential 18, and a capacitor 15 is connected between the circuit point 19 and the reference potential 18. The advantageous embodiment shown is that the simulation of a lossless coil is achieved with a capacitance value of C/3 of capacitor 16 when capacitor 14 has a capacitance value of C/4; Assume that the value is C.
Circuit point 20 is connected to one upper input terminal 17 via switch S23. The lower input terminal is indicated at 21. Therefore, in this case the lower input terminal 21 is also connected to the reference potential 18. When a voltage U _(z) is applied between terminals 17 and 21, a current I _(z) flows through the circuit.

The switch symbols have been chosen as follows in FIG. 1 and in the other figures. That is, the switch S is shown in relation to a two-digit number, the second digit of which corresponds to the clock phase at which the switch is to close.

The individual clock phases are shown in Figure 2.
The time during which each individual switch is closed is represented by a time line extending above the reference line.
It is assumed that the individual clock phases, e.g. to be represented by clock phases 3, 4, 5 and 6, do not overlap, and only if the switch operating in clock phase 3 has already opened is the switch closed, e.g. by clock phase 4. It won't happen. This applies to other switches as well. Also shown in FIG. 2 is the predetermined clock period T mentioned at the beginning.

Assuming these things and considering the circuit shown in FIG. 1, switches S13 and S23 operate during clock phase 3, and switch S14 operates during clock phase 4.
It can be seen that switch S15 must be closed during clock phase 5 and switch S16 must be closed during clock phase 6.

In the implementation shown in FIG. 1 of the grounded inductance, the ground capacitance has no effect. This is because the necessary MOS capacitors are either grounded or have one electrode connected to the output terminal of a low impedance operational amplifier. Furthermore, the non-inverting input terminal 11 of the operational amplifier is always connected to ground potential and furthermore always connected to negative feedback by the capacitor 14.

In the electrical equivalent circuit of FIG. 3, the effect of the circuit according to FIG. 1 between terminals 17 and 21 is readily apparent. The impedance Z of the circuit is then given by the formula Z=s
×L=Ψ×Rc, and then Rc=
T/2C, L=T ² /4C applies. Furthermore, S=Σ
+jΩ defines the complex frequency variable of the reference filter, and the value Ψ=I/2×S takes into account the so-called Ψ transformation, the theoretical content of this Ψ transformation being known and This Ψ transformation will be further explained below in connection with the present invention. Rc is a so-called transient resistance, and the term "step resistance" has become common in English.

This advantage is fully maintained in the embodiment of FIG. 4, where a floating inductance implementation is shown, thus an inductance with neither terminal connected to a reference potential. However, in this case an impedance of the coil terminals to ground is added, which can often be eliminated again by clever arrangement of the entire circuit and in each case by the use of an additional amplifier.

In contrast to FIG. 1, in the circuit according to FIG. 4, another switch S33 is arranged between the input terminal 21 and the circuit point 2
Reach 5. A switch S456 leads directly from the circuit point 25 to the non-inverting input terminal 12 of the operational amplifier 10, which is connected to ground potential. Switch S3
3 is closed during clock phase 3, like switch S23, while switch S456 is closed during clock phases 4, 5, and 6. A parasitic circuit capacitance occurs between circuit point 25 and ground potential, and this capacitance is
It is shown by a broken line, and the capacitance value is denoted by C'. Similarly, the explanation already given for FIG. 3 applies to the electrical equivalent circuit of FIG. 5, and the mathematical symbols obtained here are also written as they are on the individual circuit elements. terminals 17 and 21 accordingly
A floating inductance is obtained between terminals 2 and 2.
A bleeder resistance R'=T/C' is formed between R1 and the reference potential, and a parasitic capacitance having a value C'/2 is formed in parallel with this.

The embodiment of FIG. 6 shows an implementation of the ground inductance according to FIG. 1 with reduced level control of the operational amplifier. Such a circuit is correspondingly constructed when realizing a floating inductance according to FIG. A comparison of FIG. 1 and FIG. 6 shows that much of the circuitry shown here is the same. In the embodiment of FIG. 6, as opposed to FIG. 1, a further circuit point 23 is inserted after the switch S23, which circuit point consists of a switch S26 to be closed at clock phase 6 on the one hand and a capacitor on the other hand. 15'. A further circuit point 22 follows the parallel shunt capacitor 15', from which a switch S36 leads directly to the reference potential 18 and thus, in this example, to the input terminal 21. A further switch S43 is connected to circuit point 22, which on the other hand leads to capacitor 15. Similar to the above configuration, switches S26 and S36 newly added in FIG. 6 compared to FIG.
However, switch S43 closes during
It is also clear that it closes during clock phase 3 at the same time as 23 and S13. Although the capacitance relationship is perfectly maintained for a lossless circuit, the capacitance values are shown with a factor of 2 for clarity.

The actual operation and advantages obtained by such a circuit will be explained later.

For the sake of clarity, the actual operation of the partial circuits used in the circuit will now be explained with reference to FIGS. 7 and 8.

As mentioned above, SC filters (switched capacitor filters) handle analog sample systems that process a series of samples, so after applying bilinear transformation, the two-terminal function or transfer function is decomposed into realizable rational numbers. The equivalent current and voltage must be defined. Since the signal is generally input to or taken from the SC filter in the form of a voltage value, it is particularly advantageous to avoid the need for synthesis circuits at the signal input or output and to choose voltage definitions of practical relevance. is important.

The voltage across the capacitors of the switch capacitor network changes from the previous value ub(nT) = Ub·e ^pnT to the later value ua(nT) = U _a ·e ^pnT of the charge group controlled by the clock timer scheme. Fluctuations during flow.
Define U(z)=Ua(z) (1) as the equivalent voltage for calculation at this time. This not only allows the simplest signal input or output, but also facilitates the interconnection of the network elements to be dealt with below to form an SC filter.

According to the definition of electric charge, q(nT)=〓〓〓〓i(t)dt (2) Therefore, the definition of current is as follows.

I(z)=2/T・z/z+1・Q(z) (3) The definitions of these charges and currents are: S=Σ+jΩ=2/Tφ φ=z−1/z+1=tanhbT/2=E+jφ (4 ) The new frequency variable p=δ+jω has been chosen to give the simplest implementation for the most frequently encountered and coil-saving two-terminal element, namely the capacitor.

Next, apply voltage and current determinations (1) and (3) to obtain 2
Realize terminal circuits, volumes, resistances and inductances, and explore parasitic capacitances or non-ideal operational amplifier effects.

As already mentioned, definitions (1) and (3) for the capacitance shown in Figure 7 mean that the impedance Z(s) = 1/
A particularly simple implementation of sC is given.

Q(z)=C(U _a −U _b ) holds true.

Since U _a = U, U _b = Uz ^-1 , Q(z) = CU(z) (1-z ^-1 ) and I(z) = 2C/T・z−1/z+1・U(z)・( 5) Become.

The indicator "a" (rear) here represents the after state of the switch, and correspondingly the indicator "b" (front) represents the previous state of the switch.

Therefore, it becomes as follows.

Z=U/I=T/2C z+1/z-1=〓=〓・(6) R _c is the transient resistance of the capacitance.

The ground capacitance C' associated with the floating capacitor C is already taken into account in the design of a time-invariant reference filter.

A circuit simulating a resistance is shown in FIG. According to the document mentioned at the outset, a constant real impedance is realized by a capacitor whose polarity is periodically reversed. This is done by a switch in capacitor C that is closed during clock phase 1 or 2.

If the earth capacity is not taken into account, the following equation holds true.

U(z) = U ₁ (z) - U ₂ (z) and I(z) = I _1(z) = -I ₂ (z), and U _b = -U _a z ^-1 . Therefore, Then, Q(z)=C(U _a −U _b )=CU(1+z ⁻¹ ) Furthermore, it becomes as follows.

I(z)=2C/T・U(z) Z=U/I=T/2C=R _c・ (7) Here, the ground capacitance associated with the floating MOS capacitor can be arranged symmetrically as shown in Figure 2. This is especially important. If this parasitic capacitance is not symmetrically partitioned, the network topology simply repeats every 2T seconds or more. On the other hand, this results in an additional image frequency (n+1)/2Ω±ω, which therefore places strict demands on the time-invariant pre- or post-filter. In the following we therefore always assume a symmetrically divided ground capacitance of a MOS capacitor whose polarity is reversed periodically.

Under these assumptions, the following equation is given for the device of FIG.

From this admittance matrix an equivalent circuit is derived, which consists of a bridge filter with half a transient resistance (R/2) in the series shunt and a capacitance C'/2 in the diagonal shunt. As is known, the equivalent circuit diagram of this bridge filter and the bridged T-type filter are equivalent, and this bridged T-type filter can be similarly applied to the circuit concept.

This non-minimum phase network characteristic caused by parasitic ground capacitance does not actually affect the SC filter since it only occurs at the termination.

Unlike the literature mentioned at the beginning, in order to realize inductive impedance, we use the above-mentioned two-terminal circuit realization method and the RC which has the drawbacks mentioned at the beginning.
It does not simulate active realization. Rather, it seeks a direct realization of the differential equations obtained for the two-terminal circuit "inductance" (see FIGS. 1 to 6).

Z=〓〓=2/T・z−1/z+1・L=z−1/z
+1·T/2C(9) From definitions (1)-(3), the following equation is obtained from equation (9).

U(z)・C=T/2・z−1/z+1・2/T・z
/z+1 ・Q(z)=1−z ⁻¹ /(1+z ⁻¹ ) ²・Q(
z) Furthermore, the following formula holds true.

Q (z) = C (U _a (z) - U _b (z)) = CU (z) (1 - U _b /U _a (z)) (10) Compare equations (9) and (10) Then, the following formula is obtained.

U _b /U _a (z) = -z ^-2 +3z ^-1 /1-z ^-1
(11) In other words, it is desirable to have a circuit that realizes the transfer function (11), receives the input signal U _a from the capacitor that constitutes the inductance, and branches the output voltage U _b from there before the next group of charges arrives. . (11)
Because the denominator polynomial N(z)=1−Z ⁻¹ in Eq.
It is clear that the device implementing this transfer function must have integral properties.

Different weighting factors for lead and lag can be realized by charge group distribution in a correspondingly selected ratio of C.

Transfer function achieved when configuring the inductance
From (11) it is clear that the voltage U _b at the operational amplifier output terminal can exceed the signal voltage U=U _a at the inductance.

The possibility of reducing U _b by 1/2 is shown in FIG. 6, which has already been largely explained.

The ground capacitance that occurs in the circuit of FIG. 6 can be fully accounted for. When lowering the level control to achieve a floating coil, the effect of ground capacitance is not directly taken into account. However, the additional amplifier provides relief for two adjacent floating coils at the same time.

The voltage U _b at the output terminal of the operational amplifier follows the signal voltage similarly to the coil voltage U _a . That is, the steps of the staircase progression become smaller as the signal frequency is lower with respect to the clock frequency. Capacity C
(FIG. 4) may have to be charged and discharged considerably depending on the case, but there is no need for the entire operational amplifier to oscillate more than all stages during these charging and discharging processes.

FIGS. 9 and 10 show a third-order bypass circuit as an example of a filter circuit, which includes capacitors C ₁ and C ₂ in a series shunt and a parallel shunt therebetween. It includes a series resonant circuit consisting of a capacitor C ₂ and a coil L. Additionally capacitors C ₁ to C ₃ as switch capacitors
There are associated ground capacitances which are connected in parallel to the series resonant circuit C ₂ ,L as a total capacitance C′ ₁ +C′ ₂ +C′ ₃ . A voltage source U _p with an internal resistance Ro and a load resistance R producing an output voltage U _L
L is similarly shown in FIGS. 9 and 10, and the earth capacitance C′ _p or C′ _L of these resistors is the resistance R _p
Or via a transformer connected in parallel to R _L and having a transformation ratio of 1:1. By comparing FIG. 10 with FIGS. 1, 7, and 8, it is readily apparent that the circuit of FIG. 9 includes the circuit elements described in the previous figures.
The coil according to FIG. 1 is thus completely simulated between terminals 17 and 21. Among the circuits in FIG. 10, the capacitive element C ₁ belonging to the high-pass circuit,
C ₂ and C ₃ are the capacitors at the same circuit position even in the circuit realized in Figure 9.
They are directly simulated as C ₁ , C ₂ , and C ₃ . Similarly, the effective resistance according to FIG. 8 is simulated by a capacitor C p whose polarity is periodically reversed with _respect to a resistor R _p and by a capacitor C _L whose polarity is periodically reversed with respect to a load resistance R _L. has been done. Correspondingly to FIG. 7, the clock phases are designated 1 and 2 for the switches to be reversed in the capacitors C _p and C _L , and for the sake of distinction the switches S11 and S21 are shown in the capacitor C _p . Alternatively, only S21 and S22 are shown. Correspondingly capacitor C
The switch in _L is S31 and S41 or S
32 and S42.

The realization of another filter circuit is likewise carried out in a similar application of this embodiment, in particular by the application of a floating coil according to FIG.
It can be applied when simulating a low-pass filter, band-pass filter, or band-stop filter.

An advantageous variant embodiment is shown in FIG. 11 for a low-pass circuit, and only part of such a low-pass circuit is shown with dashed lines on the circuit input and circuit output sides. A circuit is then simulated which is to simulate two parallel resonant circuits with a capacitor C _c arranged in the parallel shunt and arranged in the series shunt, which can also be seen in the electrical equivalent circuit diagram indicated by the dashed line. As you can see right away. The floating inductance according to FIG. 5 is then connected to the capacitors designated C _a and C _b in the series shunt, so that reference is made directly to the explanation given in this regard. For clarity, the individual switches are now marked by the clock phase, which is always marked. Voltage amplifier 2 with an additional amplification factor of +1 in the circuit of Fig. 11
6 is used. This voltage amplifier is connected via a switch S6', which closes at clock phase 6' (see FIG. 2), to a circuit point 25, to which a capacitor 15 is also connected, i.e.
A capacitor with the largest capacitance value is connected for the inductance simulation according to the diagram. This device eliminates the parasitic leakage admittance that occurs in floating inductances.

A new clock phase 6' inserted between clock phases 6 and 3 is required. The non-grounding of the non-inverting input terminal of the additional operational amplifier is not a significant disadvantage here. This is because this input terminal cannot be switched and the input capacitance can be fully taken into account.

In the circuit of FIG. 12, the signal reflected from the SC filter is used as the output signal of the circuit. Again, the illustrated circuit includes a signal generator U _p
is shown, and this signal generator is connected to the other signals via switch S53, which is closed during clock phase 3.
Connected to SC filter circuit. A periodically polarized capacitor (see FIG. 9), which simulates the signal generator internal resistance C _p , is then connected to a further circuit point 30 . Considering that a switch S46 is connected to the output terminal 31 from this circuit point, and that the switch S53 is closed during clock phase 3 and the switch S46 is closed during clock phase 6, the terminal 31 and the reference potential 18 The signal _Q・U _p ( _Q
= reflection coefficient) can be extracted. Such a circuit therefore acts as a strict branching circuit.

In general, therefore, the reflected signal can be tapped off from the input/output terminals of the SC filter at a predetermined time without significant additional costs. In this case, it is assumed that there is a capacitive path from each port of the filter that cannot be switched to ground. This condition is met in almost all cases already considering the ground capacity.

In addition, due to the configuration of the load resistor similar to that of the second signal source, the SC filter is used simultaneously in both propagation directions. In any case, the crosstalk loss between both transmission directions is the same as the return loss of the SC filter.

According to FIG. 13, the inductance L has a charge Q
_L (z) It is clear that a charge Q _c (z) is received on the capacitor C, so the total charge Q (z)
is transferred to the floating parallel resonant circuit. The resulting voltage drop is designated U(z). Therefore, the constant C _L
=T ² /4L can be directly determined from the inductance L to be realized for the parallel resonant circuit and the clock period T inherent in the system. 1 to 12 individually show further design values and also the application of the so-called z-transform, which is often used in the calculation of sample value systems.

As previously discussed, a circuit is shown in FIG. 4, most of which is the same as the fourteenth circuit. Therefore, in the description of FIG. 14, reference can be made completely to the description of FIGS. 1 to 13, the actual operation and the clocking scheme required for the switch control being also indicated. Elements of the same operation are designated with the same reference numerals, and the clock phases for closing the individual switches are also shown directly at the individual switches in FIG. Therefore, corresponding to FIG. 4, it can be seen that the following circuit elements in FIG. 14 are the same.

An input voltage U _(z) is applied between input terminals 17 and 21, and after these terminals a switch S23 is applied.
or S33 follows and these switches are closed during clock phase 3. Furthermore, a circuit point 20 is shown behind which a capacitor 15 is connected in the direction of circuit point 25. A switch S14, which closes during clock phase 4, is connected from circuit point 20 to another circuit point 19, and a capacitor 16 is connected from circuit point 19 to reference potential 18.
The integrating element likewise consists of an operational amplifier 10, the inverting input terminal of which is indicated by 11, the non-inverting input terminal by 12, and a capacitor 14 is connected to an output terminal 13. On the other hand, this capacitor is connected to the inverting input terminal 11. Switches S16, S15 and S13 are shown in another branch circuit, which are likewise closed during clock phases 6, 5 or 3.

The circuit of FIG. 14 differs from that of FIG. 4 in the following points.

Switch S15 is connected to circuit point 25 instead of circuit point 20. Additionally, switch S46 in the lower series shunt closes during clock phases 4 and 6. Additionally, a switch S25 is added, which is closed during clock phase 5 and connects circuit point 20 to reference potential 18 during this clock phase.

According to the basic research of the present invention, electric charges Q _(z) =Q _L (z) + Q _C (z) are supplied to the input terminals 17 and 21 as necessary according to the equivalent circuit diagram of FIG. I understood. That is, if the following relationship is maintained, a lossless parallel circuit is simulated.

C _p = C + C _L , C ₁ = C _p ² /3C _L -C, C ₂ = C _p ² /4C _L , C _L = T ² /4 _L. To clarify the difference from the design shown in Fig. 4, In Fig. 14, capacitor 15 or 16
The capacitance value of or 14 is indicated by C _p or C ₁ or C ₂ .

According to the design described above, a resonant circuit is realized with a resonant frequency lower than F/6, in which case switch S25 is not required, and the circuit is otherwise constructed as in FIG. Operate.

A resonant circuit with a resonant frequency higher than F/6 is obtained by a switch S25 which is closed on clock phase 5, so that the polarity reversal of capacitor 15 takes place during clock phase 5, so that in this case the circuit is It is constructed as shown and operates according to the clock scheme indicated therefor.

The circuit described above thus has the following advantages:
In other words, an active circuit with the characteristics of a floating parallel resonant circuit can actually be realized without additional circuit costs.
The parallel resonant frequency of this circuit is lower or higher than 1/6 of the system-specific clock frequency F.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of an inductance with one end grounded, and FIG. 2 shows a clock diagram for operating individual switches in clock phases 1 to 6' with a clock period T; is also valid for the following circuits; FIG. 3 is an electrical equivalent circuit diagram of the circuit of FIG. 1 that takes into account the complex frequency S and the well-known Ψ transformation, and FIG.
A circuit diagram realizing a floating inductance, i.e. an inductance not connected to earth potential,
5 is a diagram showing the electrical equivalent circuit for the circuit of FIG. 4, similar to FIG. 3; FIG. 6 is a circuit diagram for reducing the level control of the operational amplifier to realize a grounded inductance; The figure shows an electrical two-terminal circuit diagram in the form of a capacitor C with a ground capacitance C', and Figure 8 shows
An electrical two-terminal circuit diagram simulating an ohmic resistance resulting in an earth capacitance C'/2, FIG.
1 is a circuit diagram for a switched capacitor high-pass filter operating with a clocked internal resistor C _P and a clocked load resistor C _L at _p ;
At that time, an output voltage U _L is generated from the load resistance C _L , and the first
Fig. 0 is an electrical equivalent circuit diagram of the circuit shown in Fig. 9 taking into account ground capacitance, Fig. 11 is a diagram showing the realization of two floating parallel resonant circuits with compensation for parasitic ground capacitance, and Fig. 12 is a diagram of the circuit shown in Fig. 9. Figure 13 is a circuit diagram for extracting a reflected signal that has a transfer characteristic opposite to that of a filter connected in the circuit like a wave circuit, and is realized by an inductance L=T ² /4C _L and a capacitor C. FIG. 14 is another active circuit diagram for realizing the parallel resonant circuit of FIG. 13. 10...Operation amplifier, 17, 21...Input terminal, 1
8...Earth potential, 19, 20, 23, 25, 30
...Circuit point, 26...Voltage amplifier, 31...Output terminal.

Claims (1)

[Scope of Claims] 1. A filter circuit includes a switch, a capacitor, and an amplifier controlled by a predetermined clock phase, and an operational amplifier is provided between the output terminal and the inverting input terminal of the operational amplifier. In an electric filter circuit using at least one pseudo inductance, the inverting input terminal 11 of the operational amplifier 10 has a capacitor connected to the inverting input terminal 11 of the operational amplifier 10 and the non-inverting input terminal is connected to a fixed reference potential, for example ground potential. There is a switch S13 at a first circuit point 19 from which a capacitor 16 is connected from this circuit point to a reference potential 18, and a switch S14 is connected to a first circuit point 19.
A capacitor 15 is connected between the second circuit point 20 and the reference potential 18, and a capacitor 15 is connected between the second circuit point 20 and the operational amplifier 1.
There is a switch S15 between the inverting input terminal 11 of 0 and another switch S16 between the second circuit point 20 and the output terminal 13, and another switch S23 between the second circuit point 20 and the first The switches S13 and S23 are located between the input terminal 17 of the
clock phases 4, 5, which are closed simultaneously during two clock phases 3 and which do not overlap in time;
6, the switches S14, S15, and S16 close in sequence (Figs. 1, 2, and 3).
Figure), an electrical filter circuit using at least one pseudo-inductance, including a controlled switch, a capacitor and an amplifier. 2 The capacitance value of the capacitor 14 located between the output terminal 13 and the inverting input terminal 11 of the operational amplifier 10 is 1/4 (C /4), and on the other hand, the capacitor 16 between the first circuit point 19 and the reference potential 18 has a capacitance value of 1/3 of this value C.
(C/3) (Fig. 1, Fig. 2, Fig. 3).
Figure) A filter circuit according to claim 1. 3. The filter circuit includes a switch controlled by a predetermined clock phase, a capacitor and an amplifier, and an operational amplifier is provided, and a capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier. In an electric filter circuit using at least one pseudo inductance, the non-inverting input terminal is connected to a fixed reference potential, for example earth potential, from the inverting input terminal 11 of the operational amplifier 10 to the first circuit point. A switch S13 is located at 19, and a capacitor 16 is connected from this circuit point to the reference potential 18, and a switch S14 is located between the first circuit point 19 and the second circuit point 20, and the second There is a switch S15 between the circuit point 20 and the inverting input terminal 11 of the operational amplifier 10, and the second circuit point 20
and the output terminal 13, and another switch S23 between the second circuit point 20 and the first input terminal 17, and the switches S13 and S23 are connected to one clock phase. Switches S14 and S1 are closed simultaneously during the period 3 and the subsequent clock phases 4, 5, and 6 do not overlap in time.
5 and S16 are closed in sequence, and the capacitor 15 from the second circuit point 20 is connected on the one hand to the second input terminal 21 via the switch S33,
On the other hand, it is connected to the reference potential 18 via a switch S456, and is characterized in that both switches S33 and S456 correspondingly close in sequence during clock phases 3 or 4, 5 and 6. 2, 4 and 5), an electrical filter circuit including a controlled switch, a capacitor and an amplifier and using at least one pseudo-inductance. 4. The filter circuit includes a switch controlled by a predetermined clock phase, a capacitor and an amplifier, and an operational amplifier is provided, and a capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier. In an electric filter circuit using at least one pseudo inductance, the non-inverting input terminal is connected to a fixed reference potential, for example earth potential, from the inverting input terminal 11 of the operational amplifier 10 to the first circuit point. Switch S13 is connected to 19,
A capacitor 16 is connected from this circuit point to the reference potential 18, and a switch S14 is connected between the first circuit point 19 and the second circuit point 20. A capacitor 15 is connected to the potential 18, a switch S15 is connected from the second circuit point 20 to the inverting input terminal 11 of the operational amplifier 10, and a switch S15 is connected between the second circuit point 20 and the output terminal 13. Another switch S1
6 is connected, and from the second circuit point 20 to the third
A switch S26 is connected to the circuit point 23 of , a switch S26 is connected to the third circuit point which leads to the first input terminal 17 on the one hand, and an additional capacitor 15 is connected to the fourth circuit point 22 on the other hand. ' are connected, and switches S13 and S23 are closed simultaneously during one clock phase 3, and switches S14, S15, S1 are closed simultaneously during one clock phase 3, and switches S14, S15, S1 are closed simultaneously during one clock phase 3 and
6 are closed in sequence, a switch S43 is connected from the fourth circuit point 22 to the second connection point 20, and on the other hand, a switch S36 is connected between the fourth circuit point 22 and the second input terminal 21. and additional switches S43, S26 and S36,
An electrical filter using at least one pseudo-inductance, including a controlled switch, a capacitor and an amplifier, correspondingly being closed during clock phases 3 or 6 (FIGS. 2, 6, 7). circuit. 5 An additional capacitor 15' connects switch S4
5. The filter circuit according to claim 4, having the same capacitance value as the capacitor 15 connected through the capacitor 3 (FIGS. 2, 6, and 7). 6. The filter circuit includes a switch controlled by a predetermined clock phase, a capacitor and an amplifier, and an operational amplifier is provided, and the capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier. In an electric filter circuit using at least one pseudo inductance, the non-inverting input terminal is connected to a fixed reference potential, for example earth potential, from the inverting input terminal 11 of the operational amplifier 10 to the first circuit point. 19 switches S13 are connected,
A capacitor 16 is connected from this circuit point to the reference potential 18, and a switch S14 is connected between the first circuit point 19 and the second circuit point 20. A capacitor 15 is connected to the reference potential 18, and the inverting input terminal 11 of the operational amplifier 10 is connected from the second circuit point 20.
A switch S15 is connected to the switch S15, and another switch S15 is connected between the second circuit point 20 and the output terminal 13.
16 is connected and another switch S23
are connected between the second circuit point 20 and the terminal 17, and switches S13 and S23 are closed simultaneously during one clock phase 3 and during subsequent non-overlapping clock phases 4, 5, 6. Switches S14, S15, and S16 are closed in sequence, and the capacitors of the branch circuit are simulated as capacitors C ₁ , C ₂ , C ₃ ) to realize a general branch circuit, and an external switch is closed to simulate the resistance. In the circuit, another switch S1
1, S21, S31, S41 or S12, S2
2, S32, S42 are connected to capacitors Co, C _L whose polarity is periodically reversed, and switches S11, S21, S31, S41 are switched on during clock phase 1, while switches S21, S22, S
32, S42 is closed during clock phase 2 (FIGS. 2, 9 and 10), an electrical filter circuit using at least one pseudo-inductance, including a controlled switch, a capacitor and an amplifier. . 7. The filter circuit includes a switch controlled by a predetermined clock phase, a capacitor and an amplifier, and an operational amplifier is provided, and the capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier. In an electric filter circuit using at least one pseudo inductance, the non-inverting input terminal is connected to a fixed reference potential, for example earth potential, from the inverting input terminal 11 of the operational amplifier 10 to the first circuit point. Switch S13 is connected to 19,
A capacitor 16 is connected from this circuit point to the reference potential 18, and a switch S14 is connected between the first circuit point 19 and the second circuit point 20. from operational amplifier 1
A switch S15 is connected to the inverting input terminal 11 of 0, and the second circuit point 20 and the output terminal 13
Another switch S16 is connected between
and another switch S23 is connected between the second circuit point 20 and the first input terminal 17, and switches S13 and S23 are closed simultaneously during one clock phase 3 and for the following time. Switch S1 to clock phases 4, 5, and 6 that do not overlap.
4, S15 and S16 are closed in sequence, and the capacitor 15 from the second circuit point 20 is connected on the one hand to the second input terminal 21 via the switch S33 and on the other hand to the reference potential 18 via the switch S456. and both switches S33 and S456 are correspondingly closed in sequence during clock phases 3, 4, 5 and 6 and are connected to the circuit point 25 from the second input terminal 21 via the switch S6'. A voltage amplifier 26 with an amplification factor (+1) is connected to this circuit point, and a capacitor 15 is also connected to this circuit point, and this capacitor has a large capacitance value in order to simulate inductance. is characterized by being closed during clock phase 6' which occurs adjacently between clock phases 6 and 3 (FIGS. 2 and 11).
Figure), an electrical filter circuit using at least one pseudo-inductance, including a controlled switch, a capacitor and an amplifier. 8. The filter circuit includes a switch controlled by a predetermined clock phase, a capacitor and an amplifier, and an operational amplifier is provided, and the capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier. In an electric filter circuit using at least one pseudo inductance, the non-inverting input terminal is connected to a fixed reference potential, for example earth potential, from the inverting input terminal 11 of the operational amplifier 10 to the first circuit point. Switch S13 is connected to 19,
A capacitor 16 is connected from this circuit point to the reference potential 18, and a switch S14 is connected between the first circuit point 19 and the second circuit point 20. A capacitor 15 is connected to the potential 18, a switch S15 is connected from the second circuit point 20 to the inverting input terminal 11 of the operational amplifier 10, and a switch S15 is connected between the second circuit point 20 and the output terminal 13. Another switch S1
6 is connected, and another switch S23 is connected between the second circuit point 20 and the first input terminal 17, and the switches S13 and S23 are
a clock phase 4 which is closed simultaneously during one clock phase 3 and which does not overlap in time;
Switches S14, S15, and S16 are closed in sequence at 5 and 6, and a capacitor Co whose polarity is periodically reversed to simulate the internal resistance of the signal generator is closed at the 6th switch.
From this circuit point, a switch S53 is connected to the signal voltage source Uo on one side, a switch S46 is connected to the output terminal 31 on the other side, and a switch S46 is connected to the output terminal 31 on the other side.
Electrical filter circuit using at least one pseudo-inductance, including a controlled switch, a capacitor and an amplifier, characterized in that 53 and S46 close to clock phase 3 or 6, respectively. 9. The filter circuit includes a switch controlled by a predetermined clock phase, a capacitor and an amplifier, and an operational amplifier is provided, and a capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier. and the non-inverting input terminal is connected to a fixed reference potential, for example ground potential. In an electric filter circuit using at least one pseudo-inductance, a switch S13 is connected from the inverting input terminal 11 of the operational amplifier 10 to a first circuit point 19,
A capacitor 16 is connected from this circuit point to the reference potential 18, and a switch S14 is connected between the first circuit point 19 and the second circuit point 20, and the second circuit point is connected to the ground potential. A capacitor 15 is connected to 18, and a second circuit point 2
0 and the output terminal 13, another switch S23 is connected between the second circuit point 20 and the first input terminal 17, and the switches S13 and S23 are Switches S14, S15, S16 are closed simultaneously during one clock phase 3, and in sequence during subsequent non-overlapping clock phases 4, 5, 6, and the line coming from switch S15 is connected to a second circuit. Point 2
The polarity of the capacitor Co leading to the reference potential is reversed in such a way that it is connected to another circuit point 25 instead of 0, and the switch S46 connected after this circuit point 25 is connected instead of clock phases 4, 5, 6. is characterized in that it is closed during clock phases 4 and 6, and another switch S25 is connected from the second circuit point 20 to the reference potential 18, which is closed during clock phase 5 (FIG. 13, Figure 14), an electrical filter circuit including a controlled switch, a capacitor and an amplifier and using at least one pseudo-inductance. 10 Capacitor 15,1 provided in the circuit
The capacitance values Co, C ₁ and C ₂ of 6 and 14 are determined by the following equations, C _p = C + C _L , C ₁ = C _p ² /3 C _L - C, C ₂ = C _p ² /4 C _L , C _L =T ² /4L, where C or L represents the reactance value of the parallel resonant circuit to be realized, FIGS. 13 and 14,
A filter circuit according to claim 9.