JPS62117885U - - Google Patents
Info
- Publication number
- JPS62117885U JPS62117885U JP436486U JP436486U JPS62117885U JP S62117885 U JPS62117885 U JP S62117885U JP 436486 U JP436486 U JP 436486U JP 436486 U JP436486 U JP 436486U JP S62117885 U JPS62117885 U JP S62117885U
- Authority
- JP
- Japan
- Prior art keywords
- fixed impedance
- circuit
- adjustment circuit
- impedance element
- input adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Attenuators (AREA)
Description
第1図は実施例の回路図、第2図はプリント基
板のパターンを示す図、第3図はプリント基板を
示す斜視図、第4図は他の実施例を示す回路図で
ある。
10…入力調整回路、R7,R8,R9,R1
0…固定抵抗、20,21…ジヤンパ線。
1 is a circuit diagram of an embodiment, FIG. 2 is a diagram showing a pattern of a printed circuit board, FIG. 3 is a perspective view of a printed circuit board, and FIG. 4 is a circuit diagram of another embodiment. 10...Input adjustment circuit, R 7 , R 8 , R 9 , R 1
0 ... Fixed resistance, 20, 21... Jumper wire.
Claims (1)
回路において、第1、第2の固定インピーダンス
素子による分圧回路と、前記第1、第2の固定イ
ンピーダンス素子の少なくとも一方に並列に接続
される固定インピーダンス素子とスイツチ手段の
直列回路を備えることを特徴とする入力調整回路
。 In an input adjustment circuit that adjusts and outputs the level of an input signal, a voltage divider circuit includes first and second fixed impedance elements, and a fixed impedance element connected in parallel to at least one of the first and second fixed impedance elements. An input adjustment circuit comprising a series circuit of an impedance element and a switch means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP436486U JPS62117885U (en) | 1986-01-16 | 1986-01-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP436486U JPS62117885U (en) | 1986-01-16 | 1986-01-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62117885U true JPS62117885U (en) | 1987-07-27 |
Family
ID=30784963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP436486U Pending JPS62117885U (en) | 1986-01-16 | 1986-01-16 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62117885U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6423177U (en) * | 1987-07-31 | 1989-02-07 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594697B2 (en) * | 1974-11-08 | 1984-01-31 | ヘキスト アクチエンゲゼルシヤフト | Insatsuban no Seizou Sochi |
JPS59165509A (en) * | 1983-03-10 | 1984-09-18 | Seiko Epson Corp | Control circuit of resistance value |
JPS59194578A (en) * | 1983-04-19 | 1984-11-05 | Mitsubishi Electric Corp | Video tape recorder |
-
1986
- 1986-01-16 JP JP436486U patent/JPS62117885U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594697B2 (en) * | 1974-11-08 | 1984-01-31 | ヘキスト アクチエンゲゼルシヤフト | Insatsuban no Seizou Sochi |
JPS59165509A (en) * | 1983-03-10 | 1984-09-18 | Seiko Epson Corp | Control circuit of resistance value |
JPS59194578A (en) * | 1983-04-19 | 1984-11-05 | Mitsubishi Electric Corp | Video tape recorder |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6423177U (en) * | 1987-07-31 | 1989-02-07 |