JPS62114392A - Cipher apparatus - Google Patents

Abstract

PURPOSE:To attain the miniaturization of a cipher apparatus by eliminating an encoded data inputted to a storage circuit from the output of a delay circuit, and multiplexing the output of an encipherment circuit on a vacant time slot. CONSTITUTION:The output terminal of a high efficiency encoding circuit 1 is connected to the input terminal of a delay circuit 2 and a storage circuit 3, and the output terminal of the circuit 3 is connected to the input terminal of an encipherment circuit 4. The output terminal of the circuit 2 and that of the circuit 4 are connected respectively to two input terminals of a multiplexing circuit 5, and the output data of the cipher apparatus is taken out from the output terminal of the circuit 5. At such a time, the circuit 1 performs a high efficient encoding on a TV signal, and outputs the encoded data. The data is written on the storage circuit 3 in a proportion of 1 bit to 10 bits, and the output data is enciphered at the circuit 4. In that case, a delay fitting between the output of the circuit 4 and an unenciphered data is performed at the circuit 2, and an enciphered data at the circuit 4 is eliminated from the output signal of the circuit 2 at the circuit 5, and the output signal of the circuit 4 is multiplexed on the vacant slot.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention receives encoded data output from a high-efficiency encoding circuit that highly efficiently encodes a signal 2 to be transmitted, for example, a television signal, and encodes the encoded data. This relates to an encoder that uses

[Conventional technology]

Additional encryption may be required to protect information in communication systems. LSIs and devices for performing this encryption are generally commercially available, but these cannot be applied to very high-speed data, and currently only have a processing capacity of several Mb/s at most.

By the way, television signals have a very large amount of information, and even when this is highly efficiently encoded and transmitted, it can be transmitted at several tens of Mb/s.
data is generated. Therefore, in order to encrypt the transmission data of a high-efficiency encoding device for television signals, commercially available encryption LSIs and encryption circuits are used. Well, you can't use it.

[Problem that the invention seeks to solve]

To encrypt data at tens of Mb/s, it is possible to design an encryption circuit using high-speed operating elements, or to use multiple commercially available encryption LSIs for parallel processing. . However, since encryption circuits perform complex processing, it is extremely difficult to design a circuit that can process such high-speed data.

Even if one were to design one, it would be expensive, and the encryptor would also be expensive. Furthermore, when performing parallel processing, there is also a drawback that the circuit scale of the encoder increases.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide an inexpensive and compact encryptor.

[Means for solving problems]

According to the present invention, in an encoder that receives encoded data output from a high-efficiency encoding circuit that encodes a signal to be transmitted with high efficiency, a part of the encoded data is stored, and a part of the encoded data is stored. a memory circuit that outputs at a speed slower than the transmission speed; an encryption circuit that encrypts the output of the memory circuit;
a delay circuit that delays the encoded data; and a multiplexing circuit that removes the encoded data input to the storage circuit from the output of the delay circuit and multiplexes the output of the encryption circuit into the vacant time slot. An encoder characterized in that it includes the following is obtained.

〔Example〕

High-efficiency encoding of television signals utilizes the large autocorrelation of image signals to suppress redundancy and perform encoding. Therefore, if encoded data for a certain pixel is transmitted incorrectly, the decoding side will not be able to correctly decode not only that pixel data but also other pixels. For example, in intra-field predictive coding, the current value is predicted from the value of a pixel that has already been coded on the same field, and the error from that value is coded, so if the coded data for a certain pixel is transmitted incorrectly, Encoded data transmitted later cannot be decoded correctly.

However, since the encoding device normally performs a reset on a scanning line basis or field basis, the correct decoding operation returns when a new line or field starts.

If high-efficiency encoding is not performed, even if the transmitted data is kana or erroneous, the image quality will only deteriorate and the content of the image signal will be legible, but if high-efficiency encoding is performed, the encoded data will be
If a mistake is made with a certain degree of probability, the contents of the image signal will become unreadable.

The present invention utilizes such properties of highly efficient encoded data to perform encryption.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an encoder according to an embodiment of the present invention. The output terminal of the high efficiency encoding circuit 1 is connected to the input terminals of a delay circuit 2 and a memory circuit 3.

The output terminal of the storage circuit 3 is connected to the input terminal of the encryption circuit 4. The output end of the delay circuit 2 and the output end of the encryption circuit 4 are respectively connected to two input ends of the multiplexing circuit 5,
The output data of the encoder is output from the output terminal of the multiplexing circuit 5.

A high-efficiency encoding circuit 1 encodes a television signal with high efficiency and outputs the encoded data. This data is written in the memory circuit 3 at a ratio of 1 bit to 10 bits, and the output data is encrypted by the encryption circuit 4. The delay circuit 2 is a circuit for delay matching the output of the encryption circuit 4 and unencrypted data, and the multiplexing circuit 5 removes the data encrypted by the encryption circuit 4 from the output signal of the delay circuit 2. , multiplexes the output signal of the encryption circuit 4 into the vacant time slot.

FIG. 2 shows output data of the multiplexing circuit 5.

Dl and 010 indicate data that has been temporarily stored in the storage circuit 3 and then encrypted in the encryption circuit 4.

F, D2 to D9, and Dl 1 to 12 indicate data that was only delayed by the delay circuit 2 but not encrypted. Note that F is a synchronization bit included in the encoded data for synchronizing two frames when transmitting the encoded data. Which data in the high-efficiency encoded data is encrypted by the encryption circuit 4 is determined by the data written to the storage circuit 3, and this is determined by the position from the synchronization bit. Therefore, on the receiving side, frame synchronization is first performed, and then encrypted data and non-encrypted data are distinguished based on the synchronization bit, and only encrypted data is decrypted.

In the above example, the device comprising the storage circuit 3 has a speed that is 1/10 of the data output from the high-efficiency encoding circuit 1, and the processing speed of the encoding circuit can also be reduced to 1/10. The data encrypted in this way will be reduced to t 10 bits unless the encrypted data cannot be decoded correctly on the receiving side.
The data will be transmitted incorrectly depending on the bit ratio, but
As mentioned above, when high-efficiency encoding is performed, if the encoded data is erroneous with this degree of probability, the image signal will become unreadable on the receiving side, so the purpose of encryption can be achieved.

〔Effect of the invention〕

As explained above, the present invention enables encoded data of a high-efficiency encoding circuit to be processed by an encoding circuit with a slow processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an encoder according to an embodiment of the present invention;
FIG. 2 is a time chart showing an example of output data of the encoder shown in FIG. 1. ■... High efficiency encoding circuit, 2... Delay circuit, 3...
- Storage circuit, 4... Encryption circuit, 5... Multiplexing circuit, F... Synchronization bin), DI, DIO... Encrypted data, D2 to D9. Dll, DI2...Unencrypted data.゛, □1,':, Agent (7783) Patent Attorney Shiho Ikeda 7, -1, J
-ノ

Claims (1)

[Claims] 1. In an encoder that receives encoded data output from a high-efficiency encoding circuit that encodes a signal to be transmitted with high efficiency, a part of the encoded data is stored, and a part of the encoded data is encoded. a memory circuit that outputs data at a speed slower than the data transmission speed; an encryption circuit that encrypts the output of the memory circuit; a delay circuit that delays the encoded data; An encoder comprising: a multiplexing circuit that removes input encoded data and multiplexes the output of the encoder in the vacant time slot.