JPS62114341A - Light reception level monitor circuit - Google Patents

Light reception level monitor circuit

Info

Publication number
JPS62114341A
JPS62114341A JP60254014A JP25401485A JPS62114341A JP S62114341 A JPS62114341 A JP S62114341A JP 60254014 A JP60254014 A JP 60254014A JP 25401485 A JP25401485 A JP 25401485A JP S62114341 A JPS62114341 A JP S62114341A
Authority
JP
Japan
Prior art keywords
voltage
mark rate
monitor
circuit
apd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60254014A
Other languages
Japanese (ja)
Inventor
Kazuo Yamane
一雄 山根
Takashi Tsuda
津田 高至
Kazuhiro Suzuki
和裕 鈴木
Yoshinori Okuma
大隈 義則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60254014A priority Critical patent/JPS62114341A/en
Publication of JPS62114341A publication Critical patent/JPS62114341A/en
Pending legal-status Critical Current

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  • Monitoring And Testing Of Transmission In General (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To prevent the change of a monitor voltage even if the mark rate of an input optical signal is changed, by synthesizing a bias voltage value and a value, which is obtained by dividing a DC current flowing to an APD by the mark rate of the input optical signal, to obtain a monitor level. CONSTITUTION:The output of a data discriminating circuit 10 is processed by an LPF 13 to become a DC voltage VM proportional to the mark rate (m) of the optical pulse signal and is supplied to a divider 14. A voltage VDC proportional to the DC current supplied to an APD 1 from a differential amplifier 11 is supplied to the divider 14 also. A divided value V2=VDC/VM from the divider 14 and the bias voltage V1 of the APD 1 are synthesized by an adder 12 to become a monitor voltage V3. This voltage V3 is not changed even through the mark rate (m) is changed, and the voltage V3 is increased for the rise of the input optical level and is not affected by the mark rate.

Description

【発明の詳細な説明】 〔概要〕 アバランシェフォトダイオード(以下APDと云う)に
流れる直流電流に比例した電圧を入力信号のマーク率に
比例した電圧で割った値と、APDのバイアス電圧とか
ら合成した値をモニタ電圧とする。
[Detailed Description of the Invention] [Summary] Synthesized from a value obtained by dividing a voltage proportional to the DC current flowing through an avalanche photodiode (hereinafter referred to as APD) by a voltage proportional to the mark rate of the input signal and the bias voltage of the APD. The value obtained is the monitor voltage.

〔産業上の利用分野〕[Industrial application field]

本発明は光通信装置に係り、特に光受信レベルモニタ回
路に関するものである。
The present invention relates to an optical communication device, and more particularly to an optical reception level monitor circuit.

光通信の受信装置に於いては送信側から送られて来る光
信号レベルを常時監視する回路が使用されている。此の
様な回路は光受信レベルモニタ回路と云われているが、
従来の光受信レベルモニタ回路は入力光信号のマーク率
が変化した場合、同一のピーク値に対し異なったモニタ
電圧となると云う欠点があり、此の改善が望まれていた
A receiving device for optical communication uses a circuit that constantly monitors the level of an optical signal sent from the transmitting side. A circuit like this is called an optical reception level monitor circuit,
Conventional optical reception level monitor circuits have a drawback in that when the mark rate of an input optical signal changes, different monitor voltages are obtained for the same peak value, and an improvement has been desired.

〔従来の技術〕[Conventional technology]

光受信レベルモニタ回路には従来から種々の方法があり
、例えばAPDのバイアス電圧、電気増幅器のAGC電
圧の両者を合成して広いモニタ範囲を実現している。
Conventionally, there are various methods for optical reception level monitoring circuits. For example, a wide monitoring range is achieved by combining both the bias voltage of an APD and the AGC voltage of an electric amplifier.

第3図は従来の光受信回路と光受信レベルモニタ回路の
一例を示す図である。
FIG. 3 is a diagram showing an example of a conventional optical receiving circuit and an optical receiving level monitor circuit.

第4図は従来の光受信レベルモニタ回路の動作特性の説
明図である。
FIG. 4 is an explanatory diagram of the operating characteristics of a conventional optical reception level monitor circuit.

図中、1はAPD、2は抵抗、3はコンデンサ、4はプ
リアンプ、5ばAGCアンプ、6はAGC制御回路、7
はDC−DC変換器、8は等化器(EQL) 、9はタ
イミング抽出回路、10はデータ識別回路(DEC) 
、11は差動アンプ、12は加算器である。尚以下企図
を通じ同一記号は同一対象物を表す。
In the figure, 1 is an APD, 2 is a resistor, 3 is a capacitor, 4 is a preamplifier, 5 is an AGC amplifier, 6 is an AGC control circuit, and 7 is a
is a DC-DC converter, 8 is an equalizer (EQL), 9 is a timing extraction circuit, and 10 is a data identification circuit (DEC)
, 11 is a differential amplifier, and 12 is an adder. The same symbols represent the same objects throughout the following discussion.

光信号はAPDIに入り、電気信号に変換されてコンデ
ンサ3により直流成分が除去されてパルス成分のみがプ
リアンプ4で増幅される。
The optical signal enters the APDI, is converted into an electrical signal, the DC component is removed by the capacitor 3, and only the pulse component is amplified by the preamplifier 4.

次にAGCアンプ5により増幅され、此の出力はAGC
制御回路6、EQL8、及びタイミング抽出回路9に入
る。
Next, it is amplified by AGC amplifier 5, and this output is AGC
It enters the control circuit 6, EQL 8, and timing extraction circuit 9.

AGC制御回路6の出力はAGCアンプ5の出力レベル
が一定となる様にAGCアンプ5の利得を制御する。同
時にAGC制御回路6の別の出力ばDC−DC変換器7
に入力され、DC−DC変換器7出力は抵抗2を介して
APD 1に直流電流を供給する。此の回路は入力光信
号が低レベルの場合出力の直流電圧を変化させてAPD
Iの増倍率を大きくしてAGCアンプ5の出力レヘルが
一定となる様に制御する。
The output of the AGC control circuit 6 controls the gain of the AGC amplifier 5 so that the output level of the AGC amplifier 5 is constant. At the same time, another output of the AGC control circuit 6 is a DC-DC converter 7.
The output of the DC-DC converter 7 supplies direct current to the APD 1 via the resistor 2. This circuit changes the output DC voltage when the input optical signal is low level and converts it into an APD.
The multiplication factor of I is increased to control the output level of the AGC amplifier 5 to be constant.

又AGCアンプ5の出力ばEQL8で波形等化され、タ
イミング抽出回路9でタイミングパルスが抽出される。
Further, the output of the AGC amplifier 5 is waveform-equalized by an EQL8, and a timing pulse is extracted by a timing extraction circuit 9.

此の波形等化された信号とタイミングパルスはデータ識
別回路(DEC)10に送られ、此処でデータが識別さ
れる。
These waveform-equalized signals and timing pulses are sent to a data identification circuit (DEC) 10, where the data is identified.

上記光受信回路の動作をモニタするために普通差動アン
プ11と加算器12からなるモニタ回路が利用される。
A monitor circuit consisting of a differential amplifier 11 and an adder 12 is usually used to monitor the operation of the optical receiver circuit.

此のモニタ回路に於いてば、差動アンプ11によりAP
Dlに流れる直流電流に比例した電圧■。。
In this monitor circuit, the AP
A voltage proportional to the direct current flowing through Dl. .

を求め、次に加算器12により電圧VDCとAPD 1
のバイアス電圧■1を合成し、此の合成電圧をモニタす
る方法を採っていた。
Then, the adder 12 calculates the voltage VDC and APD 1
A method was adopted in which the bias voltages (1) were synthesized and this synthesized voltage was monitored.

此の方法はダイナミックレンジが広いことと、AGCル
ープに悪影響を与えないこと等の利点があり、広く使用
されている回路である。
This method has advantages such as a wide dynamic range and no adverse effects on the AGC loop, and is a widely used circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

然しなから先入カイ8号のマーク率が変化した場合、下
記の様な欠点がある。
However, if the mark rate of the first entry Kai No. 8 changes, there will be the following drawbacks.

光入力信号のマーク率が変化した場合差動アンプ11の
出力レベル、即ら電圧VOCは変化する。
When the mark rate of the optical input signal changes, the output level of the differential amplifier 11, that is, the voltage VOC changes.

即ら、光入力信号のマーク率が変化すると抵抗2を介し
て八PD1に流れる電流値が変化する。
That is, when the mark rate of the optical input signal changes, the value of the current flowing through the resistor 2 to the eight PDs 1 changes.

第4図に示す様に成る光レベルXの時、光入力信号のマ
ーク率mが増加すると電圧VDCも増加し、マーク率m
が減少すると電圧VIllcも減少する。
At the light level X as shown in FIG. 4, as the mark rate m of the optical input signal increases, the voltage VDC also increases, and the mark rate m
When the voltage VIllc decreases, the voltage VIllc also decreases.

此の為合成電圧(モニタ電圧)も増減するが、AGCア
ンプ5の自動利得制御動作によりAGCアンプ5の出力
レベルは変化しない。
For this reason, the composite voltage (monitor voltage) also increases or decreases, but the output level of the AGC amplifier 5 does not change due to the automatic gain control operation of the AGC amplifier 5.

此の様にマーク率が変化すると従来のモニタ方式では光
入力信号が変化したと表示するが、実際にはAGCアン
プ5の出力レベルは変化していないと云う欠点があった
When the mark rate changes in this way, the conventional monitor system displays that the optical input signal has changed, but there is a drawback in that the output level of the AGC amplifier 5 does not actually change.

本発明は入力光信号のマーク率が変化してもモニタ電圧
が変わらない光受信レベルモニタ回路を提供することで
ある。
An object of the present invention is to provide an optical reception level monitor circuit in which a monitor voltage does not change even if the mark rate of an input optical signal changes.

〔問題点を解決するための手段〕[Means for solving problems]

問題点を解決するための手段は、アバランシ!。 Avalanche is the way to solve problems! .

フォトダイオードの増倍率の制御と電気的AGCアンプ
の増幅度の匍制御によりデータ識別回路の出力振幅を一
定化する光受信回路に於いて、アバランシェフォトダイ
オードのバイアス電圧と、アバランシェフォトダイオー
ドに流れる直流電流を入力光信号のマーク率で除算した
値とを合成してモニタレベルとすることにより解決され
る。
In an optical receiving circuit that stabilizes the output amplitude of the data identification circuit by controlling the multiplication factor of the photodiode and the amplification degree of the electric AGC amplifier, the bias voltage of the avalanche photodiode and the direct current flowing through the avalanche photodiode are controlled. This problem can be solved by combining the current and the value obtained by dividing the mark rate of the input optical signal to obtain a monitor level.

〔作用〕 本発明に依る光受信レベルモニタ回路はマーク率が変化
した場合、此れに対応してアバランシェフォトダイオー
ドに流れる直流電流を補正した上で合成してモニタ電圧
とするため、マーク率が変化してもモニタ電圧は変わら
ないと云う効果が生する。
[Function] When the mark rate changes, the optical reception level monitor circuit according to the present invention corrects the direct current flowing through the avalanche photodiode and synthesizes it to obtain a monitor voltage, so that the mark rate changes. The effect is that the monitor voltage does not change even if the voltage changes.

〔実施例〕〔Example〕

第1図は本発明に依る光受信レベルモニタ回路の一実施
例を示す図である。
FIG. 1 is a diagram showing an embodiment of an optical reception level monitor circuit according to the present invention.

第2図は本発明に依る光受信レベルモニタ回路の動作特
性図ある。
FIG. 2 is a diagram showing the operating characteristics of the optical reception level monitor circuit according to the present invention.

図中、13はローパスフィルタ、14は除算器である。In the figure, 13 is a low-pass filter, and 14 is a divider.

以下図に従って本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

本発明ではローパスフィルタ13をデータ識別回itO
の出力に接続して、此のローパスフィルタ13により受
信信号(パルス信号)に含まれる直流分を取り出す。此
の直流分の電圧値V、4はパルス信号のマーク率mに比
例した値である。
In the present invention, the low-pass filter 13 is
The low-pass filter 13 extracts the DC component contained in the received signal (pulse signal). This DC component voltage value V, 4 is a value proportional to the mark rate m of the pulse signal.

従って従来方式で説明した差動アンプ11の出力電圧v
llcとマーク率mに比例した電圧VMを除算器14に
入力してvnc÷■oを求める。
Therefore, the output voltage v of the differential amplifier 11 explained in the conventional method
llc and the voltage VM proportional to the mark rate m are input to the divider 14 to obtain vnc÷o.

今■。、÷V、=V、と置くと、値v2はマーク率mに
よりAPDIに流れる電流を補正した電圧値となる。
Now ■. , ÷V, =V, the value v2 becomes a voltage value obtained by correcting the current flowing through the APDI according to the mark rate m.

従って以下は従来方式と同じく加算器12により補正さ
れた電圧値V2とAPD 1のバイアス電圧■1を合成
してモニタ電圧■3とすれば、此のモニタ電圧V3はマ
ーク率が変化しても変化することはない。
Therefore, as in the conventional method, if the voltage value V2 corrected by the adder 12 and the bias voltage ■1 of APD 1 are combined to obtain the monitor voltage ■3, this monitor voltage V3 will be the same even if the mark rate changes. It never changes.

従って第2図に示す様に入力光レヘルが増加するとモニ
タ電圧■3は増加し、マーク率mの影習を受けることは
なくなる。
Therefore, as shown in FIG. 2, when the input light level increases, the monitor voltage (3) increases and is no longer affected by the mark rate m.

向上記説明ではローパスフィルタ13をデータ識別回路
10の出力に接続したが、第1図に点線で未す様にEQ
L8の出力、又はAGCアンプ5の出力に接続しても同
様な結果が得られる。
In the explanation above, the low-pass filter 13 was connected to the output of the data identification circuit 10, but the EQ is connected as indicated by the dotted line in Figure 1.
Similar results can be obtained by connecting to the output of L8 or the output of AGC amplifier 5.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に本発明によれば、入力光信号の
マーク率が変化してもモニタ電圧は影響を受けないと云
う大きい効果がある。
As described above in detail, the present invention has the great effect that the monitor voltage is not affected even if the mark rate of the input optical signal changes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に依る光受信レベルモニタ回路の一実施
例を示す図である。 第2図は本発明に依る先受イδレヘルモニタ回路の動作
特性図ある。 第3図は従来の光受信回路と光受信レベルモニタ回路の
一例を示す図である。 第4図は従来の光受信レベルモニタ回路の動作特性の説
明図である。 図中、1はAPD、2は抵抗、3はコンデンサ、4はプ
リアンプ、5はAGCアンプ、6はAGC制御回路、7
ばDC−DC変換器、8は等他罪(EQL) 、9ばタ
1°ミング抽出回路、10はデータ識別回路(DEC)
 、11は差動アンプ、12は加算器、13はローパス
フィルタ、14ば除算器である。 育°f12 第 Z  図
FIG. 1 is a diagram showing an embodiment of an optical reception level monitor circuit according to the present invention. FIG. 2 is a diagram showing the operating characteristics of the pre-receiving δ level monitor circuit according to the present invention. FIG. 3 is a diagram showing an example of a conventional optical receiving circuit and an optical receiving level monitor circuit. FIG. 4 is an explanatory diagram of the operating characteristics of a conventional optical reception level monitor circuit. In the figure, 1 is an APD, 2 is a resistor, 3 is a capacitor, 4 is a preamplifier, 5 is an AGC amplifier, 6 is an AGC control circuit, and 7
8 is a DC-DC converter, 8 is an equal liability (EQL), 9 is a 1° timing extraction circuit, and 10 is a data identification circuit (DEC).
, 11 is a differential amplifier, 12 is an adder, 13 is a low-pass filter, and 14 is a divider. Iku°f12 Figure Z

Claims (1)

【特許請求の範囲】 アバランシェフォトダイオード(1)の増倍率の制御と
電気的AGCアンプ(4)の増幅度の制御によりデータ
識別回路(9)の出力振幅を一定化する光受信回路に於
いて、 該アバランシェフォトダイオード(1)のバイアス電圧
と、 該アバランシェフォトダイオード(1)に流れる直流電
流を入力光信号のマーク率で除算した値とを合成してモ
ニタレベルとすることを特徴とする光受信レベルモニタ
回路。
[Claims] In an optical receiving circuit that stabilizes the output amplitude of a data identification circuit (9) by controlling the multiplication factor of an avalanche photodiode (1) and the amplification degree of an electric AGC amplifier (4) , A light source characterized in that a monitor level is obtained by combining the bias voltage of the avalanche photodiode (1) and a value obtained by dividing the direct current flowing through the avalanche photodiode (1) by the mark rate of the input optical signal. Reception level monitor circuit.
JP60254014A 1985-11-13 1985-11-13 Light reception level monitor circuit Pending JPS62114341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60254014A JPS62114341A (en) 1985-11-13 1985-11-13 Light reception level monitor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60254014A JPS62114341A (en) 1985-11-13 1985-11-13 Light reception level monitor circuit

Publications (1)

Publication Number Publication Date
JPS62114341A true JPS62114341A (en) 1987-05-26

Family

ID=17259056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60254014A Pending JPS62114341A (en) 1985-11-13 1985-11-13 Light reception level monitor circuit

Country Status (1)

Country Link
JP (1) JPS62114341A (en)

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