JPS62114234A - Sealing method for semiconductor - Google Patents

Sealing method for semiconductor

Info

Publication number
JPS62114234A
JPS62114234A JP25433985A JP25433985A JPS62114234A JP S62114234 A JPS62114234 A JP S62114234A JP 25433985 A JP25433985 A JP 25433985A JP 25433985 A JP25433985 A JP 25433985A JP S62114234 A JPS62114234 A JP S62114234A
Authority
JP
Japan
Prior art keywords
semiconductor
resin
sealing
chip
reduced pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25433985A
Other languages
Japanese (ja)
Inventor
Hirohisa Hino
裕久 日野
Taro Fukui
太郎 福井
Shinji Hashimoto
真治 橋本
Masaya Tsujimoto
雅哉 辻本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP25433985A priority Critical patent/JPS62114234A/en
Publication of JPS62114234A publication Critical patent/JPS62114234A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To seal a semiconductor with high reliability with hermetical seal sufficient in practice by pouring liquid resin sealer and then deforming it under reduced pressure. CONSTITUTION:A substrate is spot-face (dug) in the height of the silicon of a semiconductor chip 2 as semiconductor placing portions 6. A wiring pattern 5 is fed via through holes 4 to the back surface of the organic substrate 1, and led to pins 7. A sealing method includes pouring liquid resin sealer to the portion 6 and the chip 2 and then pouring resin until gold wirings 3 are completely buried. The sealing resin contains optimally liquid epoxy resin to be mixed with a curing agent, a cure accelerator or the like.

Description

【発明の詳細な説明】 [技術分野] 本発明は、PGA (ピングリッド・アレイ)、LCC
(リードレスチップキャリヤ)等の半導体パッケージの
半導体部分の封止技術の分野に属する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to PGA (pin grid array), LCC
It belongs to the field of sealing technology for semiconductor parts of semiconductor packages such as (leadless chip carriers).

[背景技術] 一般に、半導体チップは温度、湿度、衝撃等の外的スト
レスから保護するために、半導体装置部を封止するのが
普通である。
[Background Art] Generally, in order to protect a semiconductor chip from external stresses such as temperature, humidity, and shock, the semiconductor device portion thereof is usually sealed.

半導体素子の集積度が高まるにつれて、ICのバ・2ケ
ージングも多様化してきている。一般に、パッケージン
グ方法には、大別して、気密封止と樹脂封止があげられ
る。気密封止とは、ICチップを、リードフレームの上
にグイボンディングし、金ワイヤーで、チップとリード
を結び、その上下に空間を設けたまま、金属、セラミッ
ク、ガラス等で密閉してしまい、内部の空間に、不活性
の窒素ガスまたは、乾燥空気を入れて、封止する方法で
ある。この方法では、外部からの水分の浸入がほとんど
無く、温度、衝撃等の外部ストレスから保護されている
ために、半導体素子の信頼性が非常に高い。さらに、気
密封止の場合は、熱線膨張についての問題もなく、電気
絶縁性も良いため、封止方法として最適であるとされて
いた。
As the degree of integration of semiconductor devices increases, the packaging of ICs also becomes more diverse. In general, packaging methods can be broadly classified into hermetic sealing and resin sealing. Hermetic sealing involves bonding an IC chip onto a lead frame, connecting the chip and leads with gold wire, and sealing the chip with metal, ceramic, glass, etc. while leaving a space above and below it. This is a method of filling the internal space with inert nitrogen gas or dry air and sealing it. In this method, there is almost no intrusion of moisture from the outside and the semiconductor element is protected from external stresses such as temperature and impact, so the reliability of the semiconductor element is extremely high. Furthermore, in the case of hermetic sealing, there is no problem with thermal linear expansion and the electrical insulation is good, so it was considered to be the most suitable sealing method.

一方、パンケージングの形状としては、汎用ICの場合
、主にピン数が16〜24本位のDIP(デュアルイン
ラインパッケージ)が多かったが、高集積化と共に、パ
ッケージングの形状も様々なものが出てきた。ゲートア
レイに代表される外部取出しピンの多いLSI用のパッ
ケージには、PGA、LCC,FP (フラットパッケ
ージ)等も、使われるようになった。PGAには、ピン
数が100本以上のものも開発されている。これらは、
微細な回路を有しており、かつ寸法安定性が要求される
ために、やはり、はとんどセラミック材料を使用した気
密封止が採用されている。
On the other hand, in the case of general-purpose ICs, the shape of pancaging was mainly DIP (dual in-line package) with 16 to 24 pins, but with the increase in integration, various packaging shapes have become available. It's here. PGA, LCC, FP (flat package), etc. have also come to be used in LSI packages with many external pins, such as gate arrays. PGAs with more than 100 pins have also been developed. these are,
Since they have minute circuits and require dimensional stability, hermetic sealing using ceramic materials is often adopted.

以上のセラミック等を使用した気密封止は、材料が高価
で、成型に時間がかかるために、より簡易な封止方法の
提供が要望されていた。その要望を満たす封止方法とし
て、前記樹脂封止が注目されるようになっている。樹脂
封止は、半導体素子を樹脂中に埋込んでしまう方法であ
り、一般的には、IC基板としてセラミックス基板を使
用し、封止剤としてエポキシ樹脂を使用し、低圧トラン
スファー成型により封止する方法が、広く採用されてい
る。前記封止用樹脂はセラミックに比べて、低価格であ
るが、熱線膨張率が大きく、2つの材料間の熱線膨張が
著しく異なることになるので、界面の接着性も悪くなり
、機密性が低下し、結局信頼性を失う結果になっていた
The above-mentioned hermetic sealing using ceramics and the like requires expensive materials and takes time to mold, so there has been a demand for a simpler sealing method. The resin encapsulation is attracting attention as a encapsulation method that satisfies this demand. Resin encapsulation is a method of embedding semiconductor elements in resin. Generally, a ceramic substrate is used as the IC substrate, an epoxy resin is used as the sealant, and the semiconductor element is sealed by low-pressure transfer molding. The method has been widely adopted. Although the sealing resin is cheaper than ceramic, it has a large coefficient of linear thermal expansion, and the thermal linear expansion between the two materials will be significantly different, resulting in poor adhesion at the interface and reduced airtightness. However, this resulted in a loss of reliability.

この欠点を補うために、シリカ等の無機充填剤を封止用
樹脂中に多量に加えて熱膨張を小さくする試みがなされ
ているが、充分満足するような性能を得るには至ってい
ない。
In order to compensate for this drawback, attempts have been made to reduce thermal expansion by adding a large amount of inorganic filler such as silica to the sealing resin, but this has not resulted in fully satisfactory performance.

以上のような実情において、一層経済的で、機密性が良
く、信頼性に優れた封止体の開発が望まれていた。
Under the above circumstances, it has been desired to develop a sealed body that is more economical, has better confidentiality, and is more reliable.

[発明の目的] 半導体の封止に際して、上記のセラミック等による封止
方法より簡便で、実用上充分な機密性を有し、信頼性の
ある封止方法を提供することを目的とする。
[Object of the Invention] It is an object of the present invention to provide a sealing method for semiconductors that is simpler than the ceramic sealing method described above, has practically sufficient airtightness, and is reliable.

[発明の開示] この発明は、有機基板を用いて作られたPGA、LCC
等の半導体パッケージの半導体部分の封止方法であって
、液状樹脂封止剤を使用して、これを注入した後、減圧
下で脱泡すること特徴とする半導体の封止法を提供する
ものである。
[Disclosure of the Invention] This invention provides a PGA and LCC made using an organic substrate.
Provides a method for encapsulating a semiconductor part of a semiconductor package, such as the following, which uses a liquid resin encapsulant, and after injecting the same, degassing is performed under reduced pressure. It is.

以下、本発明を一実施例として掲げた図面に基づいて説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be explained based on drawings showing one embodiment of the present invention.

第1図は封止前の半導体チップを乗せたPGAの斜視図
であり、第2図は第1図のPGAを樹脂封止した様子を
示す斜視図である。有機基板1め材料としては、ガラス
基材エポキシ樹脂積層板、ポリイミド樹脂積層板、紙基
材フェノール樹脂積層板などがあげられるが、限定はし
ない。PGAパッケージの半導体搭載部6は、半導体チ
ップ2と、基板1の配線パターン5との間を金ワイヤ−
3で結ぶために、少し位置を低くする方が都合が良い。
FIG. 1 is a perspective view of a PGA with a semiconductor chip mounted thereon before sealing, and FIG. 2 is a perspective view showing the PGA of FIG. 1 sealed with resin. Examples of the first organic substrate material include, but are not limited to, glass-based epoxy resin laminates, polyimide resin laminates, paper-based phenolic resin laminates, and the like. The semiconductor mounting part 6 of the PGA package has a gold wire between the semiconductor chip 2 and the wiring pattern 5 of the substrate 1.
It is more convenient to lower the position a little in order to tie it at 3.

よって、半導体チップ2のシリコンの高さくらいのザグ
リ (掘り込み)を基板に作り、ここを半導体登載部6
とする。配線パターン5は、スルホール4を通って、有
機基板1の裏面に導かれ、ピン7に導通させる。封止方
法は、半導体登載部6や半導体チップ2へ液状の樹脂封
止剤を注入して行き、金ワイヤ−3が完全に埋没してし
まうまで、樹脂を注入する。
Therefore, make a counterbore in the substrate that is about the height of the silicon of the semiconductor chip 2, and place this counterbore in the semiconductor mounting part 6.
shall be. The wiring pattern 5 is guided to the back surface of the organic substrate 1 through the through hole 4 and is electrically connected to the pin 7. In the sealing method, a liquid resin sealant is injected into the semiconductor mounting part 6 and the semiconductor chip 2 until the gold wire 3 is completely buried.

ここで使用される封止用の樹脂としては、特に限定する
趣旨ではないが、液状のエポキシ樹脂が最適であり、こ
れに適宜、硬化剤、硬化促進剤等を配合して使用する。
Although the sealing resin used here is not particularly limited, a liquid epoxy resin is most suitable, and a curing agent, a curing accelerator, etc. are mixed therein as appropriate.

エポキシ樹脂としては、特に限定する趣旨ではないが、
ビスフェノールA型のもの等が使用される。また、硬化
剤としては、特に限定する趣旨ではないが、2,4−ジ
ヒドラジン−6−メチルアミノ−S−)リアジン(以下
、2.4−HT)またはアジピン酸ジヒドラジド等が好
ましい。最も好ましいのは2.4−HTである。エポキ
シ樹脂の粘度で、特に好ましい範囲は1万〜50万CP
S程度である。
The epoxy resin is not intended to be particularly limited, but
Bisphenol A type etc. are used. The curing agent is preferably 2,4-dihydrazine-6-methylamino-S-)riazine (hereinafter referred to as 2.4-HT) or adipic dihydrazide, although it is not intended to be particularly limited. Most preferred is 2.4-HT. The viscosity of the epoxy resin is particularly preferably in the range of 10,000 to 500,000 CP.
It is about S.

なお、金ワイヤ−3が多数ボンディングされているため
、半導体登載部6に液状樹脂封止剤を注入して行く際、
多少空気が混入してしまう。また、封止剤自身にも空気
が混っていることもあるため、硬化の際、発泡現象を起
こすことがある。発泡すると、硬化物の耐湿性が悪化し
たり、強度が低下したりし、結局機密性、信頼性を低下
させる。また表面形状も悪化し商品価値を低下させる。
Note that since a large number of gold wires 3 are bonded, when injecting the liquid resin sealant into the semiconductor mounting part 6,
Some air will be mixed in. Furthermore, since the sealant itself may contain air, foaming may occur during curing. When foaming occurs, the moisture resistance of the cured product deteriorates, the strength decreases, and eventually the airtightness and reliability decrease. Moreover, the surface shape deteriorates, reducing the commercial value.

そこで、発泡をなくするために、脱泡工程を設けること
が有効である。すなわち、樹脂封止したPGA等を減圧
下に置いて脱泡する。減圧脱泡は、常温で行うのが望ま
しいが、場合によっては、たとえば封止樹脂の粘度が高
くて、脱泡にくい時には、封止剤の性能を悪化させない
程度に加温してもかまわない。脱泡工程は、I Tor
r位の減圧下に、30分位曝して、発泡が、はぼ無くな
るのを目安とするが、減圧度や、時間は限定しない。発
泡がほとんどなくなった状態で、脱泡終了とするが、で
きるだGす完全に脱泡する方が望ましい。
Therefore, in order to eliminate foaming, it is effective to provide a defoaming step. That is, a resin-sealed PGA or the like is placed under reduced pressure to degas it. Degassing under reduced pressure is preferably carried out at room temperature, but in some cases, for example, when the sealing resin has a high viscosity and defoaming is difficult, it may be heated to an extent that does not deteriorate the performance of the sealant. The defoaming process is performed using I Tor
As a guideline, the foaming should be completely eliminated by exposing the product to a reduced pressure of R for about 30 minutes, but the degree of reduced pressure and the time are not limited. Defoaming is completed when there is almost no foaming, but it is preferable to completely defoam as much as possible.

以上の様にして、半導体登載部6を封止し、脱泡した後
、樹脂を硬化させて、第2図に示す様な、樹脂封止8し
たPGAを得るのである。
After the semiconductor mounting portion 6 is sealed and defoamed in the manner described above, the resin is cured to obtain a resin-sealed PGA 8 as shown in FIG.

次ぎに、前記のようにして樹脂封止したPGAの性能を
調べるために、PCT(プレッシャークツカーテスト)
およびTHB試験を行い、その結果を第1表に示した。
Next, in order to examine the performance of the PGA resin-sealed as described above, we conducted a PCT (Pressure Couple Test).
and THB test were conducted and the results are shown in Table 1.

比較のために、樹脂封止工程において、減圧脱泡しない
場合についても調べて表中に併記した。
For comparison, the case where degassing under reduced pressure was not performed in the resin sealing process was also investigated and is also listed in the table.

第1表 [発明の効果] この発明は、有機基板を用いて作られたピングリッド・
アレイ、リードレスチップキャリヤ等の半導体パッケー
ジの半導体部分の封止方法であって、液状樹脂封止剤を
使用し、これを注入した後、減圧下で脱泡すること特徴
とするので、簡便に、かつ実用上充分な機密性を保持し
、結局信頼性の高い半導体パッケージが提供できると言
う効果がある。
Table 1 [Effects of the invention] This invention provides a pin grid made using an organic substrate.
A method for encapsulating semiconductor parts of semiconductor packages such as arrays and leadless chip carriers, which uses a liquid resin encapsulant and is characterized by degassing under reduced pressure after injecting it, making it easy to use. , and maintains practically sufficient confidentiality, resulting in the provision of a highly reliable semiconductor package.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体を搭載した封止前のPGAを示す斜視図
、第2図は封止後のPGAを示す斜視図である。 1・・・・・・有機基板 2・・・・・・半導体 3・・・・・・金ワイヤ− 4・・・・・・スルホール 5・・・・・・配線パターン 6・・・・・・ザグリ部 7・・・・・・ピン 8・・・・・・封止樹脂。 第1図 第2図
FIG. 1 is a perspective view of a PGA mounted with a semiconductor before sealing, and FIG. 2 is a perspective view of the PGA after sealing. 1...Organic substrate 2...Semiconductor 3...Gold wire 4...Through hole 5...Wiring pattern 6... - Counterbored portion 7...Pin 8...Sealing resin. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)有機基板を用いて作られたピングリッド・アレイ
、リードレスチップキャリヤ等の半導体パッケージの半
導体部分の封止方法であって、液状樹脂封止剤を使用し
、これを注入した後、減圧下で脱泡すること特徴とする
半導体の封止法。
(1) A method for sealing a semiconductor part of a semiconductor package such as a pin grid array or a leadless chip carrier made using an organic substrate, which uses a liquid resin sealant, and after injecting the liquid resin sealant, A semiconductor encapsulation method characterized by degassing under reduced pressure.
JP25433985A 1985-11-13 1985-11-13 Sealing method for semiconductor Pending JPS62114234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25433985A JPS62114234A (en) 1985-11-13 1985-11-13 Sealing method for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25433985A JPS62114234A (en) 1985-11-13 1985-11-13 Sealing method for semiconductor

Publications (1)

Publication Number Publication Date
JPS62114234A true JPS62114234A (en) 1987-05-26

Family

ID=17263625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25433985A Pending JPS62114234A (en) 1985-11-13 1985-11-13 Sealing method for semiconductor

Country Status (1)

Country Link
JP (1) JPS62114234A (en)

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