JPS62114194A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the malfunction of an unselected word line at the time of active pull-up operation and to reduce the peak load of current consumption by operating the active pull-up circuits of a pair of bit lines divided into plural blocks that intersect the same word line successively at every time interval. CONSTITUTION:A pair of bit lines that intersect the same word lines WL1, WL0 are divided into two groups of blocks of bit line BL0 and inversion BL0, BL2 and inversion BL2..., BL1 and inversion BL1, BL3 and inversion BL3... etc. Corresponding active pull-up circuits AR0, AR2..., AR1, AR3..., etc., of the pair of bit lines of blocks of bisection, etc., are operated successively by clocks phiR0, phiR1. By this divided operation, the wave height of coupling noise of positive direction received from bit lines intersected by unselected word lines is made small, and it is not necessary to make the degree of conduction of a transistor that forms a leak bus of word lines WL0, WL1 too large, and the malfunction of unselected word lines can be prevented. Further, the peak load of current consumption can be lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to improvement of a semiconductor memory device such as a dynamic RAM having an active pull-up circuit.

[Prior Art] In a dynamic MO3-RAM, after sensing the bit line potential according to the data stored in the memory cell, an active pull-up circuit operates and pulls the "H" level bit line potential to VCO (power supply voltage) or Pulling up even more than that is being done.

FIG. 3 is a circuit diagram showing the periphery of a sense system in a conventional dynamic RAM. In the figure, a pair of pits 1
IBLo and BLo are transistors Qo and o, respectively.
* Connected to data bus ■10 and Ilo via Qo+. The on/off state of these transistors Qθo and Qo+ is controlled by the output of the column decoder 1, and is turned on when selected.

11 to 1 transistor/1 capacitor type memory cells MC are connected to each pit line. Each memory cell MC
The word lines WLo, WL+.

... is connected. Also, bit filF31-o,
One dummy memory cell DM is installed in each of πI-0.
C is connected. These dummy memory cells DMG include
Dummy word line WLDMo, WLD
M+ is connected. Also, Pi 1~Ren 13Lo, BL
o have transistors QP mu and QP, respectively.
* Precharge electric voltage VP connection is connected via +. These transistors QP * ov QP * +
The on/off of is controlled by the precharge clock φP.

Further, a sense amplifier S A o and an active pull-up circuit APO are connected to the pit line B Lo , 1 O 0 . The third sense amplifier SAo is for detecting the potential of the pit lines BLo, BLo, and its operation is controlled by the sense amplifier drive signal φ. The active pull-up circuit APG is for pulling up the potential of the selected pit line after the operation of the sense amplifier S, and its operation is controlled by the clock φR.

On the other hand, each word line WLo, WL+, . . . has a transistor Q20.027.
... is connected. These transistors 0201Q2
4. . . . is for discharging positive noise received by each word line during word line selection and active pull-up operation to the ground, and the conductivity of each transistor is controlled by signal RQ.

Note that in an actual semiconductor memory, memory cells MC and dummy memory cells DMC are arranged in a matrix, and there are a plurality of bit line pairs (BL).

and BLo, 81 and BLs, . . . 6. FIG. 4 is a timing chart showing the operation timing of the circuit shown in FIG. 3. In this Figure 4, φ
≦, φF, φF, and RQ respectively correspond to the signals shown in FIG. 3, BL and BL represent potential changes of the bit line pair, and WLo and WL+ represent the word lines WLo, It represents the potential change of WL.

Note that RA100 represents a row address stave signal. This row address strobe signal RAS is a signal for defining the non-active wJ111 and the active period. Below, referring to this Figure 4, the third
The operation of the n-way shown in the figure will be explained.

First, during the non-active period, that is, the period when the row address strobe signal RAS is "H", the RI0tsuk φP is "H".
Therefore, the transistor QF * o * Q
Both r*+ are on, and each pit 1118
1-o, [31To is precharged to a potential of VP1 by a precharge voltage aivP.

After that, the D-address strobe signal kT1 falls and the active) IJIll starts. During this active period, one of the word lines and one of the dummy word lines
A book is selected and each potential rises. Note that here, the word line W L o and the dummy word 1 m W
l-DMoffi is selected.

After this selection, the clock φP rises and the sense amplifiers SAo, . . . are activated. As a result, 11
1 Pit line BLo on the N level side... (representatively 8
1) is the ground level. After this, the clock φ rises and the active pull-up circuit APO, ・
... is activated, and active pull-up operation of the pit line is started. As a result, the pit lines 8Lo, . . . (representatively written as BL) on the H'' level side are pulled up to the power supply voltage VCe.

Here, the precharge potential of bits IIBL and BL is
For example, in the case of (1/2) Vce, half of the total pit lines in the semiconductor memory device are (1/2)
It will be pulled up from Vcc to VCC.

Therefore, at this time, as shown in FIG. 5, the value of the operating cost 11RNIcc of the semiconductor memory device reaches its peak. At this time, regarding an unselected word line (for example, WL+), a large number (usually several hundreds) of pit lines that intersect with this word line are pulled up from (1/2) Vcc to Vcc. Therefore, the unselected word lines receive a large noise in the positive direction through the pit line-word line coupling chamber, and the potential of each word line increases. When the potentials of the unselected word lines exceed the threshold voltage VT of the transfer gate of the memory cell MC (Fig. 5, 11).
, the unselected word line becomes selected, and the data stored in the memory cells connected to it are destroyed.

Incidentally, each word line is connected to a transistor Q201Q2+*... whose gate receives a signal RQ. This signal RQ is Vy + (X
(αL & 0.1~0.2 V(F) small sana 1lffi)
Transistor Q2o *
Q2 + t... is in a high resistance state. Therefore, a weak leakage bus (II leakage current red path) is formed by the transistor Q20 e Q2 + *..., which prevents the unselected word line from rising during word line selection and active pull-up operation. . However, if the leakage current in this leakage bus becomes too large, a problem arises in that the potential of the selected word line that has been pulled up decreases. It has been difficult to effectively cancel coupling noise.

[rIIJ problem to be solved by the invention] Since the conventional semiconductor memory device is configured as described above, the non-selected word is There was a problem that the level of the line rose and became undesirably selected.

This invention was made to solve the above-mentioned problems, and it is possible to prevent erroneous selection of unselected word lines and to reduce the peak value of current consumption during active pull-up. The purpose of the present invention is to provide a semiconductor memory device that can perform the following steps.

[Means for Solving the Problems] A semiconductor storage device according to the present invention divides a plurality of bit line pairs that intersect with the same word line into a plurality of blocks, and performs an active pull-up operation on the bit lines of each block. These steps are not performed simultaneously, but are performed sequentially with a time difference.

[Operation] The plurality of bit line pairs in the present invention are divided into a plurality of blocks, and the active pull-up circuits connected to each bit line pair perform active pull-up operations with a time difference for each block. This reduces the noise in the positive direction that the word line receives, and also reduces the peak value of the W4 current.

[Embodiment] FIG. 1 is a schematic diagram showing the vicinity of an active pull-up circuit system in an embodiment of the present invention based on its planar layout. In the figure, in a highly integrated dynamic RAM, the pitch between bits m is very small, and the active pull-up circuit has Ro, △R1,
. . . is a line of layer I in the l11 (up and down) direction of the figure.
It is difficult to
Often arranged in columns. Each bit line pair BLo and BL
Active pull-up circuits ARa, AR+, . . . are connected to O, BL, and BL+, -. Conventionally, these active pull-up circuits ARo,
AR+, . . . were controlled to be activated simultaneously by one clock φR. However, in this embodiment, of the active pull-up circuits arranged in two columns in the vertical direction, the active pull-up circuits in the right column, that is, the even-numbered active pull-up circuits ARn, AR2.
, . . . are driven by the clock φRQ, and are driven by the active pull-up circuits in the left column, that is, the odd-numbered active pull-up circuits AR+, ARs, . In addition, word lines WLo'e WL+,... are arranged to intersect with each bit line, and memory cells are arranged at the intersections of these word lines and bit lines (this is indicated by an O in the figure). ). Note that in the above layout, the drive signal wiring for the active pull-up circuit is often 1.2 lines, and separate clocks φi0+φII+ are used for the active pull-up circuit in the right column and the active pull-up circuit in the left column. Inputting this information is not a burden on the layout.

FIG. 2 is a diagram showing the relationship between the rising timing of the clock φtO+φ, the change in potential of the unselected word mWL during active pull-up operation, and the change in 1 cc of system power supply current during active pull-up operation. It is. As shown in the figure, clocks φ, a, etc. φ5.
rises at the time III difference [d. In this way, as shown in the figure, the wave height of the coupling noise in the positive direction received by the unselected word line WL becomes small. Therefore, a leak bus is formed]・Ransistor Q 201Q
24. . . . (see FIG. 3), it is possible to prevent the potential of the unselected word line from exceeding the transfer voltage VT of the memory cell MC without increasing the channel voltage too much. Therefore, it is possible to solve the problem of the conventional device in which the potential of the selected word line decreases due to a leak bus. In addition, in this case, the bit lines are pulled up by half (1/4 of the total number of bit lines) with a time difference of 6, so the leakage current is small and J:<, which is also compared to the conventional example. It's advantageous. Furthermore, this embodiment has the advantage that the peak value of 1 cc of large current consumption that occurs during active pull-up can be reduced (see FIG. 2), increasing the margin for the power supply of the memory system.

In addition, in the above embodiment, a method was shown in which each active pull-up circuit connected to each pit line pair is divided into two systems and each system is driven at a different time. It is not necessary to allocate the data to each other, and the same effect as in the above embodiment can be obtained no matter what method is used to allocate the data. Further, the active pull-up circuit may be divided into a plurality of systems and driven at different times, and the present invention is not limited to a circuit in which the active pull-up circuit is divided into two systems as in the above embodiment.

Furthermore, active pull-up operation is not limited to the NMO8 circuit system, but also the NMOS sense amplifier, P
The present invention can be similarly applied to cases where it can be regarded as a MOS pull-up circuit.

[Effect of the Invention 1 As described above, according to the present invention, it is possible to prevent incorrect selection of unselected word lines during active pull-up operation, and to reduce the peak value of current consumption, resulting in high reliability and power supply system. It is possible to obtain a semiconductor device that can reduce the peak load of.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an embodiment of the present invention based on its planar layout. Figure 2 shows the rise timing of the clock φ@otφ used in the circuit of Figure 1, the potential change of the unselected word line WL, and the power consumption current ■tc
FIG. FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device. FIG. 4 is a timing chart without showing the operation timing of the circuit shown in FIG. 3. FIG. 5 is a waveform diagram showing the relationship between the rising timing of the clock φ used in the circuit 1 shown in FIG. 3, the potential change of the unselected word line WL, and the power consumption 11 m I c c. In the figure, BL'o, BLo, ... are pit lines, W Lo, W L +, - are word lines,
ARo, A=13-R1,... is an active pull-up circuit, φff1D
+φ5. indicates the drive clock of the active pull-up circuit. Agent: Masu Oiwa, Yumani, Figure 2, OV foil, Figure 5, 1, Incident indication, Patent Application No. 1986-257086, 2,
Name of the invention: Semiconductor storage device 3; Person making the amendment; 5; Detailed description of the invention in the specification subject to amendment; column 6; Contents of the amendment; ] Delete. that's all

Claims (2)

[Claims] (1) A plurality of bit line pairs to which a plurality of memory cells are connected, a word line arranged to intersect with the bit line and for selecting the memory cell, and a word line connected to each of the bit line pairs and connected to this potential. A semiconductor memory device comprising a sense amplifier for sensing and an active pull-up circuit for pulling up the potential of each bit line after a sensing operation of the sense amplifier, wherein the bits intersect with the same word line. A semiconductor memory device, wherein a line group is divided into a plurality of blocks, and the active pull-up circuit operates with a time difference for each block. (2) The bit line group is arranged alternately in two bit line pairs for each bit line pair.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is divided into system blocks.