JPS62113454A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62113454A JPS62113454A JP25274685A JP25274685A JPS62113454A JP S62113454 A JPS62113454 A JP S62113454A JP 25274685 A JP25274685 A JP 25274685A JP 25274685 A JP25274685 A JP 25274685A JP S62113454 A JPS62113454 A JP S62113454A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- bending
- semiconductor device
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、プラスチックパッケージ型半導体装置の製造
方法に関し、特に、チップサイズの大きい高容量メモリ
ＬＳＩに好適な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a plastic package type semiconductor device, and particularly to a method of manufacturing a semiconductor device suitable for a high capacity memory LSI with a large chip size.
従来のプラスチックパッケージ型半導体装置の製造方法
は、まず、第４図に示す如く、タブ２上にチップ１を接
着し、チップーヒの電極とリードフレーム４上の電極間
をワイヤ３で結んだものを下金型６と上金型５の間には
さみ、その間にレジン７を圧入して固め、これを次に、
第５図に示す如く、曲げダイ８とノック、アウト９の各
々のつめ８’ 、９’の間にはさみ、Ｑ−ラ１０でリー
ドフレーム４を折り曲げ、第６図の完成品に示す如く製
造していた。しかし、この方法では、最近のチップ１の
サイズの増大に伴い、つめによるはさみ代Ｑ′が充分と
れなくなり、折り曲げ時に、第７図に示すようにリード
フレーム４の折り曲げ防止値に剥離領域１１が発生する
危険が生じてきた。The conventional manufacturing method of a plastic package type semiconductor device is as shown in FIG. It is sandwiched between the lower mold 6 and the upper mold 5, and the resin 7 is press-fitted between them to harden it.
As shown in FIG. 5, the lead frame 4 is sandwiched between the bending die 8 and the claws 8' and 9' of the knockout/out 9, and is bent with the Q-ra 10, producing the finished product as shown in FIG. Was. However, with this method, with the recent increase in the size of the chip 1, it is no longer possible to take enough scissoring allowance Q' by the claws, and when the lead frame 4 is bent, a peeling area 11 is caused in the bending prevention value of the lead frame 4, as shown in FIG. There is a danger that this may occur.
この剥離を防止する方法として、例えば特開昭５８−２
０４８号公報に開示されている方法があるが、これでも
不充分である。As a method for preventing this peeling, for example, JP-A-58-2
There is a method disclosed in Japanese Patent No. 048, but this method is still insufficient.
本発明の目的は、リード折り曲げ時に発生するリードフ
レームとレジン間の剥離を防止し、耐湿、耐食性能の高
い半導体装１ユを得ることである。An object of the present invention is to prevent peeling between a lead frame and resin that occurs when bending leads, and to obtain a semiconductor device unit with high moisture resistance and corrosion resistance.
本発明は、半導体装置の製造時において、リード折り曲
げを、モールデ・ｒレグ工程時あるいはモ−ルディング
工程前に行うようにしたことを特徴とするものである。The present invention is characterized in that lead bending is performed during the molding/r-leg process or before the molding process during the manufacture of semiconductor devices.
以下、本発明の一実施例を第１図により説明する。チッ
プ１．タブ２．ワイヤ３９図のように既で折り曲げられ
たリードフレーム４の接合体を、このリードフレームの
形状に合わせて既に形成させられた上金型５′及び下金
型６′間にはさみ、この後レジン７をモールディングす
る。あるいは、上金型５′及び下金型６′をリードフレ
ーム４を折り曲げるプレス金型にも兼用することにより
。An embodiment of the present invention will be described below with reference to FIG. Chip 1. Tab 2. Wire 39 As shown in the figure, the joined body of the lead frame 4 which has already been bent is sandwiched between the upper mold 5' and the lower mold 6' which have already been formed to match the shape of this lead frame, and then the resin is inserted. Molding 7. Alternatively, the upper mold 5' and the lower mold 6' may also be used as press molds for bending the lead frame 4.
リードフレーム４の折り曲げ工程と、モールディング工
程を結びつけて行うことができる。The bending process of the lead frame 4 and the molding process can be performed in combination.
第２図は他の実施例で、チップ１の寸法が大きくなった
場合、リードフレーム４がレジン７に接着されている領
域１２を充分とるためにリードフレームの両サイドを上
金型５′の内壁に１３の部分で当てるようにしたもので
ある。FIG. 2 shows another embodiment in which when the size of the chip 1 becomes large, both sides of the lead frame are attached to the upper mold 5' in order to secure a sufficient area 12 where the lead frame 4 is bonded to the resin 7. It is designed so that it touches the inner wall at part 13.
第３図も他の実施例で、上金型５′と下金型６′の間に
中間金型１４を用い、リードフレーム４の上部４′が全
てレジン７に包まれてしまうような構造にしたもので、
この構造になれば、チップサイズが充分大きくなった場
合でも、リードフレームとレジン７との接着域充分にと
ることができ、耐湿性、耐食性のよい半導体装置を装作
することができる。FIG. 3 shows another embodiment, in which an intermediate mold 14 is used between the upper mold 5' and the lower mold 6', and the upper part 4' of the lead frame 4 is entirely covered with the resin 7. It was made into
With this structure, even if the chip size becomes sufficiently large, a sufficient adhesive area between the lead frame and the resin 7 can be secured, and a semiconductor device with good moisture resistance and corrosion resistance can be mounted.
本発明によれば、リードフレームをレジンモールディン
グ時あるいは、レジンモールディング前に折り曲げるた
め、従来の、レジンモールド後にリードフレームを折り
曲げていた時のような、折り曲げ部近傍でのリードフレ
ームとレジンとの剥離が防止でき、耐湿性、耐食性のい
い半導体装置を製造、提供できる効果がある。According to the present invention, since the lead frame is bent at the time of resin molding or before resin molding, separation of the lead frame and resin near the bending part is avoided, unlike when the lead frame is bent after resin molding in the conventional case. This has the effect of making it possible to manufacture and provide semiconductor devices with good moisture resistance and corrosion resistance.
第１図は本発明の製造方法の一実施例を説明するための
モールディング状態の断面図、第２図及び第３図は本発
明の詳細な説明するためのモールディング状態の断面図
、第４図〜第６ｖＩＩは従来の製造方法の一例を説明す
る図で第４図はモールディング状態の断面図、第５図は
リードフレーム折り曲げ状態の断面図、第６図は完成さ
れた半導体装置の断面図、第７図は従来の方法でリード
フレームを折り曲げ成形した場合の剥離発生状態の部分
断面図である。
１・・・半導体素子（チップ）、２・・・タブ、３・・
・ワイヤ、４・・・リードフレーム、５・・・上金型、
６・・・下金第 ｌ 口
第 ２ 日
第 ３ 図
第 ４ 口FIG. 1 is a cross-sectional view of a molded state for explaining an embodiment of the manufacturing method of the present invention, FIGS. 2 and 3 are cross-sectional views of a molded state for explaining the present invention in detail, and FIG. ~6vII is a diagram explaining an example of a conventional manufacturing method, FIG. 4 is a sectional view of a molded state, FIG. 5 is a sectional view of a lead frame in a folded state, and FIG. 6 is a sectional view of a completed semiconductor device. FIG. 7 is a partial sectional view of a state in which peeling occurs when a lead frame is bent and formed by a conventional method. 1... Semiconductor element (chip), 2... Tab, 3...
・Wire, 4...Lead frame, 5...Upper mold,
6...Shimogane 1st day 2nd day 3rd day 4th day
Claims (1)
ワイヤで接続したものを、レジンで封止して成る半導体
装置において、リードフレームの折り曲げを、レジンモ
ールディング工程時に、あるいはレジンモールディング
工程前に行うことを特徴とする半導体装置の製造法方。In a semiconductor device in which a semiconductor element (chip) and a lead frame each having electrodes connected by wires are sealed with resin, the lead frame is bent during or before the resin molding process. A method for manufacturing a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25274685A JPS62113454A (en) | 1985-11-13 | 1985-11-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25274685A JPS62113454A (en) | 1985-11-13 | 1985-11-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62113454A true JPS62113454A (en) | 1987-05-25 |
Family
ID=17241700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25274685A Pending JPS62113454A (en) | 1985-11-13 | 1985-11-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62113454A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1119037A3 (en) * | 1996-08-20 | 2001-10-10 | Hitachi, Ltd. | Semiconductor device and method of manufacturing thereof |
-
1985
- 1985-11-13 JP JP25274685A patent/JPS62113454A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1119037A3 (en) * | 1996-08-20 | 2001-10-10 | Hitachi, Ltd. | Semiconductor device and method of manufacturing thereof |
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