JPS62112433A - Clock distribution equipment - Google Patents
Clock distribution equipmentInfo
- Publication number
- JPS62112433A JPS62112433A JP60251933A JP25193385A JPS62112433A JP S62112433 A JPS62112433 A JP S62112433A JP 60251933 A JP60251933 A JP 60251933A JP 25193385 A JP25193385 A JP 25193385A JP S62112433 A JPS62112433 A JP S62112433A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- clock signal
- clock
- line
- delay amount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はデジタル通信機器を構成するクロック分配装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock distribution device constituting a digital communication device.
従来、この種の複数の筺体にわたる大規模なデジタル通
信機器において各筺体に位相の揃ったクロック信号を送
出する方法としては、筺体間の遠近によらず全供給ケー
ブルの長さを同一にする方法があった。Conventionally, in this type of large-scale digital communication equipment that spans multiple chassis, the method of sending clock signals with the same phase to each chassis is to make all supply cables the same length regardless of the distance between the chassis. was there.
上述した従来のクロック信号送出方法は全供給ケーブル
の長さを一定とするため、機器の増設を含め最大長が数
十−mもしくは百m以」二となる場合もあり、隣接する
筺体間にこのような長大なケーブルを敷設することは設
備の無駄でもあり、また、美観上も好ましくない。In the conventional clock signal transmission method described above, the length of all supply cables is fixed, so the maximum length, including equipment expansion, may be several tens of meters or even more than 100 meters. Laying such a long cable is a waste of equipment and is also undesirable from an aesthetic point of view.
このような問題点を解決するために本発明は、伝送遅延
量測定線路に接続され高周波パルス列を発生する高周波
パルス発生回路とクロック信号の遅延量を検出する為に
パルスを計数するパルス計数回路とを有する伝送遅延量
測定部と、タップが設けられた遅延線路とタップを選択
するセレクタとを有するクロック信号送出部とをクロッ
ク分配装置に設けるようにしたものである。In order to solve these problems, the present invention provides a high-frequency pulse generation circuit that is connected to a transmission delay measurement line and generates a high-frequency pulse train, a pulse counting circuit that counts pulses to detect the delay amount of a clock signal, and A clock distribution device is provided with a transmission delay amount measuring section having a transmission delay amount measuring section, and a clock signal sending section having a delay line provided with a tap and a selector for selecting the tap.
本発明にむいては、伝送遅延量測定線路を介してクロッ
分配装置と各筺体との間を往復した高周波パルス列の往
復時間を検出し1、この往復時間に基づいて自動的に設
定された遅延量を有するクロック信号を送出する。In the present invention, the round-trip time of the high-frequency pulse train that went back and forth between the clock distribution device and each housing via the transmission delay measurement line is detected1, and the delay is automatically set based on this round-trip time. Sends out a clock signal having a certain amount.
本発明に係わるクロック分配装置の一実施例が適用され
たデジタル通信機器を第1図に示す。第1図ニt、;イ
て、1は本実施例としてのクロック分配装置、2はクロ
ック発生部、3はクロック信号供給ケーブル10a、R
obにおけるクロック信号の遅延であるケーブル遅延を
測定するだめの伝送遅延量測定部、4はずべての筺体9
a、9bにおいて同一位相のクロック信号を受信するた
めにケーブル遅延に応じて遅延量が設定されたクロック
信号を送出するクロック信号送出部である。FIG. 1 shows a digital communication device to which an embodiment of the clock distribution device according to the present invention is applied. In FIG. 1, 1 is a clock distribution device according to this embodiment, 2 is a clock generator, and 3 is a clock signal supply cable 10a, R.
Transmission delay measurement unit 4 is for measuring the cable delay, which is the delay of the clock signal in ob, in all cases 9
This is a clock signal sending section that sends out a clock signal with a delay amount set according to the cable delay in order to receive clock signals of the same phase at the terminals a and 9b.
伝送遅延量測定部3は、クロック信号供給ケーブル10
a、10b内にクロック信号線11a。The transmission delay measurement section 3 is connected to a clock signal supply cable 10.
a, a clock signal line 11a in 10b;
11bと併設された伝送遅延量測定線路12a。A transmission delay amount measurement line 12a is provided alongside 11b.
12bに接続され高周波パルス列を発生する高周波パル
ス発生回路5と、クロック供給ケー゛プル10a、lO
b対応に設備されクロック信号の遅延量を検出する為に
パルスを計数するパルス計数回路6a、6bとから構成
される。クロック信号送出部4は、ケーブル遅延に応じ
た遅延量を発生するための数種類のタップが設けられた
遅延線路7と、クロック供給ケーブル10a、10b対
応に設備されケーブル遅延に応じた遅延量を有するクロ
ック信号を出力するためにタップを選択するセレクタ8
a、8bとから構成される。またクロック信号の供給を
受ける各筺体9a、9bはクロック供給ケーブルlOa
、10bに接続されている。12b and generates a high-frequency pulse train, and clock supply cables 10a and 10
The pulse counting circuit 6a and 6b are provided for counting pulses in order to detect the delay amount of the clock signal. The clock signal sending unit 4 has a delay line 7 provided with several types of taps for generating a delay amount according to the cable delay, and a delay line 7 that is installed to correspond to the clock supply cables 10a and 10b and has a delay amount according to the cable delay. Selector 8 for selecting a tap to output a clock signal
It is composed of a and 8b. Each housing 9a, 9b receiving the clock signal is connected to the clock supply cable lOa.
, 10b.
高周波パルス発生回路5では、第2図(alに示す送出
パルス列を発生し、伝送遅延量測定線路12a、12b
およびパルス計数回路6a、6bに対し供給している。The high-frequency pulse generation circuit 5 generates the transmission pulse train shown in FIG.
and is supplied to pulse counting circuits 6a and 6b.
伝送遅延量測定線路12aを往復して戻ってきたパルス
列が第2図(blに示す返送パルス列のようなものであ
った場合、パルス計数回路6aにおいて計数されたパル
ス数は、第2図(C1に示すように、6バルスとなる。If the pulse train that has traveled back and forth on the transmission delay measurement line 12a and returned is like the return pulse train shown in FIG. 2 (bl), the number of pulses counted in the pulse counting circuit 6a is as shown in As shown, there are 6 pulses.
第2図+a)に示す送出パルス列の周波数が50MHz
の場合、計数されたパルス数が6ということは、6X2
0ns=120nsの遅延が伝送遅延量測定線路12a
において発生したことを示している。仮に各筺体9a、
9bの受信端でのクロック信号の遅延量を200nsと
設定してあったとすれば、さらに140ns=200
n s −120n s / 2の遅延を与えればよい
。The frequency of the sending pulse train shown in Figure 2+a) is 50MHz
In this case, the number of counted pulses is 6, which means 6X2
A delay of 0ns=120ns is the transmission delay measurement line 12a.
This indicates that this occurred in If each housing 9a,
If the delay amount of the clock signal at the receiving end of 9b was set to 200ns, then the delay amount would be 140ns = 200ns.
It is sufficient to provide a delay of ns - 120ns/2.
この判定結果に従い、パルス計数回路6aは遅延線路7
のタップの選択を行うセレクタ8aを制御し、セレクタ
8aは140nsの遅延を持ったクロック信号を送出す
る。According to this determination result, the pulse counting circuit 6a controls the delay line 7.
The selector 8a selects a tap, and the selector 8a sends out a clock signal with a delay of 140 ns.
〔発明の効果]
以上説明したように本発明は、間欠的に送出される高周
波パルス列を往復−灯の伝送遅延量測定線路を介してク
ロッ分配装置とクロック信号の供給をうける各筺体との
間を往復させ、パルス計数回路により高周波パルス列が
クロック信号供給ケーブル内を往復する往復時間を検出
し、予め定められた遅延量が各筺体のクロック受信端で
得られるように伝送遅延量測定線路の往復時間に基づい
て自動的に遅延線路のタップを選択することにより、送
出するクロック信号の遅延量を選択できるようにしたの
で、長大な等長ケーブルを用いることなく、またケーブ
ル線長を意識することなく、すべての筺体において同一
位相のクロック信号を受信することを可能にする効果が
ある。[Effects of the Invention] As explained above, the present invention provides for transmitting a high-frequency pulse train that is intermittently sent back and forth between a clock distribution device and each housing that receives a clock signal via a transmission delay measuring line of a lamp. A pulse counting circuit detects the round trip time of the high frequency pulse train within the clock signal supply cable, and the round trip time of the transmission delay measurement line is detected so that a predetermined delay amount is obtained at the clock receiving end of each housing. By automatically selecting the taps of the delay line based on the time, it is possible to select the delay amount of the clock signal to be sent, so there is no need to use long cables of the same length, and there is no need to be conscious of the cable length. This has the effect of making it possible to receive clock signals of the same phase in all cases.
第1図は本発明に係わるクロック分配装置の一実施例が
適用されたデジタル通信機器を示す系統図、第2図は本
実施例を説明するためのタイムチャートである。
1・・・・クロック分配装置、2・・・・クロック発生
部、3・・・・伝送遅延量測定部、4・・・・クロック
信号送出部、5・・・・高周波パルス発生回路、6a、
6b・・・・パルス計数回路、7・・・・遅延線路、8
a、8b・・・・セレクタ、9a、9b−−・・筺体、
10a、10b・・・・クロック供給ケーブル、lla
、11b・・・・クロック信号線、12a、12b・・
・・伝送遅延量測定線路。FIG. 1 is a system diagram showing a digital communication device to which an embodiment of the clock distribution device according to the present invention is applied, and FIG. 2 is a time chart for explaining this embodiment. DESCRIPTION OF SYMBOLS 1... Clock distribution device, 2... Clock generation section, 3... Transmission delay amount measuring section, 4... Clock signal sending section, 5... High frequency pulse generation circuit, 6a ,
6b...Pulse counting circuit, 7...Delay line, 8
a, 8b...Selector, 9a, 9b...Housing,
10a, 10b...Clock supply cable, lla
, 11b...clock signal line, 12a, 12b...
...Transmission delay amount measurement line.
Claims (1)
ック信号供給ケーブルを介してクロック信号を供給する
クロック分配装置において、前記クロック信号供給ケー
ブルにおけるクロック信号の遅延であるケーブル遅延を
測定するための伝送遅延量測定部と、前記すべての筺体
において同一位相のクロック信号を受信するために前記
ケーブル遅延に応じて遅延量が設定されたクロック信号
を送出するクロック信号送出部とを備え、前記伝送遅延
量測定部は、前記クロック信号供給ケーブル内にクロッ
ク信号線と併設された伝送遅延量測定線路に接続され高
周波パルス列を発生する高周波パルス発生回路と、前記
伝送遅延量測定線路に接続されクロック信号の遅延量を
検出する為にパルスを計数するパルス計数回路とを有し
、前記クロック信号送出部は、前記ケーブル遅延に応じ
た遅延量を発生するためのタップが設けられた遅延線路
と、前記ケーブル遅延に応じた遅延量を出力するために
前記タップを選択するセレクタとを有し、間欠的に送出
される高周波パルス列を往復一対の前記伝送遅延量測定
線路を介してクロッ分配装置とクロック信号の供給をう
ける前記各筺体との間を往復させ、前記パルス計数回路
により前記高周波パルス列がクロック信号供給ケーブル
内を往復する往復時間を検出し、予め定められた遅延量
が前記各筺体のクロック受信端で得られるように前記往
復時間に基づいて自動的に遅延線路のタップを選択し、
すべての筺体において同一位相のクロック信号を受信で
きるようにしたことを特徴とするクロック分配装置。In a clock distribution device that supplies clock signals via a clock signal supply cable to multiple cases constituting large-scale digital communication equipment, transmission for measuring cable delay, which is the delay of the clock signal in the clock signal supply cable. a delay amount measuring section; and a clock signal sending section that sends out a clock signal with a delay amount set according to the cable delay in order to receive clock signals of the same phase in all the cases, The measuring section includes a high-frequency pulse generation circuit that is connected to a transmission delay amount measurement line that is installed alongside the clock signal line in the clock signal supply cable and generates a high-frequency pulse train, and a high-frequency pulse generation circuit that is connected to the transmission delay amount measurement line and that generates a transmission delay amount measurement line that is connected to the transmission delay amount measurement line that is connected to the clock signal line in the clock signal supply cable. and a pulse counting circuit that counts pulses in order to detect the amount of delay, and the clock signal sending section includes a delay line provided with a tap for generating a delay amount corresponding to the cable delay, and a pulse counting circuit that counts pulses to detect the amount of delay. and a selector for selecting the tap in order to output a delay amount according to the clock distribution device and a clock signal supplied through the pair of transmission delay measurement lines for reciprocating the high-frequency pulse train that is sent out intermittently. The pulse counting circuit detects the reciprocating time of the high-frequency pulse train within the clock signal supply cable, and a predetermined amount of delay is detected at the clock receiving end of each of the housings. automatically select the delay line taps based on the round trip time as obtained;
A clock distribution device characterized by being able to receive clock signals of the same phase in all cases.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60251933A JPS62112433A (en) | 1985-11-12 | 1985-11-12 | Clock distribution equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60251933A JPS62112433A (en) | 1985-11-12 | 1985-11-12 | Clock distribution equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62112433A true JPS62112433A (en) | 1987-05-23 |
Family
ID=17230128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60251933A Pending JPS62112433A (en) | 1985-11-12 | 1985-11-12 | Clock distribution equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62112433A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6472641A (en) * | 1987-09-08 | 1989-03-17 | Tektronix Inc | Skew correction apparatus |
JPH0446429A (en) * | 1990-06-13 | 1992-02-17 | Nec Corp | Phase locked loop oscillator |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5538749A (en) * | 1978-09-11 | 1980-03-18 | Meisei Electric Co Ltd | Synchronous system for data transmission |
-
1985
- 1985-11-12 JP JP60251933A patent/JPS62112433A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5538749A (en) * | 1978-09-11 | 1980-03-18 | Meisei Electric Co Ltd | Synchronous system for data transmission |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6472641A (en) * | 1987-09-08 | 1989-03-17 | Tektronix Inc | Skew correction apparatus |
JPH0446429A (en) * | 1990-06-13 | 1992-02-17 | Nec Corp | Phase locked loop oscillator |
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