JPS62112298A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To set a time required for fuse melting optionally by operating a fuse circuit from an outside directly with an address signal. CONSTITUTION:When an address signal Ext.A1 is set at L, an N-channel MOS transistor 11 keeps an off state, and even when a high voltage VP1 is impressed on a redundant power source terminal 3, a current is supplied scarcely through a fuse 10, therefore no fusion occurring. On the other hand, when the address signal Ext.A1 is led from L to H, the N-channel MOS transistor 11 is turned on and a node N1 becomes a 0 level. Next, when the VP1 is led, the current is supplied to the fuse 10 through a current paths of the fuse 10 and the N- channel MOS transistor 11 from the redundant power source terminal 3, thereby resulting the fusion. Thus, the time required for fusion can be set optionally and the fuse can be easily melted with a simple timing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit having a fuse tM in a redundant circuit and a fuse circuit which can be blown in a redundant circuit.

[Conventional technology]

Recently, with the development of dynamic MO8RAM, the chip size of the chip is increasing! This has become unavoidable with the miniaturization of the B manufacturing process. This increase in chip size and the 4I1 thinning process increase the probability that crystal defects will exist in a single chip.

Also, what about the effects of pattern defects and dust that occur during the manufacturing process? I have a big one. Therefore, dynamic MO8
A spare memory cell is provided in the RAM memory box, and a defective memory cell caused by crystal defects, pattern defects, or dust is replaced with a spare memory cell. Redundant circuits are widely used.

In such a redundant circuit, a fuse is required to replace a defective memory cell with a spare memory cell, and a method using this fuse's EV-source wire or an electrical method is used. The replacement was carried out by melting and cutting.

Figure 10 shows the dynamics of a conventional fuse circuit.
FIG. 19 is a circuit 1917 diagram showing an example of an OS RAM. In the figure, 1 is the address input terminal, and the at/input signal Et
, A, is applied, for example, in the case of a 256-bit dynamic MO8RAM, the input terminal 1 is Ext,
There are 9 runs from the 6th to Ext and As.

2 is a 7-domain V buffer circuit which receives the "L71/bell" or "R" level signal of the 7-ton signal Ext, A, and amplifies it;
It generates an in-phase output A, and an opposite-phase output A, .

3.4 is the first and second redundant power supply terminals used when melting the electric heater, and the first redundant tm terminal 3
VPI is applied to the second redundant power supply terminal 4, and VPI is applied to the second redundant power supply terminal 4.
PI is applied.

5 is the address signal -t, A, Y for latching the signal E, t, RAS (Row Ad
A clock terminal 6 for applying a clock signal (dressStrobe) is a RAS buffer circuit that generates various tarok signals based on the clock signals E, t, and RAS, and sends out a clock signal φ. T is a fuse circuit.

Controls the melting of electric heaters and provides a 7-volt voltage buffer circuit 2
The in-phase output AI, the opposite-phase output input i, and the clock signal φ which is also output from the RAS buffer circuit 6 are input. Reference numeral 8 denotes a poochor circuit, which is connected to the in-phase output A1 and the opposite-phase output A1 of the atto-VS buffer circuit 2. 9 is the RL terminal necessary to operate the dynamic MO8 RAMY (usually Vee=+S
V) is applied.

Figure 11 is an example of the fuse circuit γ shown in Figure 10. FIG. In the figure, 10 is a fuse, one end of which is connected to the redundant power supply terminal 3 of @1, and the other end is connected to the first node N, which generates the FC signal YxA, which is the output of the fuse circuit γ. . 11 is an N-channel MO for correcting the flow when the fuse 10 is blown.
S transistor, whose gate is connected to the second node N! The drain is connected to the first node N, and the source is connected to the ground terminal.

12 is a resistor that prevents the first node N1 from floating; its resistance value RI2 is sufficiently large; one end is connected to the first node N+K, and the other end is connected to the ground terminal. . , 13 is the first redundant power supply terminal 3 indicated by n■ and ■. A resistor with a resistance value R13 inserted between the eTIL source terminals 9, which becomes VPI when the fuse blows. It is also possible to apply a higher voltage (VPI = Ve- is also acceptable), and the first redundant voltage can be applied to the source terminal 3 voltage Vp during normal memory operation.
T'! It has the role of generating FCC signal light when it is not connected and left in the open state.

That is, during normal memory operation, if the fuse 10 is not blown, there will be a resistance at the first node N between the resistor 12 and the resistor 13;
Heater 10 is fused.

(6e) Since the supply of current from the power supply terminal 9 is cut off, the resistor 12 causes the first note NIK to have Ov. Therefore, when the fuse 10 is not blown, pc;v-, and when the fuse 10 is blown, FC
-OV. 14 is from the second redundant power supply terminal 4 to the second
Node N! An N-channel MO8 transistor for charging the RAS buffer IoJ, whose gate is approximately 6
01 output, the drain is connected to the second redundant [source terminal 4], and the source is connected to the second redundant [source terminal 4].
is connected to node N2 of 15 is 1st river 6th 2nd
This is an N-channel MOS transistor that controls the 0 node N20 node, and its gate is connected to the address node (the opposite phase outputs A and K of the Zuffer circuit 2, and the drain is connected to the second node).
The source is connected to the ground terminal N2, and the source is connected to the ground terminal.

Next, the operation will be explained according to the timing chart of the fuse blowing cycle shown in FIG.

However, it is assumed that the combination of address signals Ext and A corresponding to the address of a defective memory cell is known through a normal test in addition to the fuse blowing cycle.

First, ■ is attached to the ve0 power supply terminal 9. Clock signals E, t, and RAs are applied to the input terminal 5, and atomic signals E, j, Aly! corresponding to the defective address are applied to the address input terminal 1. /1 It is necessary to apply exactly the same operation as a normal memory operation.

That is, at time t, clock signal Ext.

RAS Y falls from "H" to L", maintains a constant ATO V S7 7 TPU interlacing and ATO 7 Shold interception before and after this time 11, and then outputs a 7 D/S signal Ext.

Apply AI'l. 2122 at time t+
When No. 45 φ is 1Hn, the reverse phase output of Ato 237171 circuit 2 A I Ka "L" nanote, second mate N 2 G
i, from Vp2 via the MOS transistor 14.
H"K light is being turned on. Therefore, at this time, the N-channel MOS transistor 11 is turned on, but ■P
Since 1 remains OV, fuse 10 has 111. The stream doesn't flow.

Next, at tz for 1 hour, p7 cui No. 3 φ is 11 (1
to 1L”, the N-channel MOS transistor 11
is turned off, 71737777 circuit 2 is activated,
Outputs corresponding to the in-phase output A1 and the anti-phase output AIK7 do/s signals Ext and AI of the address buffer circuit 2 are generated. As shown by the solid line in FIG.
In this case, the reverse phase output of the atto 777777 circuit 2 is 'L
"H" K rises, so the second node N! is discharged to 0■, and the N-channel MOS transistor 11 is turned off.In this case, the first redundant power supply is turned off from time ts to t4. Even if a high voltage vPl of V. or more is applied to the terminal 3, only a small amount of current flows through the fuse 10, so the fuse 10 will not melt.

On the other hand, as shown by the dotted line in FIG.
At time t!, if AI is H'', the opposite-phase output λ1 of the address buffer circuit 2 remains at "L", so the second node N2 is in a floating state, and the N-channel MOS remains in a floating state. Transistor 11 remains on. In this case, time 1. -1. If VPI of a voltage higher than Vee is applied to the first redundant power supply terminal 3 at
．． Since current flows to the fuse 10 through the 'rjL flow path of the N-channel MOS transistor 11, the fuse 10 is blown. Next, at time t1, the fuse blowing cycle is completed when the ay signal Et and the current level rise from L" to H".

[Problem that the invention seeks to solve]

In the conventional dynamic MOS RAM as mentioned above,
In the fuse blowing cycle, as in normal memory operation, complicated timing is required.
Not only is it necessary to apply the 7 dos V signals Ext and AI in synchronization with No. 11 Ext and RAS, but also it is necessary to apply the redundant power supply terminal 3 only during the period when the clock signals Eat and RAS are “L”. There is a restriction that a high voltage Vp+'t' cannot be applied, and there is also a drawback that the time TF required for fuse blowing from time t3 to time t4 can only be defined by the time during which VPI is rising. moreover,
The fuse blowing time Tr is determined at the second node N in FIG.
, there was a problem that it could not be set longer than the time that can hold "H"% (normally the second) -do Nt discharges from "H" to 1L' due to p-n junction leakage). .

The present invention has been made to solve the above-mentioned problem χ, and it is an object of the present invention to provide a semiconductor integrated circuit having a fuse circuit in which the time required for fuse blowing can be arbitrarily set with simple timing.

[Means for solving problems]

In the semiconductor integrated circuit according to the present invention, the fuse circuit is activated immediately after receiving a 7-ton signal from the outside.

[Effect]

The main feature of this invention is that the required fuses are blown by applying the address signal directly to the MY fuse circuit.

〔Example〕

FIG. 1 is a circuit block diagram of a dynamic MO8RAM which is an embodiment of the semiconductor integrated circuit of the present invention.

In the figure, the same reference numerals as in FIG. 10 indicate the same parts, and 1
6 is a fuse circuit according to the present invention. FIG. 2 is a circuit diagram showing the fuse circuit 16 shown in FIG. 1.

In the figure, the same reference numerals as in FIGS. 10 and 11 indicate the same parts.

Next, the operation will be explained using the timing chart of the heat melting cycle shown in FIGS. 3 and 4.

FIG. 3 shows a case where the fuse 10Y does not blow, and the atome signals Ext and At are set to "L'K".

At this time, since the N-channel MOS transistor 11 remains off, the voltage V with a low IQI is applied to the first redundant source terminal 3.
Even if P is applied, almost no current flows through the fuse 10, and the fuse 10 does not break.

FIG. 4 shows the case where the heater 10 is melted down.

At time R, 7 tons wound Ext, At L
When the voltage is raised from "to 1H", the N-channel MOS transistor 11 is turned on and the node N+ of WJl becomes the OV level. Next, when VPI rises at time R2, the fuse 1 ON channel MO is connected to the first redundant power supply terminal 3.
A current flows through the fuse 10 through the current path of the eight transistors 11, and the fuse 10 is blown.

FIG. 5 shows a circuit diagram of a dynamic MOS RAM which is another embodiment of the semiconductor integrated circuit of the present invention.

This is a diagram. In this figure, the same reference numerals as in FIGS. 1 and 10 indicate the same parts.

FIG. 6 is a circuit diagram showing the heating circuit 16 shown in FIG. In the figure, the same reference numerals as in FIGS. 2 and 11 indicate the same parts, and 17 is the second redundant power supply terminal 4.
N-channel MO for photoconverting the second node N2 from
S transistor, whose gate is connected to the atomic signal Ez (A
The drain is connected to the second redundant power supply terminal 4 (/
C-connected, and the source is connected to the second]-domain N2. 18 is a resistor that prevents the second node N2 from being in a floating state, and its resistance value R1
4 is quite large and one end thereof is connected to the second node Nt.

The other end is connected to the ground terminal.

Next, the operation will be explained using the timing chart 7 of the fuse blowing cycle shown in FIGS. 7, 8 and 9.

Figure 7 shows the case of fuse 10ya-not blown? Show, 7
The external signals Ext and AI are set to "L".

At this time, since the N-channel MOS transistor 1T remains off, the second node N is set to Ov by the resistor 18.
is maintained, and N-channel MOS transistor 11 remains off. In this case, even if a high voltage Vp is applied to the first redundant II source terminal 3, only a small amount of current flows through the fuse 10.

Since the water does not flow, the fuse 10 does not blow.

FIG. 8 shows a case where the heats 10Y bath is cut off.

At time S1, the address signal E is changed from L' to H'.
When the voltage is turned on, the N-channel MOS transistor 17 turns on, and the redundant '1 [terminal 4 of g2 is also input.
P! The node N is photovolted to "H". Then, the N-channel MOS transistor 11 is turned on, but
At this time, since VPI is still Ov, no current flows through the fuse 10. Next, if a high voltage VPI is applied to the first redundant power supply terminal 3 between 118 S and ~S, the first redundant power supply terminal 3 connects the fuse 10, N
A current flows through the fuse 10 through the current path of the channel MOS transistor 11, and the fuse 10 is blown.

In this case, the second node N2 is low impedance and H
Since it is connected to v8 of ', the time required to blow the fuse is T.
rt can be set to any time without being limited by the pn junction leakage of the second node N2.

Figure 9 shows the other four cases when fuse 10 is blown.
Even if a crystalline voltage VPI is applied to the first redundant power supply terminal 3 at time ul, the address signal Ext,
AI mold L" so N channel MOS transistor I
T is off, the second node N2 is held at O■ by the resistor 18, and the N-channel MOS transistor 1
1 is off. For this reason, in Shi-zu 10,
No current flows yet.

Next, time U! In the address signal Ext, AI
When the voltage changes from “L” to “H”, the N-channel MOS transistor 17 is turned on (the second one is turned on by the VPI input from the second redundant power supply terminal 4).
is charged to. And N-channel MOS transistor 11y! - Since it is turned on, the first redundant 1! Source terminal 3
More Hughes 10. N thousand Yanel MO8) Runnstar 11
In the current path of t, the current passes through heats 10 &l and heats 1
0 is fused. At time u3, address signal Ex
When t, AI goes from 1H" to 1L", N channel MC
) The S transistor 17 is turned off, and the second node Nt is discharged from "H" to QV via the resistor 18. Atl/X signal +jExt, while holding A+ or 1H'', the second node N has a V of 9H'' with a low impedance.
Since it is connected to p- of the second node N, the fuse melting time Tr is connected to p- of the second node N, as in the case of FIG.
By n-junction leak? (You can set it at the time of your appointment.)

In addition, as can be seen by comparing the Whs diagram and Figure 9, the required time for fusing the heats TF can be set not only by the VPI time but also by the 7 do/s signal Ext and AI times, increasing the degree of freedom in timing setting. .

In the above embodiment, a dynamic MO8RAM using an N-channel MOS transistor was described, but a P-channel MOS transistor and a CMO
The same applies to the case where 3'l' is used, and it goes without saying that the dynamic MO8RAMKX can also be applied to semiconductor memories such as static RAM and ROM with a power fuse circuit.

〔Effect of the invention〕

As explained above, this invention has a structure in which the fuse circuit is operated directly by an address signal from the outside, so that the fuse can be blown by simply applying an external Atomes signal, and therefore the required time for fusing the fuse can be set arbitrarily. It can be set easily and has the effect of being able to reliably melt the heat at a simple timing.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a dynamic MO8RAM which is an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a circuit diagram showing the fuse circuit shown in FIG. 1, and FIGS. 5 is a circuit block diagram of a dynamic MO8RAM which is another embodiment of the semiconductor integrated circuit of the present invention, and FIG. 6 is a fuse circuit shown in FIG. 5. Figures 7, 8 and 9 are timing diagrams of the fusing cycle in the heating circuit shown in Figure 6, Figure 10 is a circuit block diagram of a conventional dynamic MOSRAM, and Figure 11 is is a circuit diagram of the heater circuit shown in FIG. 1(), and FIG. 12 is a timing diagram of the heater fusing cycle shown in FIG. In the figure, 1 is an atto Vs input terminal, 2 is an atons buffer 7 circuit, 3 is a first redundant power supply terminal, 4 is a second redundant source terminal, and 5 is a clock terminal. 6 is a ττ single cover 777 circuit, 8 is a decoder circuit, 9 is a power supply terminal, 10 is a heat supply, 11 is an N-channel MOS)
16 is a fuse circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Yoshinori Oiwa (2 others) Fig. 1 Xk, c - Fig. 2 1---------------7J Fig. 3 Ext, Ai □□ Fig. 4 Fig. 5 6 Figure 7 Vρ2□ ExLAi□□ N2□ Figure 8 5152 S3 Sz Figure 9 tJ+ u2 t, I] tJ4
Figure 10 Figure 11 Figure 12 jl t2 tl
j= tS procedural amendment (voluntary) 6] 34 Showa month F-1 1. Indication of case Patent application 1986-25105143'
26 Title of the invention ¥4-body integrated circuit 3, Relationship to the amended person case Patent applicant address 2-2 Marunouchi, Chiyoda-ku, Tokyo; 3 Name (601) Mitsubishi Electric Corporation Representative Mamoru Shiki Ya46th generation 1ri person 5 Subject of addition Akira, l1il+, ': of the invention of #, 4+1 explanation column and drawing 6, contents of addition (1) Specification 11: Lines 3 to 4 of page 1O "Redundant power supply terminal 3" is corrected to "first redundant power supply terminal 3." (2) Correct [)-do N+ J on line 7 of page 14 to "second node N2 J." (3) Correct Figures 2, 6, and 10 as shown in the attached sheet. Figure 6 (Figure 6)

Claims (3)

[Claims] (1) It has a memory cell that stores information, a redundant memory cell, a fuse for replacing the memory cell and the redundant memory cell, and a fuse circuit that electrically blows out the fuse, A semiconductor integrated circuit, wherein the memory cell is selected by an external address signal, and the fuse circuit is directly activated by an external address signal. (2) The fuse circuit includes a fuse whose one end is connected to a first redundant power supply terminal and whose other end is connected to a first node, a gate to which an external address signal is applied, and a drain connected to the first redundant power supply terminal. The semiconductor integrated circuit according to claim 1, characterized in that the semiconductor integrated circuit comprises a MOS transistor whose source is connected to a ground terminal. (3) The fuse circuit includes a fuse whose one end is connected to a first redundant power supply terminal and the other end is connected to a first node, a gate to which an external address signal is applied, and a drain to a second redundant power supply terminal. a first MOS transistor connected to a power supply terminal and having a source connected to a second node; a first MOS transistor having a gate connected to the second node; a drain connected to the first node; and a source connected to the ground terminal. and a resistor having one end connected to the second node and the other end connected to the ground terminal. ) The semiconductor integrated circuit described in item 2.