JPS62111872U

JPS62111872U -

Info

Publication number: JPS62111872U
Application number: JP23986U
Authority: JP
Priority date: 1986-01-06
Filing date: 1986-01-06
Publication date: 1987-07-16

Description

[Brief explanation of the drawing]

第１図ａは本考案の１実施例に係るメモリカー
ドの平面図、第１図ｂは第１図ａの側面図、第１
図ｃは第１図ａのメモリカードに対して切欠き位
置が異なる場合の本考案の実施例の平面図、第２
図ａは装置本体側接続部の平面図、第２図ｂは第
２図ａの接続部に対してピン位置が異なる場合の
装置本体側接続部の平面図、第３図は正常嵌合状
態における本考案のメモリカードの平面図、第４
図および第５図はそれぞれ誤実装時におけるメモ
リカードの平面図である。１，１′…メモリカード、２…基板、３，３′
…フレーム、４…接続接栓、５，５′…切欠き部
、６，６′…装置本体側接続部、７…接栓受口、
８，８′…ピン。 FIG. 1a is a plan view of a memory card according to an embodiment of the present invention, FIG. 1b is a side view of FIG. 1a, and FIG.
Figure c is a plan view of an embodiment of the present invention in which the notch position is different from that of the memory card in Figure 1a;
Figure a is a plan view of the connecting part on the device main body side, Figure 2 b is a plan view of the connecting part on the device main body side when the pin position is different from the connecting part in Figure 2 a, and Figure 3 is a normal mating state. 4th plan view of the memory card of the present invention in
FIG. 5 is a plan view of the memory card when it is incorrectly mounted. 1, 1'... Memory card, 2... Board, 3, 3'
... Frame, 4... Connection plug, 5, 5'... Notch, 6, 6'... Device main body side connection part, 7... Connection socket,
8, 8'...pin.

Claims

[Scope of utility model registration request]

A memory circuit having a plurality of memory elements and their peripheral circuits is formed on a substrate, a connection plug is provided on the substrate in which a read/write data bus with the memory elements and a control signal line of the peripheral circuit are arranged, and the 1. A memory card in which a board is packaged by surrounding it in a pack case, characterized in that the pack case is provided with a locking means for preventing erroneous insertion into an apparatus main body.