JPS6211157Y2 - - Google Patents
Info
- Publication number
- JPS6211157Y2 JPS6211157Y2 JP1979164234U JP16423479U JPS6211157Y2 JP S6211157 Y2 JPS6211157 Y2 JP S6211157Y2 JP 1979164234 U JP1979164234 U JP 1979164234U JP 16423479 U JP16423479 U JP 16423479U JP S6211157 Y2 JPS6211157 Y2 JP S6211157Y2
- Authority
- JP
- Japan
- Prior art keywords
- coil
- reset
- pulse
- power supply
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005856 abnormality Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000003086 colorant Substances 0.000 claims description 2
- 230000002441 reversible effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 2
- 244000145845 chattering Species 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Landscapes
- Emergency Alarm Devices (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
【考案の詳細な説明】
本考案は電源電圧の異常を表示する装置、例え
ば半導体メモリシステム用バツクアツプ電源等の
電圧異常時、特に電圧低下を表示する装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for indicating an abnormality in power supply voltage, for example, an apparatus for indicating a voltage drop in an abnormal voltage such as a backup power supply for a semiconductor memory system.
一般に、IC（集積回路）を用いた半導体メモ
リ装置には数多くの電源が用いられていることは
周知である。そして、これらの電源の他に、停
電、電源装置の故障発生時の対策として、通常の
電源に異常が発生した時瞬時に切換わるバツクア
ツプ電源と呼ばれるバツテリー電源（一次又は二
次電池）が用意されているのが普通である。 It is generally known that a large number of power supplies are used in semiconductor memory devices using ICs (integrated circuits). In addition to these power sources, as a countermeasure in the event of a power outage or failure of the power supply, a battery power source (primary or secondary battery) called a backup power source is prepared, which can be switched instantly when an abnormality occurs in the regular power source. It is normal to have
しかし、このバツクアツプ電源においても、長
時間使用あるいは自己放電作用により電圧が徐々
に低下し、第１図に示すように、半導体メモリ装
置のデータ保持可能な閾値電圧Ｖs以下になると
電源として利用し得なくなる。したがつて、バツ
クアツプ電源の電圧も監視する必要があり、電圧
に異常が発生した場合これを知らせる装置が必要
である。 However, even with this backup power supply, the voltage gradually decreases due to long-term use or self-discharge, and as shown in Figure 1, when it falls below the threshold voltage V s at which the semiconductor memory device can retain data, it cannot be used as a power supply. You won't get any more. Therefore, it is necessary to monitor the voltage of the backup power supply, and a device is required to notify when an abnormality occurs in the voltage.
この種の異常表示装置としては、電子ブザー、
発光ダイオード等による警報表示装置が考えられ
るが、このような装置は消費電力が大きく電圧降
下が起こつている間も表示用の電力を消費するの
でバツクアツプ電源電圧の低下を促進してしまい
最適とは言えない。 This type of abnormality display device includes an electronic buzzer,
An alarm display device using a light emitting diode or the like may be considered, but such a device consumes a large amount of power and consumes power for displaying even when a voltage drop occurs, which promotes a drop in the backup power supply voltage and is not optimal. I can not say.
このことから本考案は一旦表示動作を行なえば
以後の表示保持のための電力消費を必要としない
ようにした低消費電力型の電源電圧異常表示装置
を提供しようとするものである。 Therefore, it is an object of the present invention to provide a low power consumption power supply voltage abnormality display device that does not require power consumption for subsequent display maintenance once a display operation is performed.
本考案は、セツトコイル及びリセツトコイルが
巻回された略Ｕ字形磁心の磁極間に表裏に異なる
色等を付した永久磁石による円板を面方向に180
゜反転可能に配設して成る表示素子と、電源電圧
を基準電圧と比較するコンパレータと、該コンパ
レータの出力信号に応じてセツトパルス、リセツ
トパルスを発生してそれぞれ、前記セツトコイ
ル、リセツトコイルに送出するＣ−MOS回路で
構成されたパルス発生回路とを含み、しかも前記
セツトコイル及びリセツトコイルに並列に比較的
大容量のコンデンサを接続して、前記セツトパル
スあるいはリセツトパルス送出時該コンデンサか
らの放電電流も重畳して供給されるようにしたこ
とを特徴とする電源電圧異常表示装置である。 In the present invention, a disk made of permanent magnets with different colors on the front and back is placed between the magnetic poles of a substantially U-shaped magnetic core around which a set coil and a reset coil are wound.
゜A display element arranged to be reversible, a comparator for comparing the power supply voltage with a reference voltage, and generating a set pulse and a reset pulse according to the output signal of the comparator and sending them to the set coil and reset coil, respectively. It includes a pulse generation circuit constituted by a C-MOS circuit, and furthermore, a capacitor of relatively large capacity is connected in parallel to the set coil and reset coil, so that when the set pulse or reset pulse is sent out, the discharge current from the capacitor is also superimposed. This is a power supply voltage abnormality display device characterized in that the power supply voltage abnormality display device is supplied with
以下に本考案の実施例を説明する。 Examples of the present invention will be described below.
第２図及び第３図はそれぞれ本考案に用いる表
示素子の概略図を状態別に示す。 FIGS. 2 and 3 each show schematic diagrams of display elements used in the present invention in different states.
図において、この表示素子１は、磁性材による
略Ｕ字形磁心２にコイル３を巻回しこの中間部か
らタツプ端子C0を引出して、端子Ｓe−Ｃp間をセ
ツトコイル、端子Ｒe−Ｃp間をリセツトコイルと
してそれぞれ構成するようになし、磁心２の両磁
極間には、これらのコイルによつて形成される磁
極の極性に応じて面方向に180゜の反転回動可能
なように、永久磁石による円板４を配設して成
る。円板４は磁心２の両磁極を結ぶ線分に直角な
回転軸５に磁極軸が直角に交差するよう軸支され
ている。 In the figure, this display element 1 is constructed by winding a coil 3 around a substantially U-shaped magnetic core 2 made of magnetic material, pulling out a tap terminal C0 from the intermediate part, and connecting the set coil and terminals R e -C between terminals S e and C p . between the two are configured as reset coils, and between the two magnetic poles of the magnetic core 2, there is a coil that can be rotated 180 degrees in the plane direction depending on the polarity of the magnetic poles formed by these coils. , a disk 4 made of a permanent magnet is arranged. The disk 4 is pivotally supported by a rotating shaft 5 which is perpendicular to a line connecting both magnetic poles of the magnetic core 2 so that the magnetic pole axis intersects at a right angle.
この表示素子は、例えば第２図のように、端子
Ｓe−Ｃp間、すなわちセツトコイル３ａにパルス
電流i1を供給すると、磁心２に形成されたＮ極と
円板４のＳ極が、Ｓ極と円板４のＮ極がそれぞれ
最短距離で吸引し合う位置まで回転して円板４の
一方の面が図中上方に表示される。この後、電流
供給が無くても磁心２の磁極の残留磁化により円
板４の一方の面の表示が保持される。一方、第３
図に示すように、端子Ｒe−Ｃp間、すなわちリセ
ツトコイル３ｂにパルス電流i1と逆向きのパルス
電流i2を供給すると、磁心２の磁極が逆になり、
これによつて円板４が180゜回転して円板４の他
方の面が表示される。ここで、円板４のそれぞれ
の面には、異なる彩色あるいは文字等を付してセ
ツト、リセツトの識別ができるようにしてあり、
このような表示素子は市販されている。 In this display element, for example, as shown in FIG. 2, when a pulse current i1 is supplied between the terminals S e and C p , that is, to the set coil 3a, the N pole formed in the magnetic core 2 and the S pole of the disk 4 are The S pole and the N pole of the disk 4 are rotated to a position where they attract each other at the shortest distance, and one surface of the disk 4 is displayed at the top in the figure. Thereafter, the display on one side of the disk 4 is maintained due to the residual magnetization of the magnetic poles of the magnetic core 2 even if no current is supplied. On the other hand, the third
As shown in the figure, when a pulse current i 2 in the opposite direction to the pulse current i 1 is supplied between terminals R e and C p , that is, to the reset coil 3b, the magnetic pole of the magnetic core 2 is reversed.
This causes the disk 4 to rotate 180 degrees and the other side of the disk 4 to be displayed. Here, each surface of the disc 4 is painted in a different color or has letters, etc., so that it can be identified as set or reset.
Such display elements are commercially available.
第４図は電源電圧の低下を検知してパルス電流
を発生することにより前述の如き表示素子を駆動
する本考案の一実施例の回路図であり、前述した
システム電源の停電時に電源供給を行なうバツク
アツプ電源ＶBの電圧異常を表示する場合につい
て説明する。 FIG. 4 is a circuit diagram of an embodiment of the present invention which drives the above-mentioned display element by detecting a drop in the power supply voltage and generating a pulse current, and supplies power during the above-mentioned system power outage. The case of displaying a voltage abnormality of the backup power supply VB will be explained.
第４図において、Q1〜Q8はＣ−MOS回路で構
成されたNAND論理素子、COPは電源ＶBの電圧
と基準電圧とを比較するコンパレータ、３ａ，３
ｂはそれぞれ、第２図におけるセツトコイル、リ
セツトコイルである。 In FIG. 4, Q 1 to Q 8 are NAND logic elements composed of C-MOS circuits, COP is a comparator that compares the voltage of the power supply V B and the reference voltage, 3a, 3
b are the set coil and reset coil in FIG. 2, respectively.
コンパレータCOPは電源ＶBの電圧と、抵抗
R1，R2，R3により設定された基準電圧とを比較
し、電源ＶBの電圧が第１図のように、例えば
3.6Vから閾値電圧Ｖs（3.0V）まで低下すると出
力が例えばハイレベルに変化する。この出力変化
で論理素子Q1，Q2，Q3抵抗R5及びコンデンサC1
により、2ms程度の高速パルス信号が発生され、
エミツタホロワ構成のトランジスタTr1のベース
端子に供給される。これによつてトランジスタ
Tr1が導通すると抵抗R8に電源ＶBからの電流が
流れて次段のエミツタホロワ構成のトランジスタ
Tr2も導通状態となりセツトコイル３ａに電流が
供給される。これによつて、表示素子においては
電源ＶBの電圧“異常”を表示する。セツトコイ
ル３ａへの電流供給は非常に短時間であるが、一
旦駆動された表示素子の円板は前述したような保
持機能により表示が維持されるので表示保持のた
めの電力を必要としない。 The comparator COP is the voltage of the power supply V B and the resistance
By comparing the reference voltages set by R 1 , R 2 , and R 3 , the voltage of power supply V B is determined as shown in Fig. 1, for example.
When the voltage drops from 3.6V to the threshold voltage V s (3.0V), the output changes to, for example, a high level. With this output change, logic elements Q 1 , Q 2 , Q 3 , resistor R 5 and capacitor C 1
A high-speed pulse signal of about 2ms is generated,
It is supplied to the base terminal of the transistor Tr1 having an emitter follower configuration. This results in a transistor
When Tr 1 becomes conductive, current from the power supply V B flows through resistor R 8 and the emitter follower configuration transistor in the next stage flows.
Tr 2 also becomes conductive and current is supplied to the set coil 3a. As a result, the display element indicates that the voltage of the power supply V B is "abnormal". Although the current is supplied to the set coil 3a for a very short period of time, once the disk of the display element is driven, the display is maintained by the above-mentioned holding function, so no power is required to maintain the display.
ところで、本考案ではセツトコイル３ａ、リセ
ツトコイル３ｂに並列に比較的大容量（100〜200
μＦ）のコンデンサＣpを接続しており、セツト
コイル３ａ、あるいはリセツトコイル３ｂに電流
が供給される時コンデンサＣpの放電電流が重畳
されるようにしている。勿論、この放電電流は表
示素子を駆動するのに十分な値であり、電源ＶB
からの電流供給が非常に短かいことと合せて、表
示素子駆動のための消費電力を最小限にとどめる
ことができ、しかも表示保持のための電力を要し
ないので、従来の電源ＶBの電圧降下を促進する
という欠点を解消できる。 By the way, in the present invention, a relatively large capacity (100 to 200
A capacitor C p of .mu.F) is connected so that when a current is supplied to the set coil 3a or the reset coil 3b, the discharge current of the capacitor C p is superimposed. Of course, this discharge current is sufficient to drive the display element, and the power supply V B
In addition to the fact that the current supply from The disadvantage of accelerating descent can be overcome.
一方、電源ＶBの電圧が正常になると、コンパ
レータCOPの出力が変化して論理素子Q1，Q5，
Q6抵抗R6、コンデンサC2により高速パルスが発
生され、エミツタホロワ構成のトランジスタ
Tr3，Tr4が導通してリセツトコイル３ｂに電流
が供給されることにより、表示素子は円板が反転
されて“正常”の表示を行なう。 On the other hand, when the voltage of the power supply V B becomes normal, the output of the comparator COP changes and the logic elements Q 1 , Q 5 ,
A high-speed pulse is generated by the Q 6 resistor R 6 and the capacitor C 2 , and the emitter follower configuration transistor
When Tr 3 and Tr 4 are made conductive and a current is supplied to the reset coil 3b, the disk of the display element is reversed and a "normal" display is performed.
なお、コンパレータCOPとしてヒステリシス
特性を持つものを選定すれば、第５図に示すよう
に、セツト時及びリセツト時の検出電圧に差を持
たせることができ、表示素子のチヤタリングを無
くすことができる。 If a comparator COP having hysteresis characteristics is selected, as shown in FIG. 5, it is possible to provide a difference in the detected voltages at the time of setting and resetting, and it is possible to eliminate chattering of the display element.
以上説明してきたように、本考案は高速パルス
で駆動される表示保持機能を有する表示素子及び
電圧低下時このパルスを発生する駆動回路を用い
た装置であり、表示を行なう時の消費電力は非常
に小さく、電源の電圧降下を促進するようなこと
が無いので、例えば半導体メモリ装置のバツクア
ツプ電源の電圧異常表示装置として最適である。 As explained above, the present invention is a device that uses a display element that has a display holding function that is driven by high-speed pulses and a drive circuit that generates this pulse when the voltage drops, and the power consumption when displaying is extremely low. Since it is small in size and does not promote a voltage drop in the power supply, it is ideal as a voltage abnormality display device for a backup power supply of a semiconductor memory device, for example.
第１図は電源装置の電圧変化を示した図、第２
図及び第３図はそれぞれ、本考案に使用される表
示素子の概略図を状態別に示した図、第４図はこ
の表示素子を駆動するための本考案による駆動回
路、第５図は電源電圧に対するセツト、リセツト
の関係を示した図である。
図中、１は表示素子、２は磁心、３はコイル、
３ａはセツトコイル、３ｂはリセツトコイル、４
は円板、５は回転軸、COPはコンパレータ、Q1
〜Q8はNAND論理素子。
Figure 1 is a diagram showing the voltage change of the power supply device, Figure 2
3 and 3 are schematic diagrams showing the display element used in the present invention according to its state, FIG. 4 is a drive circuit according to the present invention for driving this display element, and FIG. 5 is a power supply voltage. FIG. 3 is a diagram showing the relationship between setting and resetting. In the figure, 1 is a display element, 2 is a magnetic core, 3 is a coil,
3a is a set coil, 3b is a reset coil, 4
is a disk, 5 is a rotation axis, COP is a comparator, Q 1
~ Q8 is a NAND logic element.
Claims (1)
略Ｕ字形磁心の磁極間に表裏に異なる色等を付し
た永久磁石による円板を面方向に180゜反転可能
に配設して成る表示素子と、電源電圧を基準電圧
と比較するコンパレータと、該コンパレータの出
力信号に応じてセツトパルス、リセツトパルスを
発生してそれぞれ、前記セツトコイル、リセツト
コイルに送出するＣ−MOS回路で構成されたパ
ルス発生回路とを含み、しかも前記セツトコイル
及びリセツトコイルに並列に比較的大容量のコン
デンサを接続して、前記セツトパルスあるいはリ
セツトパルス送出時該コンデンサからの放電電流
も重畳して供給されるようにしたことを特徴とす
る電源電圧異常表示装置。 A display element consisting of a disk made of permanent magnets with different colors on the front and back arranged so as to be reversible by 180 degrees in the plane direction between the magnetic poles of a substantially U-shaped magnetic core around which a set coil and a reset coil are wound, and a power supply voltage a comparator for comparing the output signal with a reference voltage, and a pulse generation circuit configured with a C-MOS circuit that generates a set pulse and a reset pulse according to the output signal of the comparator and sends them to the set coil and the reset coil, respectively, Moreover, a relatively large capacity capacitor is connected in parallel to the set coil and the reset coil, so that when the set pulse or the reset pulse is sent out, the discharge current from the capacitor is also supplied in a superimposed manner. Abnormality display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979164234U JPS6211157Y2 (en) | 1979-11-29 | 1979-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1979164234U JPS6211157Y2 (en) | 1979-11-29 | 1979-11-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5683938U JPS5683938U (en) | 1981-07-06 |
| JPS6211157Y2 true JPS6211157Y2 (en) | 1987-03-16 |
Family
ID=29675189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1979164234U Expired JPS6211157Y2 (en) | 1979-11-29 | 1979-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6211157Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5347980U (en) * | 1976-09-22 | 1978-04-22 |
-
1979
- 1979-11-29 JP JP1979164234U patent/JPS6211157Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5347980U (en) * | 1976-09-22 | 1978-04-22 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5683938U (en) | 1981-07-06 |
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