JPS62109297A - Peak value holding circuit - Google Patents

Peak value holding circuit

Info

Publication number
JPS62109297A
JPS62109297A JP60249346A JP24934685A JPS62109297A JP S62109297 A JPS62109297 A JP S62109297A JP 60249346 A JP60249346 A JP 60249346A JP 24934685 A JP24934685 A JP 24934685A JP S62109297 A JPS62109297 A JP S62109297A
Authority
JP
Japan
Prior art keywords
voltage
capacitor
analog input
peak value
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60249346A
Other languages
Japanese (ja)
Inventor
Tsuneo Fujita
藤田 常雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60249346A priority Critical patent/JPS62109297A/en
Publication of JPS62109297A publication Critical patent/JPS62109297A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To hold a peak value following steadily to the change at high speed of an analog input voltage by opening/closing the charging current of a capacitor based on a result in which a size between the analog input voltage and a voltage held by the capacitor is compared. CONSTITUTION:Since a switch 2 is accompanied by an equivalent series resis tance 5, a time constant circuit is constituted with the equivalent series resis tance 5 and a voltage holding capacitor 1, and a voltage V1 held by the voltage holding capacitor 1 follows the change of an analog input voltage Vx delaying by time decided at the time constant circuit. When the input voltage Vx reaches its peak value Vxp and the input voltage Vx coincides with the voltage V1 held by the voltage holding capacitor 1, a potential difference generated at both ends of the equivalent series resistance 5 becomes zero, and the output of a comparator 4 is inverted, thereby becoming a low level. Thereby, the switch 2 is placed in an open state, and an input terminal 10 and the voltage holding capacitor 1 are separated, and the voltage holding capacitor 1 holds the voltage almost equivalent to the value of the peak value Vxp of the analog input voltage Vx.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はコンデンサを利用したピーク値保持回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak value holding circuit using a capacitor.

〔概要〕〔overview〕

本発明は、コンデンサにアナログ信号のピーク値を保持
させるピーク値保持回路において、アナログ入力電圧と
このコンデンサが保持している電圧との大小を比較した
結果に基づいて、コンデンサの充電電流を開閉すること
により、アナログ入力電圧の高速変化に確実に追従して
ピーク値を保持できるピーク値保持回路をモノリシック
集積回路で実現できるようにしたものである。
The present invention has a peak value holding circuit that causes a capacitor to hold the peak value of an analog signal, and opens and closes the charging current of the capacitor based on the result of comparing the analog input voltage with the voltage held by the capacitor. This makes it possible to realize a peak value holding circuit that can reliably follow high-speed changes in analog input voltage and hold the peak value using a monolithic integrated circuit.

〔従来の技術〕[Conventional technology]

コンデンサと増幅器を用いた従来例ピーク値保持回路で
は、アナログ入力電圧を整流する増幅器を介してコンデ
ンサを充電し、コンデンサが保持している電圧よりもア
ナログ入力電圧の方が低い場合には増幅器の整流作用で
回路が導通せず、コンデンサは保持電圧を保持し続ける
。一方、コンデンサが保持している電圧よりもアナログ
入力電圧の方が高い場合には、増幅器の整流作用で回路
が導通して、コンデンサをアナログ入力電圧まで充電し
、これまでに印加されたアナログ入力電圧値の最大値を
コンデンサに保持する。
In a conventional peak value holding circuit using a capacitor and an amplifier, the capacitor is charged via an amplifier that rectifies the analog input voltage, and if the analog input voltage is lower than the voltage held by the capacitor, the amplifier is The rectification action prevents the circuit from conducting, and the capacitor continues to maintain the holding voltage. On the other hand, if the analog input voltage is higher than the voltage held by the capacitor, the circuit conducts due to the rectifying action of the amplifier, charging the capacitor up to the analog input voltage and reducing the voltage at the analog input applied so far. The maximum voltage value is held in the capacitor.

コンデンサと増幅器を用いた従来例ピーク値保持回路を
第4図に示す。この回路は電圧保持コンデンサ11と、
増幅器13および14と、整流器15および16と、ア
ナログ入力電圧VXの入力端子10と、ピーク値電圧■
2の出力端子20とを備える。ここで、増幅器13およ
び14はそれぞれ利得1の非反転増幅回路であり、増幅
器14の出力は増幅器13の反転入力端子にも接続され
る。まず、入力端子10にアナログ入力電圧VXが印加
されると、増幅器13の出力電圧■2はvXに等しくな
る。このときに増幅器13の出力電圧■2の値が電圧保
持コンデンサ11が保持している電圧■、より高い場合
には、整流器16が導通して電圧保持コンデンサ11は
さらに充電される。ところが、整流器16を介しての充
電であるので、電圧保持コンデンサ11の電圧は増幅器
13の出力電圧■2より整流器の闇値電圧■7だけ低い
値すなわち(Vz  Vt)までしか充電されない。と
ころで、増幅器13の出力電圧V2はアナログ入力電圧
■8に等しくかつ増幅器14の出力電圧Vpは■1に等
しくなるので、増幅器14の出力電圧■、は(■、 V
t)となる。一方、増幅器14の出力は増幅器13の反
転入力端子に帰還されているので、増幅器13の反転入
力端子の印加電圧は増幅器14の出力電圧V、すなわち
(V−Vt)になる。増幅器13の非反転入力端子の印
加電圧はアナログ入力電圧■8であるので、増幅器13
の反転入力端子と非反転入力端子への印加電圧は不平衡
状態になり、印加電圧の差は■アになる。したがって、
増幅器13は反転入力端子と非反転入力端子への印加電
圧の差で出力電圧が変化する。増幅器13の出力電圧の
変化は増幅器14を介して増幅器13の反転入力端子に
帰還される。増幅器13の反転入力端子に印加される電
圧がアナログ入力電圧v、Iに等しくなったときに平衡
状態になり、増幅器13の出力電圧の変化は止まる。最
終的に増幅器13の出力電圧■2の値は(v、+vT)
により、電圧保持コンデンサ11の保持電圧V1の値は
V、lになってアナログ入力電圧に等しくなる。したが
って、アナログ入力電圧VXの最大値をVXpとすると
、電圧保持コンデンサ11の保持電圧■1はXX、まで
上昇し、増幅器14の出力電圧■、もVXpまで上昇す
る。このときの増幅器13の出力電圧■2は増幅器14
からの帰還作用によって(VXp+V、) となってい
る。次に、アナログ入力電圧■8が最大値VX9より低
くなると、増幅器13の出力電圧V2が(Vxp”VT
 )より低くなって、整流器16は逆バイアス状態にな
り非導通になる。したがって、入力端子の変化は電圧保
持コンデンサ11には伝わらず、電圧保持コンデンサは
アナログ入力電圧■、の最大値■X、の値を保持し続け
る。ここで、整流器15はアナログ入力端子■8が負に
なったときに増幅器13の出力が負側に振れないように
クランプされる。
A conventional peak value holding circuit using a capacitor and an amplifier is shown in FIG. This circuit includes a voltage holding capacitor 11,
Amplifiers 13 and 14, rectifiers 15 and 16, input terminal 10 of analog input voltage VX, and peak value voltage ■
2 output terminals 20. Here, amplifiers 13 and 14 are each non-inverting amplifier circuits with a gain of 1, and the output of amplifier 14 is also connected to the inverting input terminal of amplifier 13. First, when analog input voltage VX is applied to input terminal 10, output voltage 2 of amplifier 13 becomes equal to vX. At this time, if the value of the output voltage (2) of the amplifier 13 is higher than the voltage (2) held by the voltage holding capacitor 11, the rectifier 16 becomes conductive and the voltage holding capacitor 11 is further charged. However, since charging is performed via the rectifier 16, the voltage of the voltage holding capacitor 11 is charged only to a value lower than the output voltage (2) of the amplifier 13 by the dark value voltage (2) of the rectifier, that is, (Vz Vt). By the way, the output voltage V2 of the amplifier 13 is equal to the analog input voltage ■8, and the output voltage Vp of the amplifier 14 is equal to ■1, so the output voltage ■, of the amplifier 14 is (■, V
t). On the other hand, since the output of the amplifier 14 is fed back to the inverting input terminal of the amplifier 13, the voltage applied to the inverting input terminal of the amplifier 13 becomes the output voltage V of the amplifier 14, that is, (V-Vt). Since the voltage applied to the non-inverting input terminal of the amplifier 13 is the analog input voltage ■8, the amplifier 13
The voltages applied to the inverting input terminal and the non-inverting input terminal of are in an unbalanced state, and the difference in the applied voltages becomes ■A. therefore,
The output voltage of the amplifier 13 changes depending on the difference in voltage applied to the inverting input terminal and the non-inverting input terminal. Changes in the output voltage of amplifier 13 are fed back to the inverting input terminal of amplifier 13 via amplifier 14 . When the voltage applied to the inverting input terminal of the amplifier 13 becomes equal to the analog input voltage v, I, an equilibrium state is reached and the output voltage of the amplifier 13 stops changing. Finally, the value of the output voltage ■2 of the amplifier 13 is (v, +vT)
Therefore, the value of the voltage V1 held by the voltage holding capacitor 11 becomes V,l, which is equal to the analog input voltage. Therefore, if the maximum value of the analog input voltage VX is VXp, the voltage held by the voltage holding capacitor 11 (1) increases to XX, and the output voltage (2) of the amplifier 14 also increases to VXp. At this time, the output voltage ■2 of the amplifier 13 is
(VXp+V,) due to the feedback action from. Next, when the analog input voltage ■8 becomes lower than the maximum value VX9, the output voltage V2 of the amplifier 13 becomes (Vxp”VT
), the rectifier 16 becomes reverse biased and non-conducting. Therefore, the change in the input terminal is not transmitted to the voltage holding capacitor 11, and the voltage holding capacitor continues to hold the maximum value of the analog input voltage, ■X. Here, the rectifier 15 is clamped so that the output of the amplifier 13 does not swing to the negative side when the analog input terminal 8 becomes negative.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このような従来例ピーク値保持回路では、増幅器14の
出力を増幅器13に帰還することで整流器16の閾値電
圧■アの補正を行っているので、アナログ入力電圧が変
化してから最終的な平衡状態になるまでには増幅器13
の出力が変化して整流器16を介して電圧保持コンデン
サ11の充電が行われ、さらに増幅器14の出力が変化
し、増幅器14の出力が増幅器13の入力に帰還されて
増幅器13の出方がさらに変化するという帰還動作をく
りがえす。したがって、アナログ入力の周波数が高くな
って電圧の変化が速くなると帰還動作はそれだけ高速動
作が必要になり、増幅器13および増幅器14に高速増
幅器を用いることが必要になる。アナログ入力の周波数
が高くなって電圧の変化が速くなったときに増幅器の動
作速度が十分でなく、アナログ入力の変化に帰還動作が
追従できな(なったときの各部の動作波形を第5図に示
す。アナログ入力端子VXの変化が速く、帰還動作がア
ナログ入力の変化に追従できないので、電圧保持コンデ
ンサ11の保持する電圧■、および増幅器14の出力電
圧Vpはアナログ電圧■8のピーク値■X9に達するこ
とができずに第5図に示すような誤差を生ずる。すなわ
ち、従来のピーク値保持回路ではアナログ入力の周波数
が高くなって電圧の変化が速くなったときには、誤差の
発生を防ぐために高速の増幅器を必要とし、このような
増幅器の回路は複雑であり、ピーク値保持回路をモノリ
シック集積回路化する場合にチップ面積および消費電力
の増大を招く欠点があった。
In such a conventional peak value holding circuit, the threshold voltage (a) of the rectifier 16 is corrected by feeding back the output of the amplifier 14 to the amplifier 13, so the final balance is adjusted after the analog input voltage changes. By the time the state is reached, the amplifier 13
The output of the amplifier 14 changes, and the voltage holding capacitor 11 is charged via the rectifier 16, and the output of the amplifier 14 changes, and the output of the amplifier 14 is fed back to the input of the amplifier 13, so that the output of the amplifier 13 is further changed. Repeat the feedback action of change. Therefore, as the frequency of the analog input becomes higher and the voltage changes faster, the feedback operation needs to operate at a higher speed, and it becomes necessary to use high-speed amplifiers for the amplifiers 13 and 14. When the frequency of the analog input increases and the voltage changes quickly, the operating speed of the amplifier is insufficient and the feedback operation cannot follow the changes in the analog input. Since the analog input terminal VX changes quickly and the feedback operation cannot follow the changes in the analog input, the voltage held by the voltage holding capacitor 11 and the output voltage Vp of the amplifier 14 are the peak value of the analog voltage 8. X9 cannot be reached, resulting in an error as shown in Figure 5.In other words, in the conventional peak value holding circuit, when the analog input frequency becomes high and the voltage changes quickly, it is difficult to prevent the error from occurring. The circuit of such an amplifier is complicated, and when the peak value holding circuit is integrated into a monolithic circuit, the chip area and power consumption increase.

本発明は、このような欠点を除去するもので、整流器を
伴った増幅回路を用いることになく、したがって帰還回
路が簡単でしかもMOS)ランジスタ構造だけで構成さ
れたモノリシック集積回路化に適した高速で動作可能な
ピーク値保持回路を提供することを目的とする。
The present invention eliminates these drawbacks, does not use an amplifier circuit with a rectifier, has a simple feedback circuit, and is suitable for high-speed monolithic integration consisting only of MOS transistor structures. The purpose of the present invention is to provide a peak value holding circuit that can operate at

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、アナログ信号を入力する端子と、このアナロ
グ信号の電圧ピーク値の相当値を保持するコンデンサと
、上記端子とこのコンデンサとの間の経路に挿入され、
このコンデンサを充電する電流を開閉側?111する制
御手段とを備えたピーク値保持回路において、上記制御
手段は、上記経路を開閉する開閉手段と、上記端子およ
び上記コンデンサの一端に二つの入力が接続され、その
出力がこの開閉手段の制御入力に接続された比較器とを
備えたことを特徴とする。
The present invention provides a terminal for inputting an analog signal, a capacitor that holds a value equivalent to the voltage peak value of this analog signal, and a capacitor inserted in a path between the terminal and this capacitor,
Is the current that charges this capacitor the opening/closing side? In the peak value holding circuit, the control means includes a switching means for opening and closing the passage, and two inputs are connected to the terminal and one end of the capacitor, and the output thereof is connected to the switching means for opening and closing the passage. and a comparator connected to the control input.

この開閉手段は半導体アナログスイッチであってもよい
This switching means may be a semiconductor analog switch.

〔作用〕[Effect]

アナログ入力電圧とコンデンサが保持している電圧との
大小が比較器で比較される。この比較結果に基づいてス
イッチの開閉が制御される。このスイッチ開閉の応答は
スイッチの等個直列抵抗とコンデンサとで構成される時
定数回路の時定数で支配されるので、この時定数を小さ
く設定すれば、コンデンサが保持するアナログ電圧のピ
ーク値をアナログ入力電圧の変化に確実に追従させるこ
とができる。
A comparator compares the analog input voltage and the voltage held by the capacitor. Opening and closing of the switch is controlled based on the comparison result. The response of this switch opening/closing is controlled by the time constant of the time constant circuit made up of the equal series resistance of the switch and the capacitor, so by setting this time constant to a small value, the peak value of the analog voltage held by the capacitor can be reduced. It is possible to reliably follow changes in analog input voltage.

〔実施例〕〔Example〕

以下、本発明実施例回路を図面に基づいて説明する。 Hereinafter, a circuit according to an embodiment of the present invention will be explained based on the drawings.

第1図は本発明第一実施例回路の構成を示す接続図であ
る。この第一実施例回路は、電圧保持コンデンサ1と、
アナログ入力電圧の入力端子10と、入力端子10と電
圧保持コンデンサ1との間の回路の開閉を行うスイッチ
2と、アナログ入力電圧■8と電圧保持コンデンサ1が
保持している電圧■1との大小を比較判定し、この比較
結果に基づいてスイッチ2の開閉を制御する比較器4と
、電圧保持コンデンサ1が保持している電圧■1を出力
する出力増幅器3と、出力端子20とを備える。図中、
符号5はスイッチ2が有する等個直列抵抗を示す。
FIG. 1 is a connection diagram showing the configuration of a circuit according to a first embodiment of the present invention. This first embodiment circuit includes a voltage holding capacitor 1,
An analog input voltage input terminal 10, a switch 2 that opens and closes the circuit between the input terminal 10 and the voltage holding capacitor 1, and a switch 2 that connects the analog input voltage (8) and the voltage (1) held by the voltage holding capacitor (1). It includes a comparator 4 that compares and determines the magnitude and controls the opening and closing of the switch 2 based on the comparison result, an output amplifier 3 that outputs the voltage 1 held by the voltage holding capacitor 1, and an output terminal 20. . In the figure,
Reference numeral 5 indicates equal series resistances that the switch 2 has.

次に、この実施例回路の動作を第1図に基づいて説明す
る。まず、スイッチ2が開状態で入力端子10にアナロ
グ入力電圧VXが印加されると、比較器4はアナログ入
力端子■、と電圧保持コンデンサ1が保持している電圧
■1との大小を比較判定する。このときに、アナログ入
力電圧■8が電圧保持コンデンサlが保持している電圧
V1より低い場合には、比較器4の出力は低レベルすな
わち論理「0」になり、スイッチ2は開状態を保つ。
Next, the operation of this embodiment circuit will be explained based on FIG. First, when the switch 2 is open and the analog input voltage VX is applied to the input terminal 10, the comparator 4 compares and determines the magnitude of the analog input terminal ■ and the voltage ■1 held by the voltage holding capacitor 1. do. At this time, if the analog input voltage ■8 is lower than the voltage V1 held by the voltage holding capacitor l, the output of the comparator 4 becomes a low level, that is, logic "0", and the switch 2 remains open. .

したがって、アナログ入力電圧■、の変化は電圧保持コ
ンデンサ1には影響を与えずに電圧保持コンデンサ1は
既に保持している電圧■、を持続する。一方、アナログ
入力電圧■、が電圧保持コンデンサ1が保持している電
圧■、より高い場合には、比較器4の出力は高レベルす
なわち論理「1」になって、スイッチ2は閉状態になる
。したがって、電圧保持コンデンサ1はスイッチ2を介
して充電される。ところで、スイッチ2には等個直列抵
抗5を伴うので、等個直列抵抗5と電圧保持コンデンサ
1とで時定数回路が構成され、電圧保持コンデンサ1が
保持している電圧■1はアナログ入力電圧VXの変化に
時定数回路で決まる時間だけ遅れて追従する。また、等
個直列抵抗5の両端には充電電流に相当の電位差が発生
する。この電位差はアナログ入力電圧■8がピーク値■
Xpに近づいて、アナログ入力電圧■つと電圧保持コン
デンサlが保持している電圧■1との差が小さくなるに
従って小さくなり、入力電圧VXがピーク値VX、に達
して入力電圧■8と電圧保持コンデンサlが保持してい
る電圧V、とが等しくなったときに、等個直列抵抗5の
両端に発生した電位差は零になり、比較器4の出力は反
転して低レベルすなわち論理「0」になる。これにより
スイッチ2は開状態になって入力端子10と電圧保持コ
ンデンサlとは切り離され、電圧保持コンデンサlはア
ナログ入力電圧VXのピーク値■X、の値にほぼ等しい
電圧を保持する。電圧保持コンデンサ1で保持した電圧
は非反転接続された利得1の出力増幅器3を介して出力
端子20から出力される。
Therefore, a change in the analog input voltage (2) does not affect the voltage holding capacitor 1, and the voltage holding capacitor 1 maintains the already held voltage (2). On the other hand, when the analog input voltage ■ is higher than the voltage held by the voltage holding capacitor 1, the output of the comparator 4 becomes a high level, that is, logic "1", and the switch 2 is closed. . Therefore, the voltage holding capacitor 1 is charged via the switch 2. By the way, since the switch 2 is accompanied by an equal number of series resistors 5, a time constant circuit is constituted by the equal number of series resistors 5 and the voltage holding capacitor 1, and the voltage 1 held by the voltage holding capacitor 1 is the analog input voltage. It follows the change in VX with a delay determined by the time constant circuit. Furthermore, a considerable potential difference occurs in the charging current across the equal number of series resistors 5. This potential difference is the analog input voltage ■8 is the peak value■
As the analog input voltage approaches Xp, the difference between the analog input voltage ■ and the voltage held by the voltage holding capacitor l becomes smaller, and the input voltage VX reaches the peak value VX, and the voltage is held at input voltage ■8. When the voltage V held by the capacitor l becomes equal, the potential difference generated across the equal number of series resistors 5 becomes zero, and the output of the comparator 4 is inverted and becomes a low level, that is, logic "0". become. As a result, the switch 2 becomes open, and the input terminal 10 is disconnected from the voltage holding capacitor 1, so that the voltage holding capacitor 1 holds a voltage approximately equal to the peak value XX of the analog input voltage VX. The voltage held by the voltage holding capacitor 1 is outputted from an output terminal 20 via an output amplifier 3 with a gain of 1 which is connected in a non-inverting manner.

第3図にアナログ入力電圧vXと、電圧保持コンデンサ
lが保持する電圧■1と、出力増幅器3の出力電圧Vp
の変化および比較器4の出力の変化をそれぞれ示す。
Figure 3 shows the analog input voltage vX, the voltage ■1 held by the voltage holding capacitor l, and the output voltage Vp of the output amplifier 3.
The changes in the output of the comparator 4 and the changes in the output of the comparator 4 are shown respectively.

第2図は本発明第二実施例回路の構成を示す回路接続図
である。第2図では、スイッチ2に半導体アナログスイ
ッチが用いられている。アナログスイッチを構成する半
導体素子としてP型MOSトランジスタ7とN型MOS
トランジスタ8とを並列に接続して使用し、P型Mos
トランジスタ7のゲートには比較器4の出力をインバー
タ6で反転して接続し、N型MoSトランジスタ8のゲ
ートには比較器4の出力がそのまま接続されている。半
導体アナログスイッチは導通状態でも数十オームから数
百オームの等個直列抵抗を持つので、第2図に示す回路
は第1図の回路と等価になる。
FIG. 2 is a circuit connection diagram showing the configuration of a circuit according to a second embodiment of the present invention. In FIG. 2, a semiconductor analog switch is used as the switch 2. A P-type MOS transistor 7 and an N-type MOS are used as semiconductor elements constituting the analog switch.
Transistor 8 is connected in parallel, and P-type Mos
The output of the comparator 4 is inverted by an inverter 6 and connected to the gate of the transistor 7, and the output of the comparator 4 is directly connected to the gate of the N-type MoS transistor 8. Since a semiconductor analog switch has an equal series resistance of several tens of ohms to several hundred ohms even in a conductive state, the circuit shown in FIG. 2 is equivalent to the circuit shown in FIG. 1.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように、アナログ入力端子と電圧
保持コンデンサとの間に等個直列抵抗を持つスイッチを
接続し、アナログ入力電圧と電圧保持コンデンサが保持
している電圧との大小を比較器で比較判定し、この比較
器の比較結果に基づいてスイッチの開閉を制御するので
、従来のピーク値保持回路のように整流器の闇値電圧を
補償するために出力増幅器の出力を帰還させる必要がな
く、したがって高速で動作する増幅器を必要とせず、ス
イッチの等個直列抵抗と電圧保持コンデンサとで構成さ
れる時定数回路の時定数を単に小さくすることで、アナ
ログ入力電圧が高速で変化しても電圧保持コンデンサが
保持する電圧をアナログ入力電圧の変化に確実に追従さ
せることができる効果がある。
As explained above, the present invention connects a switch having equal series resistance between an analog input terminal and a voltage holding capacitor, and uses a comparator to determine the magnitude of the analog input voltage and the voltage held by the voltage holding capacitor. Since the opening and closing of the switch is controlled based on the comparison result of this comparator, there is no need to feed back the output of the output amplifier to compensate for the dark value voltage of the rectifier, as in conventional peak value holding circuits. Therefore, the analog input voltage can be changed at high speed by simply reducing the time constant of the time constant circuit, which consists of an equal series resistance of the switch and a voltage holding capacitor, without requiring an amplifier that operates at high speed. This also has the effect that the voltage held by the voltage holding capacitor can reliably follow changes in the analog input voltage.

また、本発明では特殊な回路を必要としないので、比較
的構成の簡単なモノリシック集積回路で回路構成するこ
とが容易である効果がある。
Furthermore, since the present invention does not require any special circuit, it is advantageous in that it is easy to configure the circuit using a relatively simple monolithic integrated circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明第一実施例回路の構成を示す回路接続図
。 第2図は本発明第二実施例回路の構成を示す回路接続図
。 第3図は本発明実施例回路の各部の電圧の変化を示す波
形図。 第4図は従来例回路の構成を示す回路接続図。 第5図は従来例回路の各部の電圧の変化を示す波形図。 l、11・・・電圧保持コンデンサ、2・・・スイッチ
、3.13.14・・・増幅器、4・・・比較器、7.
8・・・MOSトランジスタ、1o・・・入力端子、1
5.16・・・整流器、20・・・出力端子。
FIG. 1 is a circuit connection diagram showing the configuration of a circuit according to a first embodiment of the present invention. FIG. 2 is a circuit connection diagram showing the configuration of a circuit according to a second embodiment of the present invention. FIG. 3 is a waveform diagram showing changes in voltage at various parts of the circuit according to the embodiment of the present invention. FIG. 4 is a circuit connection diagram showing the configuration of a conventional circuit. FIG. 5 is a waveform diagram showing changes in voltage at various parts of the conventional circuit. l, 11... Voltage holding capacitor, 2... Switch, 3.13.14... Amplifier, 4... Comparator, 7.
8...MOS transistor, 1o...input terminal, 1
5.16... Rectifier, 20... Output terminal.

Claims (1)

【特許請求の範囲】[Claims] (1)アナログ信号を入力する端子と、 このアナログ信号の電圧ピーク値の相当値を保持するコ
ンデンサと、 上記端子とこのコンデンサとの間の経路に挿入され、こ
のコンデンサを充電する電流を開閉制御する制御手段と を備えたピーク値保持回路において、 上記制御手段は、 上記経路を開閉する開閉手段と、 上記端子および上記コンデンサの一端に二つの入力が接
続され、その出力がこの開閉手段の制御入力に接続され
た比較器と を備えたことを特徴とするピーク値保持回路。(2)開
閉手段が半導体アナログスイッチである特許請求の範囲
第(1)項に記載のピーク値保持回路。
(1) A terminal that inputs an analog signal, a capacitor that holds a value equivalent to the voltage peak value of this analog signal, and a current that is inserted in the path between the above terminal and this capacitor and controls the opening and closing of the current that charges this capacitor. In the peak value holding circuit, the control means includes a switching means for opening and closing the passage, and two inputs connected to the terminal and one end of the capacitor, the output of which controls the switching means. A peak value holding circuit comprising: a comparator connected to an input. (2) The peak value holding circuit according to claim (1), wherein the opening/closing means is a semiconductor analog switch.
JP60249346A 1985-11-06 1985-11-06 Peak value holding circuit Pending JPS62109297A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60249346A JPS62109297A (en) 1985-11-06 1985-11-06 Peak value holding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60249346A JPS62109297A (en) 1985-11-06 1985-11-06 Peak value holding circuit

Publications (1)

Publication Number Publication Date
JPS62109297A true JPS62109297A (en) 1987-05-20

Family

ID=17191658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60249346A Pending JPS62109297A (en) 1985-11-06 1985-11-06 Peak value holding circuit

Country Status (1)

Country Link
JP (1) JPS62109297A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010187092A (en) * 2009-02-10 2010-08-26 Dkk Toa Corp Peak hold circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596334B2 (en) * 1976-01-16 1984-02-10 三井液化ガス 株式会社 Method and device for co-firing oil and gas

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596334B2 (en) * 1976-01-16 1984-02-10 三井液化ガス 株式会社 Method and device for co-firing oil and gas

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010187092A (en) * 2009-02-10 2010-08-26 Dkk Toa Corp Peak hold circuit

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