JPS62109297A - Peak value holding circuit - Google Patents

Abstract

PURPOSE:To hold a peak value following steadily to the change at high speed of an analog input voltage by opening/closing the charging current of a capacitor based on a result in which a size between the analog input voltage and a voltage held by the capacitor is compared. CONSTITUTION:Since a switch 2 is accompanied by an equivalent series resis tance 5, a time constant circuit is constituted with the equivalent series resis tance 5 and a voltage holding capacitor 1, and a voltage V1 held by the voltage holding capacitor 1 follows the change of an analog input voltage Vx delaying by time decided at the time constant circuit. When the input voltage Vx reaches its peak value Vxp and the input voltage Vx coincides with the voltage V1 held by the voltage holding capacitor 1, a potential difference generated at both ends of the equivalent series resistance 5 becomes zero, and the output of a comparator 4 is inverted, thereby becoming a low level. Thereby, the switch 2 is placed in an open state, and an input terminal 10 and the voltage holding capacitor 1 are separated, and the voltage holding capacitor 1 holds the voltage almost equivalent to the value of the peak value Vxp of the analog input voltage Vx.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak value holding circuit using a capacitor.

〔overview〕

The present invention has a peak value holding circuit that causes a capacitor to hold the peak value of an analog signal, and opens and closes the charging current of the capacitor based on the result of comparing the analog input voltage with the voltage held by the capacitor. This makes it possible to realize a peak value holding circuit that can reliably follow high-speed changes in analog input voltage and hold the peak value using a monolithic integrated circuit.

[Conventional technology]

In a conventional peak value holding circuit using a capacitor and an amplifier, the capacitor is charged via an amplifier that rectifies the analog input voltage, and if the analog input voltage is lower than the voltage held by the capacitor, the amplifier is The rectification action prevents the circuit from conducting, and the capacitor continues to maintain the holding voltage. On the other hand, if the analog input voltage is higher than the voltage held by the capacitor, the circuit conducts due to the rectifying action of the amplifier, charging the capacitor up to the analog input voltage and reducing the voltage at the analog input applied so far. The maximum voltage value is held in the capacitor.

A conventional peak value holding circuit using a capacitor and an amplifier is shown in FIG. This circuit includes a voltage holding capacitor 11,
Amplifiers 13 and 14, rectifiers 15 and 16, input terminal 10 of analog input voltage VX, and peak value voltage ■
2 output terminals 20. Here, amplifiers 13 and 14 are each non-inverting amplifier circuits with a gain of 1, and the output of amplifier 14 is also connected to the inverting input terminal of amplifier 13. First, when analog input voltage VX is applied to input terminal 10, output voltage 2 of amplifier 13 becomes equal to vX. At this time, if the value of the output voltage (2) of the amplifier 13 is higher than the voltage (2) held by the voltage holding capacitor 11, the rectifier 16 becomes conductive and the voltage holding capacitor 11 is further charged. However, since charging is performed via the rectifier 16, the voltage of the voltage holding capacitor 11 is charged only to a value lower than the output voltage (2) of the amplifier 13 by the dark value voltage (2) of the rectifier, that is, (Vz Vt). By the way, the output voltage V2 of the amplifier 13 is equal to the analog input voltage ■8, and the output voltage Vp of the amplifier 14 is equal to ■1, so the output voltage ■, of the amplifier 14 is (■, V
t). On the other hand, since the output of the amplifier 14 is fed back to the inverting input terminal of the amplifier 13, the voltage applied to the inverting input terminal of the amplifier 13 becomes the output voltage V of the amplifier 14, that is, (V-Vt). Since the voltage applied to the non-inverting input terminal of the amplifier 13 is the analog input voltage ■8, the amplifier 13
The voltages applied to the inverting input terminal and the non-inverting input terminal of are in an unbalanced state, and the difference in the applied voltages becomes ■A. therefore,
The output voltage of the amplifier 13 changes depending on the difference in voltage applied to the inverting input terminal and the non-inverting input terminal. Changes in the output voltage of amplifier 13 are fed back to the inverting input terminal of amplifier 13 via amplifier 14 . When the voltage applied to the inverting input terminal of the amplifier 13 becomes equal to the analog input voltage v, I, an equilibrium state is reached and the output voltage of the amplifier 13 stops changing. Finally, the value of the output voltage ■2 of the amplifier 13 is (v, +vT)
Therefore, the value of the voltage V1 held by the voltage holding capacitor 11 becomes V,l, which is equal to the analog input voltage. Therefore, if the maximum value of the analog input voltage VX is VXp, the voltage held by the voltage holding capacitor 11 (1) increases to XX, and the output voltage (2) of the amplifier 14 also increases to VXp. At this time, the output voltage ■2 of the amplifier 13 is
(VXp+V,) due to the feedback action from. Next, when the analog input voltage ■8 becomes lower than the maximum value VX9, the output voltage V2 of the amplifier 13 becomes (Vxp”VT
), the rectifier 16 becomes reverse biased and non-conducting. Therefore, the change in the input terminal is not transmitted to the voltage holding capacitor 11, and the voltage holding capacitor continues to hold the maximum value of the analog input voltage, ■X. Here, the rectifier 15 is clamped so that the output of the amplifier 13 does not swing to the negative side when the analog input terminal 8 becomes negative.

[Problem that the invention seeks to solve]

In such a conventional peak value holding circuit, the threshold voltage (a) of the rectifier 16 is corrected by feeding back the output of the amplifier 14 to the amplifier 13, so the final balance is adjusted after the analog input voltage changes. By the time the state is reached, the amplifier 13
The output of the amplifier 14 changes, and the voltage holding capacitor 11 is charged via the rectifier 16, and the output of the amplifier 14 changes, and the output of the amplifier 14 is fed back to the input of the amplifier 13, so that the output of the amplifier 13 is further changed. Repeat the feedback action of change. Therefore, as the frequency of the analog input becomes higher and the voltage changes faster, the feedback operation needs to operate at a higher speed, and it becomes necessary to use high-speed amplifiers for the amplifiers 13 and 14. When the frequency of the analog input increases and the voltage changes quickly, the operating speed of the amplifier is insufficient and the feedback operation cannot follow the changes in the analog input. Since the analog input terminal VX changes quickly and the feedback operation cannot follow the changes in the analog input, the voltage held by the voltage holding capacitor 11 and the output voltage Vp of the amplifier 14 are the peak value of the analog voltage 8. X9 cannot be reached, resulting in an error as shown in Figure 5.In other words, in the conventional peak value holding circuit, when the analog input frequency becomes high and the voltage changes quickly, it is difficult to prevent the error from occurring. The circuit of such an amplifier is complicated, and when the peak value holding circuit is integrated into a monolithic circuit, the chip area and power consumption increase.

The present invention eliminates these drawbacks, does not use an amplifier circuit with a rectifier, has a simple feedback circuit, and is suitable for high-speed monolithic integration consisting only of MOS transistor structures. The purpose of the present invention is to provide a peak value holding circuit that can operate at

[Means for solving problems]

The present invention provides a terminal for inputting an analog signal, a capacitor that holds a value equivalent to the voltage peak value of this analog signal, and a capacitor inserted in a path between the terminal and this capacitor,
Is the current that charges this capacitor the opening/closing side? In the peak value holding circuit, the control means includes a switching means for opening and closing the passage, and two inputs are connected to the terminal and one end of the capacitor, and the output thereof is connected to the switching means for opening and closing the passage. and a comparator connected to the control input.

This switching means may be a semiconductor analog switch.

[Effect]

A comparator compares the analog input voltage and the voltage held by the capacitor. Opening and closing of the switch is controlled based on the comparison result. The response of this switch opening/closing is controlled by the time constant of the time constant circuit made up of the equal series resistance of the switch and the capacitor, so by setting this time constant to a small value, the peak value of the analog voltage held by the capacitor can be reduced. It is possible to reliably follow changes in analog input voltage.

〔Example〕

Hereinafter, a circuit according to an embodiment of the present invention will be explained based on the drawings.

FIG. 1 is a connection diagram showing the configuration of a circuit according to a first embodiment of the present invention. This first embodiment circuit includes a voltage holding capacitor 1,
An analog input voltage input terminal 10, a switch 2 that opens and closes the circuit between the input terminal 10 and the voltage holding capacitor 1, and a switch 2 that connects the analog input voltage (8) and the voltage (1) held by the voltage holding capacitor (1). It includes a comparator 4 that compares and determines the magnitude and controls the opening and closing of the switch 2 based on the comparison result, an output amplifier 3 that outputs the voltage 1 held by the voltage holding capacitor 1, and an output terminal 20. . In the figure,
Reference numeral 5 indicates equal series resistances that the switch 2 has.

Next, the operation of this embodiment circuit will be explained based on FIG. First, when the switch 2 is open and the analog input voltage VX is applied to the input terminal 10, the comparator 4 compares and determines the magnitude of the analog input terminal ■ and the voltage ■1 held by the voltage holding capacitor 1. do. At this time, if the analog input voltage ■8 is lower than the voltage V1 held by the voltage holding capacitor l, the output of the comparator 4 becomes a low level, that is, logic "0", and the switch 2 remains open. .

Therefore, a change in the analog input voltage (2) does not affect the voltage holding capacitor 1, and the voltage holding capacitor 1 maintains the already held voltage (2). On the other hand, when the analog input voltage ■ is higher than the voltage held by the voltage holding capacitor 1, the output of the comparator 4 becomes a high level, that is, logic "1", and the switch 2 is closed. . Therefore, the voltage holding capacitor 1 is charged via the switch 2. By the way, since the switch 2 is accompanied by an equal number of series resistors 5, a time constant circuit is constituted by the equal number of series resistors 5 and the voltage holding capacitor 1, and the voltage 1 held by the voltage holding capacitor 1 is the analog input voltage. It follows the change in VX with a delay determined by the time constant circuit. Furthermore, a considerable potential difference occurs in the charging current across the equal number of series resistors 5. This potential difference is the analog input voltage ■8 is the peak value■
As the analog input voltage approaches Xp, the difference between the analog input voltage ■ and the voltage held by the voltage holding capacitor l becomes smaller, and the input voltage VX reaches the peak value VX, and the voltage is held at input voltage ■8. When the voltage V held by the capacitor l becomes equal, the potential difference generated across the equal number of series resistors 5 becomes zero, and the output of the comparator 4 is inverted and becomes a low level, that is, logic "0". become. As a result, the switch 2 becomes open, and the input terminal 10 is disconnected from the voltage holding capacitor 1, so that the voltage holding capacitor 1 holds a voltage approximately equal to the peak value XX of the analog input voltage VX. The voltage held by the voltage holding capacitor 1 is outputted from an output terminal 20 via an output amplifier 3 with a gain of 1 which is connected in a non-inverting manner.

Figure 3 shows the analog input voltage vX, the voltage ■1 held by the voltage holding capacitor l, and the output voltage Vp of the output amplifier 3.
The changes in the output of the comparator 4 and the changes in the output of the comparator 4 are shown respectively.

FIG. 2 is a circuit connection diagram showing the configuration of a circuit according to a second embodiment of the present invention. In FIG. 2, a semiconductor analog switch is used as the switch 2. A P-type MOS transistor 7 and an N-type MOS are used as semiconductor elements constituting the analog switch.
Transistor 8 is connected in parallel, and P-type Mos
The output of the comparator 4 is inverted by an inverter 6 and connected to the gate of the transistor 7, and the output of the comparator 4 is directly connected to the gate of the N-type MoS transistor 8. Since a semiconductor analog switch has an equal series resistance of several tens of ohms to several hundred ohms even in a conductive state, the circuit shown in FIG. 2 is equivalent to the circuit shown in FIG. 1.

〔Effect of the invention〕

As explained above, the present invention connects a switch having equal series resistance between an analog input terminal and a voltage holding capacitor, and uses a comparator to determine the magnitude of the analog input voltage and the voltage held by the voltage holding capacitor. Since the opening and closing of the switch is controlled based on the comparison result of this comparator, there is no need to feed back the output of the output amplifier to compensate for the dark value voltage of the rectifier, as in conventional peak value holding circuits. Therefore, the analog input voltage can be changed at high speed by simply reducing the time constant of the time constant circuit, which consists of an equal series resistance of the switch and a voltage holding capacitor, without requiring an amplifier that operates at high speed. This also has the effect that the voltage held by the voltage holding capacitor can reliably follow changes in the analog input voltage.

Furthermore, since the present invention does not require any special circuit, it is advantageous in that it is easy to configure the circuit using a relatively simple monolithic integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing the configuration of a circuit according to a first embodiment of the present invention. FIG. 2 is a circuit connection diagram showing the configuration of a circuit according to a second embodiment of the present invention. FIG. 3 is a waveform diagram showing changes in voltage at various parts of the circuit according to the embodiment of the present invention. FIG. 4 is a circuit connection diagram showing the configuration of a conventional circuit. FIG. 5 is a waveform diagram showing changes in voltage at various parts of the conventional circuit. l, 11... Voltage holding capacitor, 2... Switch, 3.13.14... Amplifier, 4... Comparator, 7.
8...MOS transistor, 1o...input terminal, 1
5.16... Rectifier, 20... Output terminal.

Claims (1)

[Claims] (1) A terminal that inputs an analog signal, a capacitor that holds a value equivalent to the voltage peak value of this analog signal, and a current that is inserted in the path between the above terminal and this capacitor and controls the opening and closing of the current that charges this capacitor. In the peak value holding circuit, the control means includes a switching means for opening and closing the passage, and two inputs connected to the terminal and one end of the capacitor, the output of which controls the switching means. A peak value holding circuit comprising: a comparator connected to an input. (2) The peak value holding circuit according to claim (1), wherein the opening/closing means is a semiconductor analog switch.